JPS6068641A - Mounting method of semiconductor device - Google Patents
Mounting method of semiconductor deviceInfo
- Publication number
- JPS6068641A JPS6068641A JP59176660A JP17666084A JPS6068641A JP S6068641 A JPS6068641 A JP S6068641A JP 59176660 A JP59176660 A JP 59176660A JP 17666084 A JP17666084 A JP 17666084A JP S6068641 A JPS6068641 A JP S6068641A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- semiconductor device
- mounting
- envelope
- folded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は配線基板への半導体装置の実装方法に関する。[Detailed description of the invention] The present invention relates to a method for mounting a semiconductor device onto a wiring board.
一般に、半導体装置をプリント基板のような配線基板に
取り付ける実装方法の１つとしては、第１図に示すよう
に、半導体装置Ｊの外囲器２の側面から延びる屈曲した
複数のり一部３を外囲器の下面と平向となる方向に延在
させ、各リード３をプリント基板４の配線層５における
端子（ランド）６に重ね合せ、その後あらかじめランド
６やリード表面に付着させておいたろう材としての半田
を一時的に溶融させてランド６とり−ド３とを半田７で
接合する方法が採用されている。Generally, one mounting method for attaching a semiconductor device to a wiring board such as a printed circuit board is to attach a plurality of bent glue portions 3 extending from the side surface of an envelope 2 of a semiconductor device J, as shown in FIG. The leads 3 are made to extend in a direction parallel to the bottom surface of the envelope, and each lead 3 is overlapped with a terminal (land) 6 in the wiring layer 5 of the printed circuit board 4, and then attached to the land 6 and the lead surface in advance. A method is adopted in which the solder material is temporarily melted and the lands 6 and the leads 3 are joined with the solder 7.
しかし、この実装方法では、外囲器の側面から長く延び
るリード部分を介してプリント基板に半導体装置を取り
付けるため、同図で示すよ’＞ ’ＶＣ１取付幅ｐが大
きく、実装面績が広くなる欠点がある。However, in this mounting method, the semiconductor device is attached to the printed circuit board via the lead part extending long from the side of the envelope, so as shown in the figure, the VC1 mounting width p is large and the mounting area is wide. There are drawbacks.
例えば、取付幅の大きくなる半導体装置は、特開昭５３
−８１０７６号に開示されている。For example, semiconductor devices with large mounting widths are
-81076.
他方、本出願人は第２図で示すように、レジンからなる
外囲器（モールド部）８の中央上部が高く、その周辺部
が一段低い構造のレジンモールド型の半導体装置９を提
案している。これは、モールド部に気泡が発生したり、
外観不良となることを防止するために考えられた形状で
ある。すなわち、従来のレジンモールド型半導体装置に
あっては回路素子を形作るペレット（半導体素子）やリ
ードの内端部を被うレジンからなるモールド部は上面お
よび下面がそれぞれ平坦となるほぼ直方体の形状となっ
ている。また、製品によっては、他部局面が上下から斜
めに突出し合い中央で突き合せ状態となっている。しか
し、このような形状では、特にモールド部の薄型化を図
れば図るほど、レジンモールド時にペレットの上面のモ
ールド空間が周囲に較べて薄くなり、この空間内を流れ
るレジンの流れがペレットの側面部に沿って流れるレジ
ンの流れに較べてその流速が遅くなるため、ペレット上
面を流れるレジンが完全にペレット上を流れ終わらない
うちに、リード上下面（ペレット側面部）を流れるレジ
ンおよびペレット下方を流れるレジンが早く流れてペレ
ットを取り囲む状態となる。この結果、ベレット上面の
空気が抜けずに気泡となり、モールド内部に残留して耐
湿性の低下を来たしたり、モールド表面に残留して窪み
となり外観不良となる。そこで、本出願人は、モールド
型におけるモールド空間において、ペレット】０の上面
を流れるレジンの流速およびペレットの周囲を回り込む
ようにして流れるレジンの流速をほぼ近似させ、ベレッ
ト上面の空気が確実に抜けるように、ペレット周囲のリ
ード１１の上下にあっては、モールド空間の厚さく高さ
）を薄くしてレジンの流れ抵抗を増大させることを考え
に０そして、この結果の一つとして、同図で示すような
モールド部８の上面が二段形せをした半導体装置の出現
となった。この段差はほぼ０．５ ｍ前後であり、モー
ルド部の全体の厚さはほぼ１．５ｎ前後となる。また、
リードの厚さは０．１５ｆ？ｉ、と極めて薄い。On the other hand, as shown in FIG. 2, the present applicant has proposed a resin mold type semiconductor device 9 in which an envelope (mold part) 8 made of resin has a structure in which the central upper part is high and the peripheral part is one level lower. There is. This may cause air bubbles to form in the mold, or
This shape was designed to prevent poor appearance. In other words, in conventional resin-molded semiconductor devices, the pellet (semiconductor element) that forms the circuit element and the mold part made of resin that covers the inner ends of the leads have a substantially rectangular parallelepiped shape with flat top and bottom surfaces. It has become. Further, depending on the product, other parts protrude diagonally from above and below and are butted in the center. However, with such a shape, the more you try to make the mold part thinner, the more the mold space on the top surface of the pellet becomes thinner than the surrounding area during resin molding, and the flow of resin flowing in this space will flow more closely to the side surfaces of the pellet. Because the flow speed is slower than that of the resin flowing along the lead, before the resin flowing on the upper surface of the pellet has completely flowed over the pellet, the resin flowing on the upper and lower surfaces of the reed (the side surface of the pellet) and flowing below the pellet. The resin flows quickly and surrounds the pellet. As a result, the air on the upper surface of the pellet does not escape and becomes bubbles, which remain inside the mold and cause a decrease in moisture resistance, or remain on the mold surface and form depressions, resulting in poor appearance. Therefore, the present applicant approximated the flow velocity of the resin flowing on the upper surface of the pellet 0 and the flow velocity of the resin flowing around the pellet in the mold space of the mold, thereby ensuring that the air on the upper surface of the pellet was evacuated. As shown in the figure, one of the results of this is to reduce the thickness and height of the mold space above and below the lead 11 around the pellet to increase the flow resistance of the resin. This led to the appearance of semiconductor devices in which the upper surface of the mold portion 8 was shaped in two stages as shown in FIG. This level difference is approximately 0.5 m, and the total thickness of the molded portion is approximately 1.5 nm. Also,
Is the lead thickness 0.15f? i, extremely thin.
そこで、本発明者は外囲器から延びるリードを外囲器の
付は根部分で折り返し、リードの先端部を外囲器の周辺
部に沿って延在させることによって取付高さを増大させ
ることなく、かつ実装面積を小さくすることができるこ
とに気が付き本発明を成した。Therefore, the present inventor has developed a method to increase the installation height by folding back the lead extending from the envelope at the base of the envelope and extending the tip of the lead along the periphery of the envelope. The present invention was realized based on the realization that the mounting area can be reduced.
したがって、本発明の目的は配線基板への半導体装置の
実装方法において実装面積、実装高さを小さくできる実
装方法を提供することにある。Therefore, an object of the present invention is to provide a method for mounting a semiconductor device onto a wiring board, which can reduce the mounting area and mounting height.
このような目的を達成するために本発明は、中央部に半
導体素子をレジン封止した外囲器と外囲器の側面から延
びる複数のリードとを有する半導体装置における各リー
ドを配線基板の所定の端子とを電気接続する半導体装置
の実装方法において、前記半導体装置にあってはリード
を外囲器の付は根近傍で折り返し前記半導体素子周辺部
の外囲器の表面に沿って延在させておき、前記配線基板
にあっては前記折り返し延在したリードの一部に対応し
て配線層の端子を配設しておき、実装時には前記端子に
前記折り返し延在したリードの一部を重ね合せて前記半
導体装置を配線基板に取り付けることを特徴とする半導
体装置の実装方法であって以下実施例により本発明を具
体的に説明する。In order to achieve such an object, the present invention provides a semiconductor device having an envelope in which a semiconductor element is sealed with resin in the center and a plurality of leads extending from the sides of the envelope. In the semiconductor device mounting method for electrically connecting terminals of the semiconductor device, the leads of the semiconductor device are folded back near the base of the envelope and extended along the surface of the envelope around the semiconductor element. Then, on the wiring board, a terminal of the wiring layer is arranged corresponding to a part of the folded and extended lead, and when mounting, a part of the folded and extended lead is overlapped with the terminal. There is also a method for mounting a semiconductor device, characterized in that the semiconductor device is mounted on a wiring board, and the present invention will be specifically described below with reference to Examples.
第３図は本発明の半導体装置の実装方法により実装され
た半導体装置の状態を示す。このような状態に実装する
ためには、まず第２図で示すと同様な形状の半導体装置
１２を用意する。すなわち、モールド部１３のベレ、ッ
ト（半導体素子）の上部が周辺部１４よりもほぼＱ、
５１ｔ’Ｌ前後高い高台部分１５となるレジンモールド
型の半導体装置１２を製造するとともに、モールド部１
３の側面から延びるリード１７をモールド部１３の付は
根部分で上方に折り返し、リード先端部をモールド部１
３の低い周辺部１４上に延在させておく。この折返り一
ド部１８の上面はモールド部Ｊ３の上面（高台部分の上
面）と同一となっている。また、プリント基板１９にあ
っては、表面の配線層２０の端子（ランド）２１は前記
半導体装置１２の折返リード部１８と対応するように配
設されている。また、モールド部１３の側面から突出す
るり一ド１７０表面や、プリント基板１９０表面に設け
た配線層２００表面にはあらかじめ半田をディップして
おく。そして、半導体装置１２の実装時にＧ′！。FIG. 3 shows the state of a semiconductor device mounted by the semiconductor device mounting method of the present invention. In order to mount the semiconductor device in such a state, first, a semiconductor device 12 having a shape similar to that shown in FIG. 2 is prepared. That is, the upper part of the bevel of the mold part 13 (semiconductor element) is approximately Q, lower than the peripheral part 14.
A resin mold type semiconductor device 12 is manufactured which will become a high platform part 15 around 51t'L, and the mold part 1 is
The lead 17 extending from the side surface of the mold part 13 is folded back upward at the base of the mold part 13, and the tip of the lead is attached to the mold part 1.
3 and extend over the lower peripheral portion 14 of 3. The upper surface of this folded portion 18 is the same as the upper surface of the molded portion J3 (the upper surface of the elevated portion). Further, in the printed circuit board 19, terminals (lands) 21 of the wiring layer 20 on the front surface are arranged to correspond to the folded lead portions 18 of the semiconductor device 12. Further, the surface of the glue 170 protruding from the side surface of the mold part 13 and the surface of the wiring layer 200 provided on the surface of the printed circuit board 190 are dipped in solder in advance. Then, when the semiconductor device 12 is mounted, G'! .
リード１７の折返リード部１８をプリント基板１９のラ
ンド２１に重ね、この状態で全体加熱あるいは部分加熱
によって配線層２０およびリード１７に付着している半
田を一時的に溶かし、半田２２によって配線層２０のラ
ンド２ｊとこれに重なる折返リード部１Ｂとを接続し、
実装を完了する。The folded lead portion 18 of the lead 17 is placed on the land 21 of the printed circuit board 19, and in this state, the solder adhering to the wiring layer 20 and the lead 17 is temporarily melted by heating the whole or part of the wiring layer 20, and the solder 22 is applied to the wiring layer 20. Connect the land 2j and the folded lead part 1B overlapping this,
Complete the implementation.
このような実施例によれば、モールド部の両側から延び
る複数のリードはモールド部の付は根部分から段付部側
に折り返され、その折返リード部でプリント基板の配線
層に接続されるため、取付幅（Ｌ）が従来に較べて数訪
狭くなる。この際、モールド部の高台部分の上面をプリ
ント基板面に接触させるよ５にすれば、従来と同様な取
付高さを維持できる。According to this embodiment, the plurality of leads extending from both sides of the molded part are folded back from the base of the molded part toward the stepped part, and connected to the wiring layer of the printed circuit board at the folded lead part. The mounting width (L) is several times narrower than before. At this time, if the upper surface of the elevated part of the mold part is brought into contact with the printed circuit board surface, the mounting height similar to the conventional one can be maintained.
なお、本発明は前記実施例に限定されない。すなわち、
第３図に示すように、プリント基板１９０半導体装置取
付面にモールド部１３の高台部分】５が入る窪み２３を
設け、実装時にはこの窪み２３内にモールド部Ｊ３の高
台部分１５を一部挿入させるようにすることによって、
実装高さくｈ）を従来のようなモールド部１３の厚さく
高さ）（Ｈ）に較べて低くすることができる。この際、
窪み２３を設けたプリント基板の窪み領域の表面や内部
には従来と同様に配線層２４を設け、プリント基板にお
ける配線層密度の低下を来たさないようにし、窪みを設
けることによってプリント基板が大型化するのを防止す
る、１
また、半導体装置としては、レジンモールド型に限らず
、ガラスセラミックパッケージ型等であってもよい。ま
た、配線基板としては、プリント基板に限定されるもの
ではなく、セラミ’７り基板等地の配線基板であっても
よい。Note that the present invention is not limited to the above embodiments. That is,
As shown in FIG. 3, a recess 23 is provided on the semiconductor device mounting surface of the printed circuit board 190 into which the elevated portion 5 of the mold portion 13 is inserted, and the elevated portion 15 of the mold portion J3 is partially inserted into this recess 23 during mounting. By doing so,
The mounting height (h) can be made lower than the thickness (H) (H) of the mold portion 13 as in the prior art. On this occasion,
A wiring layer 24 is provided on the surface and inside of the recessed area of the printed circuit board in which the recess 23 is provided, as in the conventional case, so as to prevent a decrease in the wiring layer density in the printed circuit board, and by providing the recess, the printed circuit board is Preventing enlargement (1) Furthermore, the semiconductor device is not limited to a resin mold type, but may be a glass ceramic package type or the like. Further, the wiring board is not limited to a printed circuit board, and may be a wiring board made of a ceramic substrate or the like.
以上のように、本発明の半導体装置の実装方法によれば
、実装高さを増加させることなく実装面積の縮小化を図
ることができるので、この方法によれば、半導体装置を
組み込む各種装置７機器の小型化を図ることができる。As described above, according to the semiconductor device mounting method of the present invention, it is possible to reduce the mounting area without increasing the mounting height. It is possible to downsize the device.
また、本発明によれば、プリント基板に高台部分嵌合用
の窪みを設けることによって、実装高さを低くでき、こ
の方法の採用による各種装荷９機器の薄型化も図れる等
多くの効果を奏する。Further, according to the present invention, the mounting height can be lowered by providing a recess for fitting the elevated part on the printed circuit board, and by adopting this method, various loaded devices can be made thinner, and many other effects can be achieved.
第１図は従来の半導体装置の実装方法を示ず一部断面図
、第２図は本出願人提案によるレジンモールド型半導体
装置の外観図、第３図は本発明の半導体装置の実装方法
の一実施例による一部断面図、第４図は本発明の他の実
施例による一部断面図である。
Ｊ・・・半導体装置、２・・・外囲器、３・・・リード
、４・・・プリント基板、５・・・配線Ｊｆｉ、６・・
・端子（ラント）ｉ・・・半田、８・・・モールド部、
９・・・半導体装置、１０・・・ベレット、】１・・・
リード、１２・・・半導体装置、ｊ３・・・モールド部
、１４・・・周辺部、】５−高台部分、】７・・・リー
ド、１８・・・折返リード部、】９・・・プリント基板
、２０・・・配線層、２１・・・端子（ランド）、２２
・・・半田、２３・・・窪み、２４・・・配線層。
第 １ 図
？FIG. 1 is a partial cross-sectional view showing a conventional semiconductor device mounting method, FIG. 2 is an external view of a resin molded semiconductor device proposed by the applicant, and FIG. 3 is a partial cross-sectional view of a conventional semiconductor device mounting method. FIG. 4 is a partial cross-sectional view of another embodiment of the present invention. J...Semiconductor device, 2...Envelope, 3...Lead, 4...Printed circuit board, 5...Wiring Jfi, 6...
・Terminal (runt) i...Solder, 8...Mold part,
9...Semiconductor device, 10...Bellet, ]1...
Lead, 12...Semiconductor device, j3...Mold part, 14...Peripheral part, ]5-High ground part, ]7...Lead, 18...Folded lead part, ]9...Print Substrate, 20... Wiring layer, 21... Terminal (land), 22
. . . solder, 23 . . . depression, 24 . . . wiring layer. Figure 1?
Claims (1)
器の側面から延びる複数のリードとを有する半導体装置
における各リードを配線基板の所定の端子とを電気接続
する半導体装置の実装方法において、前記半導体装置に
あってはリードを外囲器の付は根近傍で折り返し前記半
導体素子周辺部の外囲器の表面に沿って延在させておき
、前記配線基板にあっては前記折り返し延在したリード
の一部に対応して配線Ｍの端子を配設しておき、実装時
には前記端子に前記折り返し延在したリードの一部を重
ね合せて前記半導体装置を配線基板に取り付けることを
特徴とする半導体装置の実装方法。1. Mounting of a semiconductor device in which each lead is electrically connected to a predetermined terminal of a wiring board in a semiconductor device having an envelope in which a semiconductor element is resin-sealed in the center and a plurality of leads extending from the sides of the envelope. In the method, in the semiconductor device, the leads are folded back near the root of the envelope and extended along the surface of the envelope in the peripheral area of the semiconductor element; Terminals of the wiring M are arranged corresponding to the portions of the folded and extended leads, and during mounting, the semiconductor device is mounted on a wiring board by overlapping the portion of the folded and extended leads on the terminals. A method for mounting a semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59176660A JPS6068641A (en) | 1984-08-27 | 1984-08-27 | Mounting method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59176660A JPS6068641A (en) | 1984-08-27 | 1984-08-27 | Mounting method of semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9360678A Division JPS5521127A (en) | 1978-08-02 | 1978-08-02 | Method of mounting semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6068641A true JPS6068641A (en) | 1985-04-19 |
Family
ID=16017469
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59176660A Pending JPS6068641A (en) | 1984-08-27 | 1984-08-27 | Mounting method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6068641A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0843326A2 (en) * | 1996-11-19 | 1998-05-20 | Nec Corporation | Chip type electronic part |
-
1984
- 1984-08-27 JP JP59176660A patent/JPS6068641A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0843326A2 (en) * | 1996-11-19 | 1998-05-20 | Nec Corporation | Chip type electronic part |
| EP0843326A3 (en) * | 1996-11-19 | 1999-08-25 | Nec Corporation | Chip type electronic part |
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