JPS6066424A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6066424A
JPS6066424A JP17530883A JP17530883A JPS6066424A JP S6066424 A JPS6066424 A JP S6066424A JP 17530883 A JP17530883 A JP 17530883A JP 17530883 A JP17530883 A JP 17530883A JP S6066424 A JPS6066424 A JP S6066424A
Authority
JP
Japan
Prior art keywords
resist
photo
semiconductor substrate
photoresist
ion implantation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17530883A
Other languages
Japanese (ja)
Inventor
Takashi Hirose
貴司 廣瀬
Hiroshi Yamazoe
山添 博司
Atsushi Nakagawa
敦 中川
Ichiro Yamashita
一郎 山下
Yoshinobu Murakami
嘉信 村上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP17530883A priority Critical patent/JPS6066424A/en
Publication of JPS6066424A publication Critical patent/JPS6066424A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Health & Medical Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To remove a photo-resist without using mechanical operation, to reduce the possibility of the damage of a substrate and to improve yield by providing a process, etc. using a non-proton solvent having high dipole moment on the removal of the photo-resist after selective ion implantation. CONSTITUTION:A positive type photo-resist is applied on the surface of a substrate 1, patterned according to a required shape and used as a mask to implanted ions 3. Silicon ions are implanted selectively as implanted ions 3 to form a semiconductor substrate active section 4 to the semiconductor substrate 1. Most of the positive type photo-resist 21 are eluted by dipping the semiconductor substrate 1, on which the positive type photo-resist 21 is applied, in dimethylformamide(DMF) as a non-proton solution having high dipole moment. Photo-resist residue 21a is removed simply by further dipping the substrate in a photo- resist removing agent as a conventional photo-resist removing method.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、半導体装置の製造工程における1選択イオン
注入後のポジ型フォトレジストの除去に用いることので
きる半導体装置の製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device that can be used to remove positive photoresist after selective ion implantation in the manufacturing process of a semiconductor device.

従来例の構成とその問題点 近年、半導体装置のp型もしくはn型領域を作製する方
法として、イオン注入が用いられてきている。以下図を
を参照しながら従来の半導体装置の製造方法について説
明する。第1図(a) 、 (b) 、 (C)。
Conventional Structures and Their Problems In recent years, ion implantation has been used as a method for manufacturing p-type or n-type regions of semiconductor devices. A conventional method for manufacturing a semiconductor device will be described below with reference to the drawings. Figure 1 (a), (b), (C).

(d)は、従来の半導体装置の製造方法の工程断面図で
あり、1は半導体基板、2は注入イオン3に対する選択
マスクとなるフォトレジスト。2aはフォトレジスト残
渣。4は注入イオン3による半導体基板活性部である。
(d) is a process cross-sectional view of a conventional method for manufacturing a semiconductor device, in which 1 is a semiconductor substrate, 2 is a photoresist serving as a selective mask for implanted ions 3; 2a is photoresist residue. Reference numeral 4 denotes an active region of the semiconductor substrate formed by the implanted ions 3.

以上のように構成された半導体装置の製造方法について
以下に説明する。
A method of manufacturing the semiconductor device configured as above will be described below.

前記イオン?IE入tよ、J’)’r’J2の不純物を
イオン化し。
Said ion? Enter IE and ionize the impurities in J')'r'J2.

イオン加速器を用いて半導体基板に杓込みその後の熱処
理にJニジ前記不純物を活性化し、p型もしくはn型半
導体を得るものである。ところで、前記イオン注入は、
しばしば半導体の集積化のため。
The impurity is poured into a semiconductor substrate using an ion accelerator and then subjected to heat treatment to activate the impurity to obtain a p-type or n-type semiconductor. By the way, the ion implantation is
Often for semiconductor integration.

同一半導体基板内に異種もしくは注入量の異なった不純
物の注入が必要となるため、半導体基板1上の7オトレ
ジスト2をマスクとして、注入イオン3の選択イオン注
入が行なわれる(第1図(a))。
Since it is necessary to implant different types of impurities or different amounts of impurities into the same semiconductor substrate, selective ion implantation of implanted ions 3 is performed using the photoresist 2 on the semiconductor substrate 1 as a mask (see FIG. 1(a)). ).

前記選択イオン注入により半導体基板1に、半導体基板
活性部4が作製される(第1図(b))。次に、前記選
択イオン注入の後、マスクとして不要となったフォトレ
ジスト2ff:通常の7第1・レジスト除去剤9例えば
J−100(ナガセ化成社製)9o〜100℃に10〜
16分浸漬し、大部分のフォトレジスト2を除去する。
A semiconductor substrate active region 4 is formed in the semiconductor substrate 1 by the selective ion implantation (FIG. 1(b)). Next, after the selective ion implantation, the photoresist that is no longer needed as a mask 2ff: Ordinary 7 1st resist remover 9 For example, J-100 (manufactured by Nagase Kasei Co., Ltd.) 9 o - 100 ° C.
After soaking for 16 minutes, most of the photoresist 2 is removed.

しかし5前記フオトレジスト2自身がマスクとしてイオ
ン注入されているため硬化し、前記のフォトレジスト除
去剤だけでは、前記フォートレジストが除去しきれず、
フォトレジスト残渣2aが残存する(第1(2)(C)
)。
However, since the photoresist 2 itself is ion-implanted as a mask, it hardens, and the photoresist cannot be completely removed with the photoresist remover alone.
Photoresist residue 2a remains (1st (2) (C)
).

よって次にトリクロロエタンもしくはアセトンなどのイ
イ機溶媒中で1選択イオン注入後の半導体基板をラビン
グし、前記フォトレジスト残渣を除去する方法がとられ
る(第1図(d))。
Therefore, next, a method is used in which the semiconductor substrate after selective ion implantation is rubbed in a suitable solvent such as trichloroethane or acetone to remove the photoresist residue (FIG. 1(d)).

しかしながら、前記のような方法においては。However, in the method as described above.

ラビングという機械的操作により、前記半導体基板が破
損する危険性は危れす、これが歩留り低下の一因となる
という問題点を有していた。
The mechanical operation called rubbing poses a problem in that there is a risk that the semiconductor substrate may be damaged, which is a cause of a decrease in yield.

発明の目的 本発明の目的は、選択イオン注入後の7オトレジストヲ
ラビング等の機械的操作を用いずに除去し、もって半導
体基板の破損の危険性を減じ、歩留りの向上を可能とす
る半導体装置の製造方法を提供することである。
OBJECTS OF THE INVENTION An object of the present invention is to provide a semiconductor substrate that can be removed without mechanical operations such as rubbing after selective ion implantation, thereby reducing the risk of damage to the semiconductor substrate and improving yield. An object of the present invention is to provide a method for manufacturing a device.

発明の構成 本発明の半導体装置の製造方法は、半導体基板に、ポジ
型フォトレジストをパターニングする工程と、前記ポジ
型フォトレジストをマスクとし選択イオン注入する工程
と、前記選択イオン注入の後、前記フォトレジストの除
去に際し双極子能率の高い非プロトン性溶媒を用いる工
程とを含むように構成したものであり、これにより、前
記選択イオン注入後の前記ポジ型フォトレジス)kラビ
ング等の機械的操作を行なうことなしに除去し、もって
半導体基板の破損の危険性を減じ、歩留りの向上となる
ものである。
Structure of the Invention A method for manufacturing a semiconductor device according to the present invention includes a step of patterning a positive photoresist on a semiconductor substrate, a step of selectively implanting ions using the positive photoresist as a mask, and a step of performing the selective ion implantation after the selective ion implantation. The method is configured to include a step of using an aprotic solvent with a high dipole efficiency when removing the photoresist, and thereby, the positive photoresist after the selective ion implantation is removed by mechanical operations such as rubbing. This method reduces the risk of damage to the semiconductor substrate and improves yield.

実施例の説明 以下本発明の一実施例について5図面を参照しながら説
明する。
DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to five drawings.

第2図(a) 、 (b) 、 (C) 、 (d)は
本発明の一実施例におけるフォトレジストの除去方法の
工程断面図を示すものである。第1図において1は半導
体基板。
FIGS. 2(a), (b), (C), and (d) show process cross-sectional views of a method for removing photoresist in an embodiment of the present invention. In FIG. 1, 1 is a semiconductor substrate.

21は、注入イオン3に対する選択マスクとなるポジ型
フォトレジスト、21aはフォトレジスト残渣、4は注
入イオン3による半導体基板活性部である。
21 is a positive photoresist serving as a selective mask for the implanted ions 3; 21a is a photoresist residue; and 4 is an active part of the semiconductor substrate formed by the implanted ions 3.

以上のように構成された本実施例の半導体装置の製造方
法について以下に説明する。まず、半導体基板1の表面
にポジ型フォトレジストトシて0FPR−800(東京
応化工業社製)を塗布し、所要のパターニングを行ない
、注入イオン3に対する。膜厚が1μmのマスクとする
。次に、注入イオン3として、シリコンを加速電圧15
0KeV注入量I X 10 dos@A4とし、選択
イオン注入を行なう(第21区fa)鳥前記選択イオン
注入により、半導体基板1に半導体基板活性部4が作製
さh λ 1* ウIツl b l 1に’ lf−g
 :5渭1マ 、−L r7.・5 リ 1゜210つ
いた半導体基板1を、双極子能率の高い非プロトン性溶
媒であるジメチルポルムアミド(以下DMF と略す]
約9o℃に10分間浸漬することにより、ポジ型7オト
レジスト21はほとんど溶出する(第2図(C))。さ
らに、従来のフォトレジスト除去方法であるフォトレジ
スト除去剤J−1oo約90℃に10〜16分浸漬する
ことにより、フォトレジスト残渣21aは簡単に除去さ
れる(第10(C))。
A method of manufacturing the semiconductor device of this embodiment configured as described above will be described below. First, a positive photoresist 0FPR-800 (manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied to the surface of the semiconductor substrate 1, and the required patterning is performed to form the implanted ions 3. The mask has a film thickness of 1 μm. Next, as implanted ions 3, silicon is accelerated at a voltage of 15
Selective ion implantation is performed with an implantation dose of 0 KeV I x 10 dos@A4 (section 21 fa) By the selective ion implantation, a semiconductor substrate active region 4 is created in the semiconductor substrate 1. l 1 to' lf-g
:5渭1ま、-L r7.・5 The semiconductor substrate 1 with a 1°210 diameter is heated with dimethylpolamide (hereinafter abbreviated as DMF), which is an aprotic solvent with high dipole efficiency.
By immersing it at about 9° C. for 10 minutes, most of the positive type 7 photoresist 21 is eluted (FIG. 2(C)). Further, the photoresist residue 21a is easily removed by immersing the photoresist remover J-1oo in about 90° C. for 10 to 16 minutes, which is a conventional photoresist removal method (No. 10 (C)).

次に、前記の一実施例で述べたフォトレジストの除去方
法において、双極子能率の高い非プロトン性溶媒として
、ジメチルスルホキシド(以下DMSOと略す2および
ヘキサメチルホスホルアミド(以下HMPAと1略すン
を用いた場合、さらに、その他の溶媒としてテトラヒド
ロフラン(以下THFと略す]、アセト/、酢酸−nブ
チル。
Next, in the photoresist removal method described in the above example, dimethyl sulfoxide (hereinafter abbreviated as DMSO) and hexamethylphosphoramide (hereinafter abbreviated as HMPA) are used as aprotic solvents with high dipole efficiency. In addition, other solvents include tetrahydrofuran (hereinafter abbreviated as THF), acetate/n-butyl acetate.

メチルセロソルブ(以下Me−Cennと略す)、メチ
ルエチルケトン(以下MEKと略す)ならびにトリクロ
ルエチレン(以下トリクレンと略す)を用いた場合の7
オトレジスト除去のjf!ijB &裏f※なお表には
、前記の一実施例で述べたDMFについても併記し、ま
た比較のため、従来例としての1−1oo のみを用い
た場合も記載した。
7 when using methyl cellosolve (hereinafter abbreviated as Me-Cenn), methyl ethyl ketone (hereinafter abbreviated as MEK) and trichlorethylene (hereinafter abbreviated as trichlene)
Otoresist removal jf! ijB & Back f *The front also shows the DMF described in the above example, and also shows the case where only 1-1oo as a conventional example is used for comparison.

前記表は、各溶媒の比較項目として、イオン注入後のマ
スクとなったポジ型フォトレジストの溶解能、ラビング
の不要性、最終的なレジスト除去の可・不可を、それぞ
れの優位性により、○、△。
The table above shows the ability to dissolve the positive photoresist that served as a mask after ion implantation, the necessity of rubbing, and whether or not the final resist can be removed, as comparison items for each solvent, depending on the superiority of each solvent. ,△.

×の順に表わしたものである。They are expressed in the order of ×.

前記表に示すように、前記一実施例で示したDMFの他
に、DMSOおよびHMPA といった双極子能率の高
い非プロトン性溶媒が、選択イオン注入後のフォトレジ
スト除去に用いることができる。また、THF 、Me
 −CeIl、fl 、MEKについては、イオン注入
後のポジ型フォトレジスト溶解能が小さくラビングを行
なってもレジストを除去することはできなかった。(表
中、レジスト除去の項に×で示す) なお、前記一実施例では、DMFでポジ型フォトレジス
トを溶出した後、従来例のl−100を用いたが、DM
Fだけで充分に前記ポジ型フォトレジストが除去された
場合には、O1■述の■−100の使用が必要ないこと
勿論である。
As shown in the table above, in addition to DMF shown in the above example, aprotic solvents with high dipole efficiency such as DMSO and HMPA can be used to remove the photoresist after selective ion implantation. Also, THF, Me
-CeIl, fl, and MEK had a low ability to dissolve the positive photoresist after ion implantation, and the resist could not be removed even by rubbing. (In the table, the column for resist removal is indicated by an x.) In the above example, after eluting the positive photoresist with DMF, the conventional l-100 was used.
Of course, if the positive photoresist is sufficiently removed by F alone, there is no need to use -100 mentioned in O1.

発明の効果 以上の説明から明らかなように1本発明は半導体基板に
ポジ型フォトレジスtfパターニングする工程と、前記
ポジ型フォトレジストヲマスクとし選択イオン注入する
工程と、前記選択イオン注入の後、前記フォトレジスト
の除去に際し、双極子能率の高い非プロトン性溶媒を用
いる工程とを含む方法であるので、前記選択イオン注入
後の前記ポジ型フォトレジストヲ、ラビング等の機械的
操作を行なうことなしに除去し、もって半導体基板の破
損の危険性を減じ、歩留りの向−Lにつながるという効
果が得られる。
Effects of the Invention As is clear from the above description, one aspect of the present invention includes a step of patterning a positive photoresist TF on a semiconductor substrate, a step of selectively implanting ions using the positive photoresist as a mask, and after the selective ion implantation. Since this method includes a step of using an aprotic solvent with high dipole efficiency when removing the photoresist, there is no need to perform mechanical operations such as rubbing on the positive photoresist after the selective ion implantation. This has the effect of reducing the risk of damage to the semiconductor substrate and improving yield.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a) 、 (b) 、 (C) 、 (d)は
、従来のラビングの工程ヶ含む半導体装置の製造方法の
工程断面図、第2図(a) 、 (b) 、 (C) 
、 (d)は本発明の一実施例における半導体装置の製
造方法の工程断面図である。 1・・・・・半導体基板、2・・・−・・・フォトレジ
ス)、2a・・・・・フォトレジスト残渣、3・・・・
・・注入イオン、4・・・・・・半導体基板活性部、2
1・・・・・・ポジ型フォトレジスト、21a・・・・
・・ポジ型フォトレジスト残渣。 代理人の氏名 弁理士 中 尾 敏 男 を1か1基筒
 1 図
FIGS. 1(a), (b), (C), and (d) are process cross-sectional views of a semiconductor device manufacturing method including a conventional rubbing process, and FIGS. 2(a), (b), and (C )
, (d) are process cross-sectional views of a method for manufacturing a semiconductor device in an embodiment of the present invention. 1...Semiconductor substrate, 2...-...Photoresist), 2a...Photoresist residue, 3...
...Implanted ions, 4...Semiconductor substrate active region, 2
1...Positive photoresist, 21a...
...Positive photoresist residue. Name of agent: Patent attorney Toshio Nakao 1 or 1 figure 1

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板上にポジ型フォトレジスト’tlバタ
ーニングする工程と、前記ポジ型フォトレジストをマス
クとし、選択イオン注入をする工程と、前記選択イオン
注入の後、前記ポジ型フォトレジストの除去に際し、双
極子能率の高い非プロトン性溶媒を用いる工程とを含む
ことを特徴とした半導体装置の製造方法。
(1) A step of patterning a positive photoresist on a semiconductor substrate, a step of performing selective ion implantation using the positive photoresist as a mask, and a step of removing the positive photoresist after the selective ion implantation. A method for manufacturing a semiconductor device, comprising: a step of using an aprotic solvent with high dipole efficiency.
(2)双極子能率の高い非プロトン性済媒が、ジメチル
ホルムアミド、ジメチルスルホキシド、または、ヘキザ
メヂルポスホルアミドである’I’J” it’l山°
l求の範囲第1項記載の半導体装置の製造方法。
(2) 'I'J'it'l mountain where the aprotic solvent with high dipole efficiency is dimethylformamide, dimethyl sulfoxide, or hexamedyl phosphoramide.
1. A method for manufacturing a semiconductor device according to item 1.
JP17530883A 1983-09-22 1983-09-22 Manufacture of semiconductor device Pending JPS6066424A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17530883A JPS6066424A (en) 1983-09-22 1983-09-22 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17530883A JPS6066424A (en) 1983-09-22 1983-09-22 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6066424A true JPS6066424A (en) 1985-04-16

Family

ID=15993820

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17530883A Pending JPS6066424A (en) 1983-09-22 1983-09-22 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6066424A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63159849A (en) * 1986-12-24 1988-07-02 Asahi Chem Ind Co Ltd Photoresist release agent composition
JPS63163457A (en) * 1986-12-26 1988-07-06 Asahi Chem Ind Co Ltd Peeling composition for photoresist
JPS63168651A (en) * 1987-01-06 1988-07-12 Asahi Chem Ind Co Ltd Stripping agent composition for photoresist
JPS6442653A (en) * 1987-08-10 1989-02-14 Tokyo Ohka Kogyo Co Ltd Peeling solution for positive type photoresist
JPS6481950A (en) * 1987-09-25 1989-03-28 Asahi Chemical Ind Agent for peeling photoresist
JPS6481949A (en) * 1987-09-25 1989-03-28 Asahi Chemical Ind Agent for peeling photoresist
JPH04133062A (en) * 1990-09-25 1992-05-07 Toray Ind Inc Developer for photosensitive polyimide
JPH0593157A (en) * 1991-07-01 1993-04-16 Nissan Motor Co Ltd Method of stripping resin coating and method of post-treatment
WO2008152907A1 (en) * 2007-06-12 2008-12-18 Toagosei Co., Ltd. Agent for stripping resist film on electroconductive polymer, method for stripping resist film, and substrate with patterned electroconductive polymer
WO2010058778A1 (en) 2008-11-19 2010-05-27 東亞合成株式会社 Method for producing substrate having patterned conductive polymer film and substrate having patterned conductive polymer film

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63159849A (en) * 1986-12-24 1988-07-02 Asahi Chem Ind Co Ltd Photoresist release agent composition
JPS63163457A (en) * 1986-12-26 1988-07-06 Asahi Chem Ind Co Ltd Peeling composition for photoresist
JPS63168651A (en) * 1987-01-06 1988-07-12 Asahi Chem Ind Co Ltd Stripping agent composition for photoresist
JPS6442653A (en) * 1987-08-10 1989-02-14 Tokyo Ohka Kogyo Co Ltd Peeling solution for positive type photoresist
JPS6481950A (en) * 1987-09-25 1989-03-28 Asahi Chemical Ind Agent for peeling photoresist
JPS6481949A (en) * 1987-09-25 1989-03-28 Asahi Chemical Ind Agent for peeling photoresist
JPH04133062A (en) * 1990-09-25 1992-05-07 Toray Ind Inc Developer for photosensitive polyimide
JPH0593157A (en) * 1991-07-01 1993-04-16 Nissan Motor Co Ltd Method of stripping resin coating and method of post-treatment
WO2008152907A1 (en) * 2007-06-12 2008-12-18 Toagosei Co., Ltd. Agent for stripping resist film on electroconductive polymer, method for stripping resist film, and substrate with patterned electroconductive polymer
JPWO2008152907A1 (en) * 2007-06-12 2010-08-26 東亞合成株式会社 Resist film stripper on conductive polymer, resist film stripping method, and substrate having patterned conductive polymer
WO2010058778A1 (en) 2008-11-19 2010-05-27 東亞合成株式会社 Method for producing substrate having patterned conductive polymer film and substrate having patterned conductive polymer film

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