JPH0239540A - Manufacture of mis type transistor - Google Patents

Abstract

PURPOSE:To make it possible to prevent deterioration or breakdown of a gate insulating film arising at removal of a resist film or at ion implantation by forming a conductive layer on a film on a gate insulating film so as to form a gate electrode with the film and the conductive layer. CONSTITUTION:After forming a field insulating layer 2 and a gate insulating film 3, a thin impurity-doped polycrystalline silicon film 4 is formed. Next, ions of, for example, boron B are implanted into the surface part of a semiconductor region 1 through the gate insulating film 3 and the polycrystalline silicon film 4 so as to form an ion implanted region 5 for controlling the threshold voltage Vth. Further, ions of impurity of the same conductivity as the semiconductor region 1 are implanted into the lower part of a channel region formation part so as to form an ion implanted layer 6 in high impurity concentration to suppress the expansion of a depletion layer. Next, an impurity-doped polycrystalline silicon layer 7 constituting a silicon gate electrode, etc., is formed on the whole surface of the film 4. Next, after formation of a silicon gate electrode 8, ions of impurity are implanted into a the semiconductor region 1 with the field insulating film 2 and the gate electrode 8 as a mask so as to form a source region 9 and a drain region 10.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing an MIS transistor, particularly a method for manufacturing an MIS transistor in which ions are selectively implanted into a semiconductor region through a gate insulating film on the semiconductor region. It is related to.

[Summary of the invention]

The present invention relates to a method for manufacturing an MIS type transistor in which ions are selectively implanted into a semiconductor region through a gate insulating film on the semiconductor region. , an impurity for suppressing at least the expansion of the depletion layer is introduced into the lower part of the channel region forming portion of the MIS type transistor in the semiconductor region through the thin film.

After that, after forming a conductive layer on the thin film, the thin film and the conductive layer are selectively etched to form a gate electrode. This structure is designed to prevent deterioration and destruction of the gate insulating film that occurs during removal of the resist film and during ion implantation.

Further, the present invention selectively implants ions into a semiconductor region through a gate insulating film on the semiconductor region.
In a method for manufacturing an S-type transistor, a thin film is formed on a gate insulating film formed on a semiconductor region of a first conductivity type, impurity ions are implanted into the semiconductor region through the thin film, and an insulating film is formed between the thin film and the gate insulating film. A portion of the semiconductor region is exposed by selectively etching the film, and a coating is formed over the exposed portion and the thin film. Thereafter, the film is etched so that at least a portion thereof is patterned on the exposed portion, and a gate pattern is formed on the gate insulating film, and then, using the gate pattern as a mask, impurities of the second conductivity type are ion-implanted. In the case of having an N-channel and P-channel MIS type transistor by forming a source and a drain using a thin film and a gate electrode using a thin film and a coating, it is possible to remove the selectively formed resist film and during ion implantation. This structure is designed to prevent deterioration and destruction of the gate insulating film that occurs when forming loosely exposed parts and when light etching is performed on the oxide film formed on the exposed parts.

[Conventional technology]

In general, when increasing the memory capacity of a memory that uses MIS transistors as a component, or when increasing the speed of the MIS transistor itself, miniaturization and high performance are required in the formation of each MIS transistor. Integration and high performance are required, and for this purpose, the thickness of the gate insulating film formed on the semiconductor region must be reduced. For example, the thickness of the gate insulating film in a 256-bit static RAM is 200A, 180A in a 1M-bit static RAM, 100-120A in a 4M-bit static R4, and 160A in a 4M-bit static RAM.
For M-bit static RAM, the number is 60 to 80.

As shown in FIG. 3, the conventional method for manufacturing MIS transistors is to selectively oxidize the surface of a silicon semiconductor region (21) of a first conductivity type, for example, P type, to form a field insulating layer (22). , a gate insulating film (23) is formed on the surface of the semiconductor region (21) by thermal oxidation (see A in the same figure).
reference).

Next, as shown in the figure, an impurity of the same conductivity type as that of the semiconductor region (21) (in this case, Since it is P type, boron B etc. are used)
An ion implantation layer (24) for suppressing the expansion of the depletion layer is formed by ion implantation.

Next, as shown in FIG.
0) and the semiconductor region (21) (so-called buried contact type), the gate insulating film (23) is selectively etched to form a window (23a).
is formed to partially expose the surface of the semiconductor region (21). In this case, a photoresist film mask (26) is formed on the gate insulating film (23) and the field insulating layer (22) other than the exposed portion (25).

After exposure, the mask (26) is removed, and during this mask removal process, as shown in the same figure, the exposed portion (26) is removed.
In 25), 5iO7 oxide film by natural oxidation (27)
is formed.

Therefore, as shown in FIG.
3) A 5in2 pattern was formed on the exposed part (25) by performing extremely shallow light etching on the entire surface.
The oxide film (27) is removed.

Next, as shown in FIG. F, a polycrystalline silicon layer (28) forming a silicon gate electrode or the like is formed on the entire surface of the gate insulating film (23) including the exposed portion (25).

Next, as shown in Figure G, the polycrystalline silicon layer (2
8) is selectively etched to form a silicon gate electrode (2).
9) and a silicon wiring layer (30) are formed.

Thereafter, using the phosphor gate electrode (29) and the field insulating layer (22) as masks, impurities of the second conductivity type, that is, N type, such as phosphorus P, are ion-implanted into the semiconductor region (21), and the source region (31) and the drain region ( 32).

[Problem to be solved by the invention]

Incidentally, an MIS type memory may be configured to include an N-M T S ) transistor and a P-MIS) transistor. In this case, for example, during the ion implantation shown in FIG.
S) Since the transistor forming region must be implanted separately, for example, when ion implantation is first performed in the N-Mis) transistor forming region, a resist film is formed on the P-Mis) transistor forming region. . Next, the resist film in the P-MIS transistor formation region is removed, and on the contrary, a resist film is formed in the N-MIS) transistor formation region, and then ions are implanted into the P'-MIS) transistor formation region. Do this.

However, in the conventional method for manufacturing MIS type transistors, the gate insulating film (23) has become extremely thin (200 Å or less) due to the trend toward thinning of the gate insulating film (23).
It has become clear that the probability of gate failure increases due to the following causes, which has a negative impact on yield and reliability.

(i) The gate insulating film (23) is eroded by ultrasonic cleaning when removing the resist film, resulting in a breakdown voltage deterioration.

(ii) During the draining process after cleaning (that is, in a spin dryer), the gate insulating film (23) is charged, and the gate insulating film (23) is electrostatically damaged.

(iii) The gate insulating film (23) is charged during ion implantation, causing electrostatic breakdown of the gate insulating film (23).

(iv) During light etching to remove the natural oxide film (27), the erosion caused by the resist film stripping process is further increased, causing deterioration of the breakdown voltage of the gate insulating film.

The present invention has been made in view of the above points, and its purpose is to provide a method for manufacturing an MIS transistor that can prevent deterioration and destruction of the gate insulating film that occurs during resist film removal and ion implantation. Our goal is to provide the following.

In addition, the present invention prevents deterioration and destruction of the gate insulating film in a buried contact type MIS transistor that occurs when removing a resist film, ion implantation, forming an exposed portion of a buried contact, and light etching. It is an object of the present invention to provide a method for manufacturing an MIS type transistor that can be used.

[Means to solve the problem]

The manufacturing method of the MIS type transistor of the present invention is applicable to the semiconductor region (
1) A thin film (4) made of polycrystalline silicon, silicide, etc. is formed on the gate insulating film (3) formed above, and the channel region of the MIS transistor in the semiconductor region (1) is formed through the thin film (4). An impurity that suppresses at least the expansion of the depletion layer is introduced into the lower part of the formation portion. After that, after forming a conductive layer (7) on the thin film (4),
and the conductive layer (7) are selectively etched to form a gate electrode (8).

Furthermore, the manufacturing method of the MIS type transistor of the present invention includes forming a thin film (4) made of polycrystalline silicon, silicide, etc. on the gate insulating film (3) formed on the semiconductor region (1) of the first conductivity type. The semiconductor region (1) is formed through the thin film (4).
), and selectively etching the thin film (4) and gate insulating film (3) to form a semiconductor region (
1) is partially exposed, and the thin film (4) is placed on the exposed B (12).
A coating (7) is formed to cover the top. After that, the coating (7)
is etched so that at least a portion thereof is patterned on the exposed portion (12), and a gate pattern (8) is formed on the gate insulating film (3), and then a gate pattern (8) is etched using the gate pattern (8) as a mask. A source (9) and a drain (10) are formed by ion-implanting impurities of two conductivity types.

[Effect]

According to the manufacturing method of the first invention described above, the semiconductor region (1)
Since a thin film (4) made of polycrystalline silicon or the like is formed on the upper surface of the gate insulating film (3) formed above, the thin film (4)
serves as a kind of protective film for the gate insulating film (3), and the gate insulating film (3) is removed by the cleaning process performed when removing the resist film.
3) can be prevented from corrosive action, and can also prevent electrostatic damage caused by draining. Further, it is also possible to prevent electrostatic breakdown of the gate insulating film (3) that occurs during ion implantation to suppress the spread of the depletion layer in the channel region forming portion. Therefore, a MIS transistor having a thin gate insulating film can be provided with high yield and high reliability.

Further, according to the manufacturing method of the second invention described above, in the formation of a buried contact type MIS transistor,
Since a thin film (4) made of polycrystalline silicon or the like is formed on the upper surface of the gate insulating film (3) formed on the semiconductor region (1), the thin film (4) serves as a kind of protective film for the gate insulating film (3). Therefore, it is possible to prevent corrosion of the gate insulating film (3) due to the cleaning process performed when removing the resist film, and also to prevent electrostatic discharge damage due to the draining process.

Furthermore, electrostatic breakdown of the gate insulating film (3) that occurs during ion implantation into the semiconductor region (1) can also be prevented. Further, when forming the exposed portion (12) for making a buried contact, it is possible to prevent the corrosion of the gate insulating film (3) due to the cleaning process, especially when removing the mask (11), and also to Electrostatic damage can be prevented, and the SlO□ oxide film (13) formed on the exposed part (12) by natural oxidation when the mask is removed
It is possible to prevent corrosion of the gate insulating film (3) that occurs during light etching to remove the etching. Therefore, it is possible to provide an MIS type transistor having a thin gate insulating film and having a reliable buried contact structure.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to FIGS. 1 and 2. Figure 1 shows the LS of a normal MIS type transistor.
This is a case where it is applied to a manufacturing method of I (large-scale integrated circuit). This process will be explained step by step below.

First, as shown in the figure Δ, a silicon semiconductor region of the first conductivity type (for example, a P-type semiconductor region for an N-channel MIS type transistor, and an N-type semiconductor region for a P-channel MIS type transistor). After selectively thermally oxidizing the surface portion of (1) to form a field insulating layer (2), the exposed semiconductor surface of the semiconductor region (1) is thermally oxidized to form a gate insulating film (thickness: Sin, membrane)
(3) is formed.

Next, as shown in Figure B, a thin impurity-doped polycrystalline silicon film (with a thickness of approximately
0 people) (4) is formed.

Next, as shown in FIG.
0KeV) to control the threshold voltage vth. (5) shows the ion-implanted layer for Vth control. In this case, boron B ions are implanted into both the N channel and the P channel. Furthermore, the above ion implantation layer (
5) In a thinner part, that is, under the channel region formation part, impurities of the same conductivity type as the semiconductor region (1) are ion-implanted to form an ion-implanted layer (6) with a high impurity concentration to suppress the expansion of the depletion layer. do.

In this case, if the semiconductor region (1) is an N type, an N type impurity such as phosphorus P is used, and if the semiconductor region (1) is a P type, a P type impurity such as boron B is used.

Incidentally, in the above step, when ions are first implanted into the 11-M I S type transistor formation region, for example, the P-M
If a resist film is formed in the IS type transistor formation region and used as a mask, and then ions are implanted into the P-MIS type transistor formation region, a resist film is formed in the NMIS type transistor formation region. Use as a mask.

In the case of this embodiment, a resist film is formed on the polycrystalline silicon thin film (4) in the MIS transistor formation region of one channel before ion implantation into the MIS transistor formation region of the other channel. Then, while ion implantation is being performed into the MIS type transistor forming region of the other channel, the resist film functions as a mask. Next, when performing ion implantation into the MIS type transistor formation region of channel 1, the resist film is made of polycrystalline silicon by thoroughly performing oxidation plasma treatment, cleaning treatment with ammonia hydrogen peroxide solution, and draining treatment. After removal from the thin film (4), ion implantation is performed. During this resist film removal process, since the gate insulating film (3) is covered with the polycrystalline silicon thin film (4), there is no fear that the gate insulating film (3) will be eroded.

Also, during ion implantation, polycrystalline silicon thin film (4
) serves as a kind of protective film for the gate insulating film (3), so that electrostatic breakdown due to charge-up inside the gate insulating film (3) during ion implantation can be prevented.

In addition, the gate insulating film (3) is very thin (thickness 100 Å).
As the gate insulating film (3 ), a polycrystalline silicon thin film (4) with a film thickness of approximately 300 mm was formed on top of the gate insulating film (3), so even if the gate insulating film (3) is formed very thin, there is no need to lower the ion implantation energy and the existing device can be used. It is possible to perform ion implantation with an energy (10 to 20 KeV) that can be outputted by.

Next, as shown in the same figure, the polycrystalline silicon thin film (4)
An impurity-doped polycrystalline silicon layer (2,700 to 3,000 layers thick) that forms a silicon gate electrode, etc. on the entire surface (
7).

Next, as shown in the figure, after selectively etching the polycrystalline silicon layer (7) and the polycrystalline silicon thin film (4) to form a silicon gate electrode (8), the field insulating film (2) is etched. Then, using the gate electrode (8) as a mask, an impurity (for example, boron B for a phosphorus PSP channel) is ion-implanted into the semiconductor region (1) to form a source region (9) and a drain region (10). Form.

After this step, manufacturing is performed in the same manner as the normal manufacturing method of MIS type LSI and the like. That is, the formation of an interlayer insulating layer, the formation of a contact window for taking out an electrode, the formation of a wiring film made of aluminum, etc. are performed, but these are not particularly different from conventional general manufacturing methods, so they will be illustrated and explained. is omitted.

In the above example, an impurity-doped polycrystalline silicon thin film was used as the thin film (4), but a thin film formed by forming a polycrystalline silicon thin film and then doping impurities, a silicide thin film, or the like may also be used.

Further, in the above example, the gate electrode (8) was formed of the polycrystalline silicon thin film (4) and the polycrystalline silicon layer (7), but other silicides may be used. In this case, in the same figure, a film with a thickness of 700 to 2000 on the polycrystalline silicon thin film (4) is
A layer of impurity-doped polycrystalline silicon is formed, and silicide, such as tungsten silicide, is formed to a thickness of 1500 to 2000 nm on the polycrystalline silicon layer. After that, the same steps as those from E onwards can be carried out.

Furthermore, although the polycrystalline silicon layer (7) is doped with impurities from the beginning to reduce its resistivity appropriately, a polycrystalline silicon layer that is not doped with impurities is formed on the polycrystalline silicon thin film (4). Afterwards, impurities may be doped. Furthermore, it is also possible to use a metal layer in place of the polycrystalline silicon layer (7).

As described above, according to the manufacturing method of the MIS transistor of this embodiment, the polycrystalline silicon thin film (4) formed on the gate insulating film (3) functions as a kind of protective film for the gate insulating film (3). Gate insulating film (
3) deterioration and destruction can be prevented.

Further, when performing ion implantation for Vth control, it is not necessary to use low energy, but it can be performed using energy that can be output by existing equipment.

Next, static R with buried contact structure
An example of the manufacturing method applied to the manufacturing of AM MIS type transistors will be explained based on the process diagram shown in FIG.

Of the manufacturing process of this MIS type transistor, A-
Since C is the same as in the first embodiment, the explanation of the steps up to that point will be omitted, and the same reference numerals as in the first embodiment will be used for those corresponding to those in the first embodiment.

In Figure C, after the ion implantation for vth control and the ion implantation for suppressing the expansion of the depletion layer, a polycrystalline silicon thin film (4
) and the gate insulating film (3) are selectively etched,
The surface of the semiconductor region (1) is partially exposed. During this etching, a mask (11) made of a photoresist film is formed in areas other than the exposed portions. After exposure, the mask (11) is removed, and in this removal process as well, oxidation plasma treatment, cleaning treatment with aqueous ammonia and hydrogen peroxide, and draining treatment are performed in the same manner as in the removal of the resist film. However, since the polycrystalline silicon thin film (4) is formed on the top surface of the gate insulating film (3), the thin film (4) is
4) serves as a kind of protective film for the gate insulating film (3) and can prevent the gate insulating film (3) from being eroded by the mask removal process.

Next, as shown in the same figure, when the mask (11) is removed, a thin S layer due to natural oxidation is formed in the exposed portion (12).
An iO□ oxide film (13) is formed. This oxide film (13
), extremely shallow light etching, so-called light etching, is performed.

By this light etching, the oxide film (13) formed on the exposed portion (12) is removed, as shown in FIG. Even during this light etching, since the polycrystalline silicon thin film (4) serves as a protective film for the gate insulating film (3), corrosion of the gate insulating film (3) due to light etching is prevented.

Next, as shown in FIG. G, an impurity-doped polycrystalline silicon layer (7) forming a silicon gate or the like is formed entirely on the polycrystalline silicon thin film (4) including the exposed portion B (t2).

After that, as shown in Figure H, a polycrystalline silicon layer (7) is formed.
Then, the polycrystalline silicon thin film (4) is selectively etched to form a silicon gate electrode (8), and an exposed portion (1) facing the window (12a) on the surface of the semiconductor region (1) is etched.
2) A silicon wiring layer (14) is formed on the silicon wiring layer (14) by patterning so that a part of the window (12a) is exposed.

Then, using the field insulating layer (2) and the silicon gate electrode (8) as a mask, an impurity (N
In the case of a channel, for example, phosphorus P is ion-implanted, and in the case of a P channel, for example, boron B) is implanted into the source region (9).
and a drain region <10).

After this step, as already explained in the first embodiment, the formation of an interlayer insulating layer, the formation of a contact window for taking out the electrodes, the formation of a wiring film made of aluminum, etc. are performed, but these are not explained in the first embodiment. As in the example, the description is omitted.

Incidentally, in the second embodiment, the gate electrode (8) was composed of the polycrystalline silicon thin film (4) and the polycrystalline silicon layer (7), but silicide may also be used as in the first embodiment. .

Further, although the polycrystalline silicon layer (7) is doped with impurities from the beginning, the nucleus layer (7) is doped with impurities as in the first embodiment.
Alternatively, after forming on the polycrystalline silicon thin film (4), impurities may be doped.

Further, as the thin film (4), an oxide thin film or the like may be used as in the first embodiment.

As described above, according to the manufacturing method of the M I S type transistor with the buried contact quib of the second embodiment, the polycrystalline silicon thin film (4) formed on the gate insulating film (3) is a type of gate insulating film ( In order to function as a protective film for 3),
It is possible to prevent deterioration and destruction of the gate insulating film (3) that occurs during removal of the resist film and during ion implantation for VTH control and the like.

Also, when forming the exposed part (11) in the buried contact, and the oxide film (11) formed on the surface of the exposed part (11),
It is possible to prevent corrosion of the gate insulating film (3) that occurs during light etching to remove the gate insulating film (3).

Furthermore, when performing ion implantation for Vth control, it is not necessary to use low energy, but it can be performed using energy that can be output by existing equipment.

Incidentally, it is also possible to adopt an LDD (light doped drain) structure in both the first and second embodiments.

〔Effect of the invention〕

The method for manufacturing an MIS transistor according to the present invention is to form a thin film on a gate insulating film formed on a semiconductor region, and to spread at least a depletion layer below the channel region forming portion of the MIS transistor in the semiconductor region through the thin film. After that, a conductive layer was formed on the thin film, and the thin film and the conductive layer were selectively etched to form the gate electrode. In the case of having a MIS type transistor, it is possible to prevent deterioration and destruction of the gate insulating film that occurs when removing a selectively formed resist film and during ion implantation.

Therefore, even if the gate insulating film is made thinner, a highly reliable and high-performance MIS transistor can be provided, and can be manufactured with high yield.

Further, the method for manufacturing the MIS type transistor according to the present invention is as follows.
A thin film is formed on the gate insulating film formed on the conductive type semiconductor region, impurity ions are implanted into the semiconductor region through the thin film, and the thin film and the gate insulating film are selectively etched to form the semiconductor region. A part of the gate insulating film is exposed, a film is formed to cover the exposed part and the thin film, and then the film is etched so that at least part of the film is patterned on the exposed part, and a code pattern is formed on the gate insulating film. After forming the gate pattern, impurities of the second conductivity type are ion-implanted to form the source and drain using the gate pattern as a mask. It is possible to prevent deterioration and destruction of the gate insulating layer that occurs when selectively forming a resist film is removed, when ion implantation is performed, when an exposed portion is formed, and when an oxide film formed on the exposed portion is light etched.

Therefore, a MIS type transistor having a buried contact structure having a thin gate insulating film can be manufactured with high yield and high reliability.

[Brief explanation of the drawing]

FIG. 1 is a process diagram showing the manufacture of a MIS type transistor according to the first embodiment, FIG. 2 is a process diagram showing the second embodiment, and FIG.
The figure is a process diagram showing a conventional example. (1) is a semiconductor region, (2) is a field insulating layer, (3
) is a gate insulating film, (4) is a polycrystalline silicon thin film, (5
) is an ion-implanted layer for vth control, (6) is an ion-implanted layer for suppressing depletion layer expansion, (7) is a polycrystalline silicon layer, (8) is an silicon gate electrode, (9) is a source region, and (10) is a drain. area, (12) is the exposed part, ri 13
) is a 5in2 oxide film, and (14) is a silicon wiring layer. Acting agent Hitoshi Fujisada Domatsu Hide Kuma Mori Figure 2 Diagram

Claims (1)

[Claims] 1. A step of forming a thin film on the gate insulating film formed on the semiconductor region, and forming at least a depletion layer under the channel region forming portion of the MIS transistor in the semiconductor region through the thin film. A method for manufacturing an MIS transistor, comprising: introducing an impurity to suppress spreading, forming a conductive layer on the thin film, and forming a gate electrode with the thin film and the conductive layer. 2. forming a thin film on the gate insulating film formed on the semiconductor region of the first conductivity type; implanting impurity ions into the semiconductor region through the thin film; and combining the thin film and the gate insulating film. selectively etching to expose the semiconductor region; forming a film covering the exposed portion and the thin film; and patterning the film so that at least a portion of the film is patterned on the exposed portion. etching and forming a gate pattern on the gate insulating film; and ion-implanting impurities of a second conductivity type using the gate pattern as a mask to form a source and a drain. and an MI that constitutes a gate electrode with the above film.
Manufacturing method of S-type transistor.