KR19990011232A - Manufacturing Method of Semiconductor Device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, comprising: forming a first insulating film on a semiconductor substrate of a first conductivity type having a normal transistor region and an ESD protection transistor region; and forming a first insulating layer on the normal transistor region and the ESD protection transistor region. Forming first and second gate electrodes on the first insulating film, and forming impurity regions of the second conductivity type on the substrates on both sides of the first and second gate electrodes, and on the normal transistor region. Forming a mask layer on the substrate and implanting ions into the exposed ESD protection transistor region; and removing the mask layer and forming a silicide layer on the first gate electrode and the impurity region in the normal transistor region. Equipped.

Therefore, since the impurity region of the normal transistor is not thin, the leakage current is prevented from flowing, the impurity region of the normal transistor and the mask layer on the gate electrode can be completely removed, thereby preventing the formation of the silicide layer, and the ESD Since the interlayer insulating layers of the protective transistor region and the normal transistor region are formed to have a uniform thickness, not only the contact window can be easily formed but also the aspect ratio of the contact window in the ESD protection transistor region can be reduced to facilitate the formation of the electrode.

Description

Manufacturing Method of Semiconductor Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing silicide from forming in an electrostatic discharge (hereinafter, referred to as ESD) protective transistor during a silicide process. It is about.

As semiconductor devices are highly integrated, impurity regions and wiring widths used as source and drain regions are reduced. As a result, the semiconductor device has a problem in that the resistance of the impurity region and the wiring increases, thereby lowering the operation speed.

Therefore, in the case where the wirings of the elements in the semiconductor device are formed of low-resistance materials such as aluminum alloy and tungsten or made of polycrystalline silicon such as the gate electrode, a silicide layer is formed to reduce the resistance. When the silicide layer is formed on the gate electrode formed of polycrystalline silicon, the silicide layer is formed on the surface of the impurity region to reduce the resistance.

However, the input / output terminals of the semiconductor device are susceptible to breakdown by electrostatic discharge due to a drop in breakdown voltage due to a transient voltage or a thin gate oxide film. That is, if the drain region has a low resistance silicide layer, the applied voltage is not evenly distributed and is concentrated in the LDD (Lightly Doped Drain) region to destroy the semiconductor device. Therefore, an ESD protection transistor is formed to prevent electrostatic discharge destruction by spreading the applied voltage evenly by increasing resistance of an impurity region used as a source and a drain region and a gate electrode formed of polycrystalline silicon in an input / output terminal.

1A to 1E are manufacturing process diagrams of a semiconductor device according to the prior art.

Referring to FIG. 1A, a field oxide film 13 is formed on a predetermined portion of a P-type semiconductor substrate 11 by a local oxide of silicon (LOCOS) method or the like to form an active region of a device, that is, a normal transistor of an internal circuit. The region R1 to be formed and the region R2 in which the ESD protection transistors of the input / output terminals are formed are defined.

Referring to FIG. 1B, the surface of the semiconductor substrate 11 is thermally oxidized to form a gate oxide film 15. The first gate electrode 17 and the input / output terminal are formed on the normal transistor region R1 of the internal circuit by depositing and patterning polycrystalline silicon or amorphous silicon doped with impurities on the field oxide film 13 and the gate oxide film 15. The second gate electrode 18 is defined in the ESD protection transistor region R2. Using the first and second gate electrodes 17 and 18 as a mask on the semiconductor substrate 11 to form an LDD structure by ion implanting N-type impurities such as an asic (As) or phosphorus (P) at low concentrations. The low concentration region 19 is formed.

Referring to FIG. 1C, sidewalls 21 are formed on side surfaces of the first and second gate electrodes 17 and 18. The sidewalls 21 are formed by depositing and etching back the silicon oxide on the semiconductor substrate 11 to cover the first and second gate electrodes 17 and 18. In addition, using the first and second gate electrodes 17 and 18 and the sidewalls 21 as masks, the semiconductor substrate 11 is ionized at high concentration with an N-type impurity such as an asce or phosphorus. The first and second impurity regions 23 and 24 used as source and drain regions of the normal transistor and the ESD protection transistor by implantation are formed to overlap the low concentration region 19.

Referring to FIG. 1D, silicon oxide is deposited on the semiconductor substrate 11 to cover the first and second gate electrodes 17 and 18. The silicon oxide is patterned such that the silicon oxide remains only in the ESD protection transistor region R2 and the normal transistor region R1 is exposed to form a mask layer 25. A high melting point metal such as Ti, W, No, Co, Ta, or Pt is deposited on the semiconductor substrate 11 to cover the first gate electrode 17 and the mask layer 25, and then heat-treated to form the first gate electrode ( 17 and the silicide layer 27 self-aligned on the surface of the first impurity region 23. At this time, the silicide layer 27 is not formed on the side of the first gate electrode 17 by the sidewalls 21, and the second gate electrode 18 and the second impurity region ( It is not formed on the surface of 24).

Referring to FIG. 1E, silicon oxide is deposited on the semiconductor substrate 11 to cover the first gate electrode 17 and the mask layer 25 to form an interlayer insulating layer 28. The interlayer insulating layer 28 is patterned to form a contact window exposing the silicide layer 27 and the second impurity region 24 on the first impurity region 23. Next, an electrode 29 is formed in contact with the silicide layer 27 and the second impurity region 24 through the contact window.

However, the aforementioned method of manufacturing a semiconductor device may be overetched or underetched when etching the silicon oxide on the normal transistor region to form a mask layer in the ESD protection transistor region. In the case of over-etching, since the impurity region used as the source and drain region of the normal transistor becomes thin, a leakage current flows. When over-etching, the silicon oxide forming the mask layer remains on the impurity region and the gate electrode to form a silicide layer. There was a problem to suppress things. In addition, since the thickness of the interlayer insulating layers of the ESD protection transistor region and the normal transistor region is different from each other by the mask layer, it is difficult to form a contact window uniformly, and the aspect ratio of the contact window of the ESD protection transistor region becomes large, making it difficult to form electrodes. There was this.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device which can prevent the leakage current from flowing due to thinning of an impurity region of a normal transistor.

Another object of the present invention is to provide a method of manufacturing a semiconductor device which can prevent the formation of the silicide layer on the impurity region and the gate electrode of the normal transistor.

It is still another object of the present invention to provide a method of manufacturing a semiconductor device capable of forming a uniform thickness of an interlayer insulating layer between an ESD protection transistor region and a normal transistor region.

It is still another object of the present invention to provide a method for manufacturing a semiconductor device capable of reducing the aspect ratio of a contact window of an ESD protection transistor region.

A semiconductor device manufacturing method according to the present invention for achieving the above objects is a step of forming a first insulating film on a semiconductor substrate of the first conductivity type having a normal transistor region and an ESD protection transistor region, and the normal transistor region and ESD Forming first and second gate electrodes on the first insulating film of the protective transistor region, and forming impurity regions of a second conductivity type on substrates on both sides of the first and second gate electrodes; Forming a mask on a transistor region and implanting ions into the exposed ESD protection transistor region; and removing the mask layer and forming a silicide layer on the first gate electrode and the impurity region in the normal transistor region. It is provided.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1A to E are manufacturing process diagrams of a semiconductor device according to the prior art.

2A to F are manufacturing process diagrams of a semiconductor device according to the present invention.

* Explanation of symbols for main parts of the drawings

31: semiconductor substrate 33: field oxide film

35 gate oxide film 37, 38 first and second gate electrodes

39: low concentration region 41: side wall

43, 44: first and second impurity regions

45 mask layer 47 ion implantation region

49 silicide layer 51 interlayer insulating layer

53: electrode

R1: Normal transistor area R2: ESD protection transistor area

2A to F are manufacturing process diagrams of a semiconductor device according to the present invention.

Referring to FIG. 2A, a field oxide film 33 is formed in a predetermined portion of a P-type semiconductor substrate 31 by an LOCOS method or the like to form an active region, that is, a region R11 in which a normal transistor of an internal circuit is to be formed and an input / output terminal. Defines an area (R12) in which the ESD protection transistors of the transistors are to be formed.

Referring to FIG. 2B, the surface of the semiconductor substrate 31 is thermally oxidized to form a gate oxide film 35. In addition, photolithography is performed after depositing polycrystalline silicon or amorphous silicon doped with impurities on the field oxide film 33 and the gate oxide film 35 by chemical vapor deposition (hereinafter, referred to as CVD). The first gate electrode 37 is defined in the normal transistor region R11 of the internal circuit and the second gate electrode 3S is defined in the ESD protection transistor region R12 of the input / output terminal. Using the first and second gate electrodes 37 and 38 as a mask on the semiconductor substrate 31 to form an LDD structure by ion implanting N-type impurities such as an asic (As) or phosphorus (P) at low concentrations. The low concentration region 39 is formed.

Referring to FIG. 2C, silicon oxide is deposited on the semiconductor substrate 31 to cover the first and second gate electrodes 37 and 38 by CVD. The silicon oxide is etched back using a reactive ion etching method (hereinafter referred to as RIE) so that the surfaces of the semiconductor substrate 31 and the first and second gate electrodes 37 and 38 are exposed. The sidewalls 41 are formed on the side surfaces of the first and second gate electrodes 37 and 38. Then, using the first and second gate electrodes 37 and 38 and the sidewalls 41 as masks, the semiconductor substrate 31 is ionized at high concentration with an N-type impurity, such as an ashen or phosphorus, on the semiconductor substrate 31. The first and second impurity regions 43 and 44 used as source and drain regions of the normal transistor and the ESD protection transistor by implantation are formed to overlap the low concentration region 39.

Referring to FIG. 2D, the photoresist is coated on the semiconductor substrate 31 to cover the first and second gate electrodes 37 and 38, and the photoresist is exposed and developed to remain only in the normal transistor region R11 and to protect the ESD. The mask layer 45 is formed by patterning the transistor region R12 to be exposed. In addition, oxygen (O ₂ ) or fluorine (F) is stored in the ESD protection transistor region R12 exposed because the mask layer 45 is not formed, and energy of about ₂ to 30 KeV and about 1 × 10 ^{11 to} 1 × 10 ¹⁴ / cm 2 The ion implantation region 47 is formed in the second gate electrode 38 and the second impurity region 44 by ion implantation at an appropriate dose. At this time, ions are not implanted into the first gate electrode 37 and the first impurity region 43 of the normal transistor region R11 by the mask layer 45. Since the mask layer 45 is formed by applying photoresist and then exposing and developing the photoresist, the surfaces of the semiconductor substrate 31 of the normal transistor region R11 and the ESD protection transistor region R12 are not damaged.

Referring to FIG. 2E, the mask layer 45 is removed. Then, Ti, W, No, Co, Ta, or Pt so as to cover the first and second gate electrodes 37 and 38 and the first and second impurity regions 43 and 44 on the semiconductor substrate 31. A high melting point metal is deposited and then heat treated to form a silicide layer 49 self-aligned on the surfaces of the first gate electrode 37 and the first impurity region 43. At this time, the second gate electrode 38 and the second impurity region 44 do not react with the high melting point metal deposited by oxygen (O 2) or fluorine (F) implanted in the ion implantation region 47 and thus the silicide layer. 49 is not formed. In addition, the side surfaces of the first and second gate electrodes 37 and 38 also do not react with the high melting point metal deposited by the sidewall 41, so that the silicide layer 49 is not formed. In addition, oxygen (O ₂ ) or fluorine (F) in the ion implantation region 47 diffuses during heat treatment to increase the resistance of the second gate electrode 38 and the second impurity region 44 to improve the characteristics of the ESD protection transistor. Improve. Then, the high melting point metal remaining without forming the silicide layer 49 is removed.

Referring to FIG. 2F, silicon oxide is deposited on the semiconductor substrate 31 to cover the first and second gate electrodes 37 and 38 by CVD to form an interlayer insulating layer 51. The interlayer insulating layer 51 is patterned to form a contact window exposing the silicide layer 49 and the second impurity region 44 on the first impurity region 43. In this case, since the interlayer insulating layer 51 is formed to have a uniform thickness in the normal transistor region R1 and the ESD protection transistor region R2, it is easy to form a contact window. Next, an electrode 53 is formed in contact with the silicide layer 49 and the second impurity region 44 through the contact window. At this time, since the aspect ratio of the contact window in the ESD protection transistor region R2 is reduced, the formation of the electrode 53 is easy.

As described above, the method of manufacturing a semiconductor device according to the present invention forms silicide by ion implanting oxygen (O ₂ ) or fluorine (F) into only the ESD protection transistor region on the semiconductor substrate, so that the impurity region and the gate electrode of the normal transistor are formed. Suppression of the formation of the silicide layer can be prevented. Therefore, the gate resistance of the ESD protection transistor can be increased to evenly distribute the applied voltage without reducing the gate resistance of the normal transistor, thereby preventing electrostatic discharge destruction.

Then, since the interlayer insulating layer is formed on the normal transistor region and the ESD protection transistor region to cover the first and second gate electrodes, the interlayer insulating layer is formed to have a uniform thickness. This reduces the aspect ratio of the contact window in the ESD protection transistor region.

Also, in order to implant ions of oxygen (O ₂ ) or fluorine (F) only in the ESD protection transistor region, a mask layer made of photoresist is formed in the normal transistor region so that the impurity region of the normal transistor becomes thinner when the mask layer is removed after ion implantation. To prevent them.

Therefore, it is possible to prevent the leakage current from flowing in the impurity region.

Claims (6)

Forming a first insulating film on the first conductive semiconductor substrate having a normal transistor region and an ESD protection transistor region, and first and second gates on a first insulating film of the normal transistor region and the ESD protection transistor region, respectively. Forming an electrode, forming a second conductivity type impurity region on the substrates on both sides of the first and second gate electrodes, and forming a mask layer on the normal transistor region and exposing the exposed ESD protection transistor region. Implanting ions into the semiconductor layer; and removing the mask layer and forming a silicide layer on the first gate electrode and the impurity region in the normal transistor region. The method of claim 1, further comprising: forming a second insulating film on the entire surface of the resultant, and selectively removing the second insulating film to form a contact window exposing a silicide layer of the normal transistor region and an impurity region of the ESD protection transistor region. And forming an electrode in contact with the silicide layer and the impurity region through the contact window. The method of claim 1, wherein the mask layer is formed of photoresist. The method of claim 1, wherein oxygen (O ₂ ) or fluorine (F) ions are implanted into the ESD protection transistor region. The method of manufacturing a semiconductor device according to claim 4, wherein the ion is implanted with energy of 2 to 30 KeV and dose of 1 × 10 ^{11 to} 1 × 10 ¹⁴ / cm 2. The method of manufacturing a semiconductor device according to claim 1, wherein the silicide layer is formed of a silicide of a high melting point metal of Ti, W, No, Co, Ta, or Pt.