JPS6065537A - Substrate material for semiconductor device - Google Patents

Substrate material for semiconductor device

Info

Publication number
JPS6065537A
JPS6065537A JP17560383A JP17560383A JPS6065537A JP S6065537 A JPS6065537 A JP S6065537A JP 17560383 A JP17560383 A JP 17560383A JP 17560383 A JP17560383 A JP 17560383A JP S6065537 A JPS6065537 A JP S6065537A
Authority
JP
Japan
Prior art keywords
mesh
iron
substrate material
intermediate layer
sintered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17560383A
Other languages
Japanese (ja)
Other versions
JPH061787B2 (en
Inventor
Nobuo Ogasa
小笠　伸夫
Akira Otsuka
昭 大塚
Kazuo Kanehiro
金廣　一雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP58175603A priority Critical patent/JPH061787B2/en
Publication of JPS6065537A publication Critical patent/JPS6065537A/en
Publication of JPH061787B2 publication Critical patent/JPH061787B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29075—Plural core members
    • H01L2224/29076—Plural core members being mutually engaged together, e.g. through inserts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To smoothly dissiplate Joule heat generated by a semiconductor element by employing an iron mesh material as an intermediate layer of a sintered material, thereby improving the thermal conductivity of thicknesswise direction of a substrate material. CONSTITUTION:An intermediate layer 1 of coper or copper alloy sintered material 2 is composed of iron-nickel alloy, and a rate of occupying the mesh material is set by volumetric ratio to 30% or higher as an intermediate layer in the sintered material, and the thermal expansion coefficient of a substrate material is set to 10.0X10<-6>/ deg.C or less. For example, a wire material made of 36%-nickel- iron alloy (Amber) is used to form a wire gauze of 200 mesh. On the other hand, as a sintered material Cu power of -250 mesh is filled in a compression injection mold cavity, tapping is executed, the gauze material is disposed in parallel with the punch surface. Thereafter, the Cu powder is again filled, tapping is performed, and compression molding is performed, and then compression molded product is sintered at 800-900 deg.C.

Description

【発明の詳細な説明】 この発明は半導体素子から発生する熱を有効に放熱する
ことのできる半導体装置用基板材料に関するものである
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a substrate material for a semiconductor device that can effectively dissipate heat generated from a semiconductor element.

従来、一般に半導体素子はロウ付け、または接着用ペー
スト材を用いて基板材料上に接着固定されている。Conventionally, semiconductor elements have generally been adhesively fixed onto substrate materials by brazing or using an adhesive paste material.

このため、基板材料に要求される特性としては、半導体
素子であるＳしやＧａ　Ａｓと熱膨張が一致することが
重要な要件であったが、近年半導体素子の高密度化や高
電力化が進むにつれて、半導体素子に発生するジュール
熱を有効に除去するための放熱特性（熱伝導特性）もま
た非常に重要な因子となってきている。For this reason, an important characteristic required of the substrate material is that the thermal expansion should match that of the S and Ga As semiconductor elements, but in recent years, the density and power of semiconductor elements have increased. As technology progresses, heat dissipation characteristics (thermal conduction characteristics) for effectively removing Joule heat generated in semiconductor devices are also becoming a very important factor.

このため、半導体素子が小型で基板材料との熱膨張係数
の差により生ずる応力が小さい場合には、基板材料とし
て銅または銅合金が用いられることが多かった。For this reason, when the semiconductor element is small and the stress caused by the difference in thermal expansion coefficient with the substrate material is small, copper or a copper alloy is often used as the substrate material.

これに対して半導体素子が大型化すると、基板材料との
熱膨張係数の差により生ずる応力が太きくなり、半導体
素子の基板からの剥離や破壊が生じやずくなるのである
。On the other hand, as the semiconductor element becomes larger, the stress generated due to the difference in thermal expansion coefficient with the substrate material increases, making it difficult for the semiconductor element to peel off from the substrate or break.

そこで基板月利の熱膨張係数を半導体素子の熱６ 膨張係数（例えばＳｉ　：　４．ＯＸ　１０ｃｍ４℃、
−八〇：６ ６．７ｘ　１０ｃｍ　１ｍ　℃）に近似させ、なおかつ
熱伝導度を向」：させるために、］バール（２９％ＮＬ
−１７％ら−Ｆｅ　）、４２−アロイ（４２％ＮＬＦｅ
）などの低熱膨張合金を中心ｖＪＮ’ｉｌとして、その
両面に銅を被覆した三層複合合金条が提案され、一部で
使用されている。Therefore, the thermal expansion coefficient of the substrate monthly rate is calculated as the thermal expansion coefficient of the semiconductor element (for example, Si: 4.OX 10cm 4℃,
-80:6 6.7x 10cm 1m ℃), and in order to improve the thermal conductivity,
-17% et al-Fe), 42-alloy (42%NLFe
A three-layer composite alloy strip consisting of a low thermal expansion alloy such as VJN'il as the core and coated with copper on both sides has been proposed and is used in some cases.

しかしながら、この金属条では条の長手方向の熱伝導率
は銅の被覆比率に応じて著しく改善されるが、特に熱放
散性の点で重要な条の板厚方向の熱伝導率はあまり改善
されず、従ってその実用範囲が限定されていた。However, with this metal strip, although the thermal conductivity in the longitudinal direction of the strip is significantly improved depending on the copper coating ratio, the thermal conductivity in the thickness direction of the strip, which is particularly important from the point of view of heat dissipation, is not improved much. Therefore, its practical range has been limited.

この発明は上記のような従来の基板材料の欠点を改善す
るためになされたものであり、焼結体の中間層として鉄
系網状体を用いることにより、基板材料の板厚方向の熱
転７５特性を向上させ、了導体素子より生ずるジュール
熱の放散をスムーズにした半導体装置用基板材料を提供
することを目的とするものである。This invention was made in order to improve the drawbacks of the conventional substrate materials as described above, and by using an iron-based mesh as the intermediate layer of the sintered body, the heat transfer in the thickness direction of the substrate material is improved. The object of the present invention is to provide a substrate material for a semiconductor device that has improved characteristics and allows smooth dissipation of Joule heat generated from a conductor element.

即ちこの発明の基板材料は第１図＋１１、ｆｌｌ）にそ
の構造を示すように、銅または銅合金焼結体２の中間層
１を鉄−ニッケル合金で形成した網状体にて構成したも
のである。That is, the substrate material of the present invention, as shown in FIG. be.

この発明において基板材料として焼結体を用いたのは、
圧接方法では工業的製造が困難であること、および圧接
後にウィスカーのまわりにボアーが生じてこの発明の目
的とする板厚方向の高熱伝導を達成できないためである
。またこの他の理由どしては、この発明になる基板材料
の使用目的が半導体双子搭載用であり、実際の使用に際
しては、複雑な形状となることもあるのでこの点をも考
慮したものである。The reason why a sintered body is used as a substrate material in this invention is because
This is because industrial manufacturing is difficult using the pressure welding method, and bores are formed around the whiskers after pressure welding, making it impossible to achieve the high thermal conductivity in the thickness direction, which is the objective of the present invention. Another reason is that the substrate material of the present invention is intended to be used to mount semiconductor twins, and in actual use, it may have a complicated shape, so this point was also taken into consideration. be.

また焼結体中の中間層として単一もしくは複数の鉄−ニ
ッケル合金からなる網状材の占める割合を体積比で３０
％以上、さらに網状体を構成する鉄−ニッケル合金中の
ニッケル含有準を２０〜６０重Ｈ％とするのは、これら
の範囲外ではこの発明で目６ 的と覆る基板４Ｊ　＄ｌ＋１の熱膨張係数が１０．ＯＸ
　１０ｃｍ　１ｍ℃以下どならないためである。In addition, the volume ratio of the network material made of single or multiple iron-nickel alloys as the intermediate layer in the sintered body is 30%.
% or more, and the nickel content in the iron-nickel alloy constituting the network body is set to 20 to 60% by weight, outside these ranges, the thermal expansion of the substrate 4J $l+1, which is the target of this invention, is The coefficient is 10. OX
This is to ensure that the temperature does not drop below 10cm and 1m℃.

また鉄−ニッケル合金よりなる網状材の開口面積を搭載
する半導体素子より小さくしているのは、半導体素子接
合部のミクロ的な熱膨張をも改善するためである。Further, the reason why the opening area of the mesh material made of iron-nickel alloy is made smaller than that of the semiconductor element on which it is mounted is to improve the microscopic thermal expansion of the semiconductor element junction.

さらに網状材の平面を焼結体の少くとも一面に平行にな
るように配置するのは、半導体素子搭載にＬ１３ける重
要な熱膨張が、ペレット平面方向にあるためである。Furthermore, the reason why the plane of the net-like material is arranged parallel to at least one surface of the sintered body is that the important thermal expansion in L13 for mounting a semiconductor element is in the plane direction of the pellet.

また半シヘ体素子の取イー１けを考慮して、基板材料の
該素子取伺喘面にはＡｕ、Ａｇ、α、Ｎし半田メッキ等
を施づこと【ま何ら差支えない。In addition, considering the cost of the half-circumferential element, it is acceptable to apply solder plating or the like with Au, Ag, α, or N to the surface of the substrate material that supports the element.

ｊス下この発明を実施例により説明する。The present invention will now be described by way of examples.

実施例 ３６％ニッケルー鉄合金（アンバー）よりなる線材を用
いて２００メツシユの網状材を形成した。Example 3 A wire rod made of 6% nickel-iron alloy (umber) was used to form a 200-mesh mesh material.

一方焼結材としては一２５０メッシコの廓粉末を圧縮成
形用金をキャピティに初期充填し、タッピングを施した
の１５、上記網状材をパンチ面に平行に配置した。その
後この上に再びＱＬ粉末の充填を行いタッピング後圧縮
成形を行った。On the other hand, as a sintering material, a cavity was initially filled with powder for compression molding of 1,250 mesh, and tapping was performed.The mesh material was placed parallel to the punch surface. Thereafter, QL powder was again filled on top of this, and compression molding was performed after tapping.

次いでこの圧縮成形体を８００〜９００℃で焼結した。Next, this compression molded body was sintered at 800 to 900°C.

かくして得られた焼結体について熱膨張係数および熱伝
導度の測定を行ったところ、前者については第２図、後
者については第３図の結果が得られ、この焼結体が半導
体装置用基板材料として熱膨張係数および熱放散性の双
方ともに良好であることが認められた。When the thermal expansion coefficient and thermal conductivity of the sintered body thus obtained were measured, the results shown in Figure 2 for the former and Figure 3 for the latter were obtained, and this sintered body was used as a substrate for semiconductor devices. The material was found to have good thermal expansion coefficient and heat dissipation.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図［１１はこの発明の半導体装置用基板材料の平面
図、第１図（Ｉｌｌは第１図の△−Ａ線断面図、第２図
はこの発明の半導体装置用基板材わ１の熱膨張係数を示
すグラフ、第３図は同じく熱伝導度を示すグラフである
。 特許出願人　住友電気工業株式会社 代　理　人　弁理士　和　１）　昭 ９８　呂　ｇさ く　−）、　−′’　７　′ｔ／ｉ−２ノ＊ｖ”：ｙ＊
茸　９　ｃｏ　ψ　寸　〜FIG. 1 [11 is a plan view of the substrate material for a semiconductor device of the present invention, FIG. 1 (Ill is a cross-sectional view taken along the line Δ-A in FIG. The graph showing the coefficient of thermal expansion and Figure 3 are also graphs showing the thermal conductivity. Patent applicant Sumitomo Electric Industries Co., Ltd. Agent Patent attorney Kazu 1) 1988 Ryo gsaku -), -''7' t/i-2ノ*v”:y*
Mushroom 9 co ψ size ~

Claims (1)

【特許請求の範囲】 ｆｉｌ　ｆｌｌｌｉｌあるいは銅合金焼結体よりなる基
板材！３１に、１−３いて、該焼結体の中間層として単
一もしくは複数の鉄−ニッケル合金からなる網状材が３
０ｖｏ１％以上存在し、かつ該中間層と平行となる焼結
体面の熱膨張係数が１０×１０／℃以下であることを特
徴とする半導体装置用基板材料。 （２）　網状材を構成する鉄−ニッケル合金中にニッケ
ルが２０〜６０重量％含有することを特徴とする特許請
求の範囲第１項記載の半導体装置用基板材料。 （３）網状材の開口面積が半導体素子より小さいことを
特徴とする特許請求の範囲第１項記載の半唇体装置ｒｑ
用基板拐１３１　。 （４）網状材の平面が焼結体の少くとも一面に対[Claims] Substrate material made of fil flllil or copper alloy sintered body! In 31, in 1-3, a mesh material made of one or more iron-nickel alloys is used as an intermediate layer of the sintered body.
1. A substrate material for a semiconductor device, characterized in that the content is 0vo1% or more, and the coefficient of thermal expansion of the surface of the sintered body parallel to the intermediate layer is 10×10/° C. or less. (2) The substrate material for a semiconductor device according to claim 1, wherein the iron-nickel alloy constituting the net-like material contains 20 to 60% by weight of nickel. (3) The hemilip body device rq according to claim 1, wherein the opening area of the net-like material is smaller than that of the semiconductor element.
PC board removal 131. (4) The plane of the net material faces at least one surface of the sintered body.
JP58175603A 1983-09-20 1983-09-20 Substrate for semiconductor device Expired - Lifetime JPH061787B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58175603A JPH061787B2 (en) 1983-09-20 1983-09-20 Substrate for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58175603A JPH061787B2 (en) 1983-09-20 1983-09-20 Substrate for semiconductor device

Publications (2)

Publication Number Publication Date
JPS6065537A true JPS6065537A (en) 1985-04-15
JPH061787B2 JPH061787B2 (en) 1994-01-05

Family

ID=15998975

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58175603A Expired - Lifetime JPH061787B2 (en) 1983-09-20 1983-09-20 Substrate for semiconductor device

Country Status (1)

Country Link
JP (1) JPH061787B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH029155A (en) * 1988-03-10 1990-01-12 Texas Instr Inc <Ti> Composite metal material
JPH02198147A (en) * 1989-01-26 1990-08-06 Omron Tateisi Electron Co Ic package
JP2001102701A (en) * 1999-09-28 2001-04-13 Kyocera Corp Wiring board

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55127044A (en) * 1979-03-26 1980-10-01 Hitachi Ltd Electric circuit substrate and its manufacture
JPS55159967A (en) * 1979-05-08 1980-12-12 Hascoe Norman Heat transmitting metallic plate unit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55127044A (en) * 1979-03-26 1980-10-01 Hitachi Ltd Electric circuit substrate and its manufacture
JPS55159967A (en) * 1979-05-08 1980-12-12 Hascoe Norman Heat transmitting metallic plate unit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH029155A (en) * 1988-03-10 1990-01-12 Texas Instr Inc <Ti> Composite metal material
JPH02198147A (en) * 1989-01-26 1990-08-06 Omron Tateisi Electron Co Ic package
JP2001102701A (en) * 1999-09-28 2001-04-13 Kyocera Corp Wiring board

Also Published As

Publication number Publication date
JPH061787B2 (en) 1994-01-05

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