JPS60136355A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60136355A
JPS60136355A JP58243902A JP24390283A JPS60136355A JP S60136355 A JPS60136355 A JP S60136355A JP 58243902 A JP58243902 A JP 58243902A JP 24390283 A JP24390283 A JP 24390283A JP S60136355 A JPS60136355 A JP S60136355A
Authority
JP
Japan
Prior art keywords
header
resin
lead
chip
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58243902A
Other languages
Japanese (ja)
Inventor
Masao Yamaguchi
正男 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58243902A priority Critical patent/JPS60136355A/en
Publication of JPS60136355A publication Critical patent/JPS60136355A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE:To augment power as well as heat dissipating capacity by a method wherein at least backside of a header is made of base metal as it is but not plating-processed. CONSTITUTION:A lead-frame composed of a lead 2, a header 4 and a guide 7 is made of a copper sheet patterned and bent by means of a precision press machine etc. Besides, the surface side of the header 4 fitted with chip 12 is coated with Ni plated layer 13 while the backside of the same 4 is not coated with the Ni plated layer 13 since the surface side only of the copper sheet is preliminarily Ni plated. In such a leadframe, another chip 11 is fixed on the header 4 using a solder 14 while the wire 12 made of aluminium is connected to the chip 11 by means of supersonic wirebonding process. At this time, the Ni plated layer 13 contributes to the excellent connection while the resin below the header 4 is made thinner to reduce the thermal resistance.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は絶縁型パワートランジスタ等の半導体装置に関
する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to semiconductor devices such as insulated power transistors.

〔背景技術〕[Background technology]

レジンパッケージ型半導体装置の組立にあっては一般に
金属製のリードフレームが採用されている。リードフレ
ームは鉄−ニッケル系合金、銅まｆＣ＃′ｉ、銅系合金
が木材として使用されている。また、リードフレームは
その表面にメッキが施されている。これはリードフレー
ムにおけるチップ（ダイ）ボンド、ワイヤボンドのため
、あるいは外装上必要となる（電子材料、１９８３年８
月号７５〜７９頁；リードフレーム用銅系材料、にも記
載されている。）。Metal lead frames are generally used in the assembly of resin packaged semiconductor devices. The lead frame is made of iron-nickel alloy, copper fC#'i, or copper alloy as wood. Furthermore, the surface of the lead frame is plated. This is necessary for chip (die) bonding, wire bonding in lead frames, or for exterior packaging (Electronic Materials, 1983, August 1983).
It is also described in "Copper-based materials for lead frames," pp. 75-79 of the issue. ).

一方、最近、ヘッダの主面上にチップ（半導体素子）を
固定し、かつヘッダの裏面側をも薄いレジンで被った絶
縁型のパワートランジスタが開発されている。たとえば
、その一つの例として、電子材料、１９８１年１１月号
４２〜４６頁に絶縁型パワートランジスタが紹介されて
いる。On the other hand, recently, an insulated power transistor has been developed in which a chip (semiconductor element) is fixed on the main surface of a header, and the back surface of the header is also covered with a thin resin. For example, as one example, an insulated power transistor is introduced in the November 1981 issue of Electronic Materials, pages 42-46.

ところで、このような絶縁型パワートランジスタを表面
にニッケル（Ｎｌ）メッキを施した銅（Ｃｕ）のリード
フレームを用いて製造した場合、つぎのような問題点が
生じるということが本発明者によりてあきらかとされ＆
。By the way, the inventor has found that when such an isolated power transistor is manufactured using a copper (Cu) lead frame whose surface is plated with nickel (Nl), the following problems occur. It is obvious &
.

すなわち、絶縁型パワートランジスタはチップで発生し
た熱をヘッダ、レジンを介して取付板に有効に伝達させ
ることによって安定動作する。しかし、Ｃｕの熱伝導率
は３．８５　Ｘ　１０−”　Ｊ　７ｃｍ　・Ｓ−Ｃと良
いが、Ｎｌの熱伝導率はＯ，９１Ｘ１０一番Ｊ／ｃｍ１
３＊Ｅと悪い。このため、ヘッダの下面にＮｉ　メッキ
層が存在すると、熱抵抗が高く良好な熱放散ができなく
なり、パワー（Ｐｃ）が低下する。That is, the insulated power transistor operates stably by effectively transmitting heat generated in the chip to the mounting plate via the header and resin. However, the thermal conductivity of Cu is good at 3.85 x 10-" J 7cm ・S-C, but the thermal conductivity of Nl is O.91 x 10 J/cm1
3*E and bad. Therefore, if a Ni plating layer exists on the lower surface of the header, the thermal resistance is high and good heat dissipation cannot be achieved, resulting in a decrease in power (Pc).

また、ヘッダの下面の薄いレジン部分にふくれが生じて
しまい実装時の熱放散性能が低下する。In addition, bulges occur in the thin resin portion on the lower surface of the header, reducing heat dissipation performance during mounting.

これはレジンとＮｉ　メッキ層との接着性（密着性）の
悪さによるものであり、界面に巻き込まれた空気の膨張
によって起きることも本発明者によってあきらかとされ
ｆｃｎ　これに対し、ヘッダの下面にＮｉ　メッキ層を
設けずに銅素地面としておくと、このようなふくれは起
きないことも本発明者によってあきらかとされた。This is due to poor adhesion between the resin and the Ni plating layer, and the inventor has also clarified that this is caused by the expansion of air caught in the interface. The inventors have also found that such blistering does not occur if a copper base surface is used without providing a Ni plating layer.

〔発明の目的〕[Purpose of the invention]

本発明は熱放散性が良好でパワー（Ｐｃ）の増大を図る
ことができる絶縁型トランジスタを提供することにある
。An object of the present invention is to provide an insulated transistor that has good heat dissipation properties and can increase power (Pc).

本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

〔発明の概要〕[Summary of the invention]

本願において開示される発明のうち代表的なものの概要
を簡単に説明すれは、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.

すなわち、本発明の絶縁型パワートランジスタは、チッ
プボンド、ワイヤポンドを良好にするためにヘッダの主
面およびリードの主面には銅素材の表面ＫＮｉ　メッキ
層を設けであるが、ヘッダの裏面にＦｉＮＩ　メッキ層
は設けてない。このため、レジンけＮｉ　よりも密着度
が良いＣｕと直接接触するためヘッダとレジンパッケー
ジとの密着性は良好となるとともに、Ｃｕ　よりも熱伝
導率が悪いＮ１がレジンとヘッダ間に介在しないため、
トランジスタの熱抵抗は低減し、熱放散効率の向上から
パワー（Ｐｃ）の向上が達成できる。That is, in the insulated power transistor of the present invention, a surface KNi plating layer of a copper material is provided on the main surface of the header and the main surface of the leads in order to improve chip bonding and wire bonding. FiNI plating layer is not provided. Therefore, the adhesion between the header and the resin package is good because it comes into direct contact with Cu, which has better adhesion than resin-based Ni, and because N1, which has a lower thermal conductivity than Cu, does not exist between the resin and the header. ,
The thermal resistance of the transistor is reduced, and the power (Pc) can be improved by improving heat dissipation efficiency.

〔実施例〕〔Example〕

第１図は本発明の一実施例による絶縁型パワートランジ
スタの斜視図、第２図は第１図の■−■線に沿う拡大断
面図である。FIG. 1 is a perspective view of an insulated power transistor according to an embodiment of the present invention, and FIG. 2 is an enlarged sectional view taken along the line 1--2 in FIG.

本実施例の絶縁型パワートランジスタは第１図に示すよ
うに、矩形のレジンパッケージ１と、このレジンパンケ
ージ１の一端面から突出する３本のリード２とからなっ
ている。また、レジンパッケージ１にはトランジスタの
実装時にねじを挿し込む取付孔３が設けられている。こ
の取付孔３は絶縁性のレジンパッケージ１によって形成
されている。As shown in FIG. 1, the insulated power transistor of this embodiment consists of a rectangular resin package 1 and three leads 2 protruding from one end surface of this resin pan cage 1. Further, the resin package 1 is provided with a mounting hole 3 into which a screw is inserted when mounting a transistor. This attachment hole 3 is formed by an insulating resin package 1.

前記リード２のうち、中央のリードはコレクタ用リード
となり、レジンパッケージ１内で途中から下方に折れ曲
がり、幅広のヘッダ４に連結している。このヘッダ４は
リード２に近い幅広のチップ取付部５と、このチップ取
付部５よりもわずかに幅が狭く中央ＫＸ通孔６を有する
取付孔形成部７とからなっている、この貫通孔６ｉｉ：
前記レジンパッケージ１の取付孔３よりも直径が大きく
なっている。貫通孔６と取付孔３の間のレジン８は取付
孔３に挿入するねじとへラダ４との間の放電を防止する
絶縁部材となることから、必要な耐圧に合せて貫通孔６
と取付孔３の直径を選択する必要がある。また、ヘッダ
４の取付孔形成部側の先端には１対の細いガイド９が設
けられている。このガイド９は途中で一段高くなりその
先端は前記リード２と同じ高さとなっている。このガイ
ド９およびリード２けレジンパッケージ１を形成する際
のレジンモールド時、モールドの上下型に挾持されて支
持され、モールド型によって形成されるキャビティ内に
ヘッダを宙吊りにする働きをし、ヘッダ４の下面に形成
される薄いレジン８の厚さを均一にする役割を果たす。Among the leads 2, the central lead serves as a collector lead, is bent downward from the middle within the resin package 1, and is connected to a wide header 4. This header 4 consists of a wide chip mounting part 5 close to the lead 2, and a mounting hole forming part 7 which is slightly narrower than this chip mounting part 5 and has a central KX through hole 6. This through hole 6ii :
The diameter is larger than that of the attachment hole 3 of the resin package 1. The resin 8 between the through hole 6 and the mounting hole 3 serves as an insulating member that prevents electrical discharge between the screw inserted into the mounting hole 3 and the ladder 4.
It is necessary to select the diameter of the mounting hole 3. Further, a pair of thin guides 9 are provided at the tip of the header 4 on the side where the attachment hole is formed. This guide 9 becomes one step higher in the middle, and its tip is at the same height as the lead 2. During resin molding to form the guide 9 and the two-lead resin package 1, the header 4 is supported by being sandwiched between the upper and lower dies of the mold, and functions to suspend the header in the cavity formed by the mold. It serves to make the thickness of the thin resin 8 formed on the lower surface of the resin uniform.

なお、このことから、ヘッダがキャビティ底面に対して
平行に維持できるモールド型構造であれば、リード２の
高さとガイド９の高さは同一でなくともよい。また、ガ
イド９はレジンモールド後にリードフレームの枠部から
切断分離されることから、その先端はレジンパッケージ
１の一端面かられずかに突出している。Note that, from this, the height of the lead 2 and the height of the guide 9 do not have to be the same as long as the header has a mold type structure that can be maintained parallel to the bottom surface of the cavity. Furthermore, since the guide 9 is cut and separated from the frame portion of the lead frame after resin molding, its tip slightly protrudes from one end surface of the resin package 1.

他方１両側に位置する２本のり一ド２はそれぞれエミッ
タリード、ベースリードとなり、レジンパッケージ１の
内部に位置する先端部分は部分的にくびれるとともに、
先端は幅広となり、ワイヤ接続部１０を構成している。The two leads 2 located on both sides of the other 1 serve as an emitter lead and a base lead, respectively, and the tip portion located inside the resin package 1 is partially constricted.
The tip is wide and forms a wire connection section 10.

前記細いくびれは、レジンパッケージｌにワイヤ接続部
１０が喰い込んでリード２が抜けないようにするために
設けられる。また、これらリード２のワイヤ接続部１０
には、ヘッダ４のチップ取付部５に固定されたチップ１
１の電極（エミッタ電極、ペース電極）に一端が接続さ
れたワイヤ１２の他端が接続されている。The narrow constriction is provided to prevent the wire connection portion 10 from biting into the resin package l and the lead 2 from coming out. In addition, the wire connection portion 10 of these leads 2
The chip 1 fixed to the chip mounting part 5 of the header 4 is shown in FIG.
One end of a wire 12 is connected to one electrode (emitter electrode, pace electrode), and the other end of the wire 12 is connected to one electrode (emitter electrode, pace electrode).

前記リード２．へラダ４．ガイド９は一枚の薄い銅板を
精密プレス等でパターニングしかつ折り曲げられ、Ｉ、
　リードフレームの各構成部分の一つである。また、こ
の銅板の主面にはあらかじめニッケル（Ｎｉ）メッキが
施されであることから、チップ１２が取り付けられるヘ
ッダ４の主面側にはＮｉメッキ層１３が被着され、へラ
ダ４の裏面側にはＮｉメッキ層は存在しない。このよう
なリードフレームではチップ１１は半田１４によってヘ
ッダ４に固定され、アルミニウムからなるワイヤ１２は
超音波ワイヤボンディングによって接続される。そして
、これらの接続において、前記Ｎｉ　メ、ツキ層１３は
良好な接続を可能としている。なお、へラダ４の下方の
レジン厚さは最大でも０．５　ｍｍと極めて薄く、トラ
ンジスタを取り付ける取付板１５との間に絶縁がとれる
最小厚さとなり、熱抵抗ができるだけ小さくなるように
配慮されている。The lead 2. Herada 4. The guide 9 is made by patterning a thin copper plate using a precision press or the like and bending it.
It is one of each component of the lead frame. In addition, since the main surface of this copper plate is plated with nickel (Ni) in advance, the Ni plating layer 13 is deposited on the main surface side of the header 4 to which the chip 12 is attached, and the back surface of the header 4 is coated with a Ni plating layer 13. There is no Ni plating layer on the side. In such a lead frame, the chip 11 is fixed to the header 4 by solder 14, and the wire 12 made of aluminum is connected by ultrasonic wire bonding. In these connections, the Ni metal layer 13 enables good connections. Note that the resin thickness below the spatula 4 is extremely thin, at most 0.5 mm, which is the minimum thickness that provides insulation between it and the mounting plate 15 to which the transistor is attached, and is designed to minimize thermal resistance. ing.

〔効果〕〔effect〕

（１）　本発明のトランジスタは、ヘッダ４の下方には
熱伝導率の悪いＮｉ　メッキ層１３が存在しないことか
ら熱抵抗の低減が達成できる、 （２）本発明のトランジスタは、ヘッダ４の下面にはレ
ジン８との容着性（接着性）が悪いＮｌ　メッキ層１３
が存在せず、レジン８けレジンとの接着性が良好な銅の
へラダ４と直接接触するため、レジンモールド時にへラ
ダ４とレジン８との間に空気が入り込まず、薄いレジン
のふくれ等は発生することがなくなり、熱抵抗の増大が
防げる。(1) In the transistor of the present invention, since the Ni plating layer 13 with poor thermal conductivity does not exist below the header 4, a reduction in thermal resistance can be achieved. (2) In the transistor of the present invention, the lower surface of the header 4 Nl plating layer 13 has poor adhesion (adhesion) with resin 8.
Since there is no resin 8 and there is direct contact with the copper spatula 4, which has good adhesion with the resin, air does not get trapped between the spatula 4 and the resin 8 during resin molding, preventing blistering of the thin resin. will not occur, and an increase in thermal resistance can be prevented.

（３）上記ｆｌ）、　＋２）から熱抵抗の低減が図れる
ため、トランジスタの熱放散効率が同上し、パワー（Ｐ
ｃ）の向上が達成できる。たとえば、Ｐｃは本発明構造
によりたとえば約１％向上した。(3) Since the thermal resistance can be reduced from fl) and +2) above, the heat dissipation efficiency of the transistor is the same as above, and the power (P
Improvement in c) can be achieved. For example, Pc was improved by about 1% with the structure of the present invention.

（４）上記（３）からＰｃの向上が図れるため、トラン
ジスタ設計上ｐｃのマージン向上が図れる効果が得られ
る。(4) Since it is possible to improve Pc from the above (3), it is possible to achieve the effect of improving the margin of PC in terms of transistor design.

（５）本発明のトランジスタは、その製造において用い
られるリードフレームには一面にのみしかＮｉメッキ層
１３が設けられないため、Ｎｉ　メッキコストの低減が
図れる結果、製造コストの軽減が達成できる。(5) In the transistor of the present invention, since the Ni plating layer 13 is provided only on one side of the lead frame used in its manufacture, the Ni plating cost can be reduced, and as a result, the manufacturing cost can be reduced.

以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、そσ）要旨を逸脱しない範囲で種々変更
可能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on examples, the present invention is not limited to the above examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say.

たとえば、第３図に示すように、へラダ４．リード２．
カイト９の表面にＦｉＮｉ　メッキ層は全く設けない構
造にすれば、前記実施例と１中様な効果が得られるとと
もに、トランジスタの製造においてメッキ工程が不要と
なるため、トランジスタの製造コストの低減が達成でき
る。これは、チップ１１、ワイヤ１２の接続は還元性雰
囲気で行なうことによって、Ｃｕ製のへ・ラダ４．リー
ド２に確実に接続できる本出願人の８発した技術により
可能となる。For example, as shown in FIG. Lead 2.
If the structure is such that no FiNi plating layer is provided on the surface of the kite 9, effects similar to those of the above embodiment can be obtained, and the plating process is not required in the manufacture of the transistor, so the manufacturing cost of the transistor can be reduced. It can be achieved. This can be done by connecting the chip 11 and the wire 12 in a reducing atmosphere to the copper ladder 4. This is made possible by the technique developed by the present applicant, which enables reliable connection to the lead 2.

また、この実施例のトランジスタは、へ、２ダ４゜ガイ
ド９．リード２の表面がレジン８との接着性が良好な銅
素地面となっていることから、レジン８との接着性が良
好で界面にはクラック、空隙等は存在し難くなり、耐湿
性の向上が達成できる。In addition, the transistor of this embodiment has a 2×4° guide 9. Since the surface of the lead 2 is a copper base surface that has good adhesion with the resin 8, it has good adhesion with the resin 8, making it difficult for cracks and voids to exist at the interface, improving moisture resistance. can be achieved.

さらに、本発明のトランジスタは前記のように耐湿性が
高いことから、耐湿性をさらに高めようとするチッブコ
ーＨａｔ必ずしも必要とはならず、製作コストが軽減で
きる。Furthermore, since the transistor of the present invention has high moisture resistance as described above, a Chibko hat for further increasing moisture resistance is not necessarily required, and manufacturing costs can be reduced.

〔利用分野〕[Application field]

以上の訝明では主として本発明者によってなされた発明
をその背景となった利用分野である絶縁型パワートラン
ジスタ技術に適用した場合について説明したが、それに
限定されるものではなく、たとえば、ダイオード、集積
回路装置等の牛導体装置にも適用でき、同様の効果が得
られる。In the above discussion, we have mainly explained the case where the invention made by the present inventor is applied to the field of application, which is the isolated power transistor technology, but it is not limited thereto. It can also be applied to conductor devices such as circuit devices, and similar effects can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例による絶縁型パワートランジ
スタの斜視図、 第２図は第１図の■−■線に沿う拡大断面図、ｍ３図ｔ
ま他の実施例によるトランジスタの拡大断面図である。 １・・・レジンパッケージ、２・・・リード、３・・・
取付孔、４・・・ヘッダ、訃・・チップ取付部、６・・
・貫通孔、７・・・取付孔形成部、８・・・レジン、９
・・・ガイド。 １０・・・ワイヤ接続部、１１・・・チップ、１２・・
・ワイヤ、１３・・・Ｎ１　メッキ層、１４・・・半田
、１５・・・取付板。 目′Fig. 1 is a perspective view of an insulated power transistor according to an embodiment of the present invention, Fig. 2 is an enlarged sectional view taken along the line ■-■ in Fig. 1, and Fig. m3 t.
FIG. 7 is an enlarged cross-sectional view of a transistor according to another embodiment. 1...Resin package, 2...Lead, 3...
Mounting hole, 4...Header, End...Chip mounting part, 6...
・Through hole, 7... Mounting hole forming part, 8... Resin, 9
···guide. 10... Wire connection part, 11... Chip, 12...
-Wire, 13...N1 plating layer, 14...solder, 15...mounting plate. eye'

Claims (1)

【特許請求の範囲】[Claims] １、半導体チップが主面に固定された金属製のヘッダと
、ヘッダの主面および裏面側を被う樹脂封止パッケージ
とを有する半導体装置であって、前記ヘッダの少なくと
も慮面はメッキ層が設けられず罠金属素地面となってい
ることを特徴とする半導体装置。1. A semiconductor device having a metal header having a semiconductor chip fixed to its main surface, and a resin-sealed package covering the main surface and back side of the header, wherein at least a surface of the header has a plating layer. A semiconductor device characterized in that it is not provided with a trap metal base surface.
JP58243902A 1983-12-26 1983-12-26 Semiconductor device Pending JPS60136355A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58243902A JPS60136355A (en) 1983-12-26 1983-12-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58243902A JPS60136355A (en) 1983-12-26 1983-12-26 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS60136355A true JPS60136355A (en) 1985-07-19

Family

ID=17110694

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58243902A Pending JPS60136355A (en) 1983-12-26 1983-12-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60136355A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9845525B2 (en) 2012-04-24 2017-12-19 Nippon Steel & Sumitomo Metal Corporation Equipment system for producing piercing-rolling plug

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9845525B2 (en) 2012-04-24 2017-12-19 Nippon Steel & Sumitomo Metal Corporation Equipment system for producing piercing-rolling plug

Similar Documents

Publication Publication Date Title
US5902959A (en) Lead frame with waffled front and rear surfaces
US5424251A (en) Method of producing semiconductor device having radiation part made of resin containing insulator powders
US6621152B2 (en) Thin, small-sized power semiconductor package
US6157074A (en) Lead frame adapted for variable sized devices, semiconductor package with such lead frame and method for using same
JPH0864634A (en) Semiconductor device and production thereof
JP2000003988A (en) Lead frame and semiconductor device
JP5103731B2 (en) Mold package
WO1990013914A1 (en) Lead frame for semiconductor devices
JPS60136355A (en) Semiconductor device
JPH04174547A (en) Surface-mounting type power semiconductor device
JPH0666354B2 (en) Semiconductor device
JP3576228B2 (en) Surface mount type semiconductor device
JPS61242051A (en) Lead frame
KR0159985B1 (en) Semiconductor package heat sink structure
CN211017068U (en) Semiconductor packaging structure
KR100252862B1 (en) Semiconductor package and method for fabricating the same
JP2003078101A (en) Semiconductor device, lead frame provided to the same, and its manufacturing method
JPS6042853A (en) Semiconductor device
JPH0333068Y2 (en)
GB2147457A (en) Encapsulated semiconductor device with composite conductive leads
JP2004335947A (en) Semiconductor device and formation method thereof
JPH03241765A (en) Semiconductor device
JP2003243599A (en) Lead frame and semiconductor device
JPS607750A (en) Insulation type semiconductor device
JPS59101843A (en) Resin sealed type electronic component part