JPS6042853A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6042853A
JPS6042853A JP58150773A JP15077383A JPS6042853A JP S6042853 A JPS6042853 A JP S6042853A JP 58150773 A JP58150773 A JP 58150773A JP 15077383 A JP15077383 A JP 15077383A JP S6042853 A JPS6042853 A JP S6042853A
Authority
JP
Japan
Prior art keywords
tab
pellet
lead frame
semiconductor device
inner lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58150773A
Other languages
Japanese (ja)
Inventor
Shoichi Ogura
小倉　昭一
Tomoichi Oku
倶一 奥
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58150773A priority Critical patent/JPS6042853A/en
Publication of JPS6042853A publication Critical patent/JPS6042853A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/01082—Lead [Pb]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce the cost without the use of Au and Ag by a method wherein only the surface tip region of inner leads in proximity to the tab part of the frame on the side of pellet mounting is provided with an Al layer, which is then connected to the Al electrode of the pellet by means of Al alloy wires, in the title device using the lead frame. CONSTITUTION:Etching or press-punching is carried out to a 42% Ni-Fe alloy plate, which is thus formed into the lead frame of a required pattern. Next, the part other than the tab proximity section 8 at the tip of the inner lead 2 opposed to the tab 1 where the pellet is placed is covered with silicon rubber approx. 0.5-50mm. thick, and the Al layer is formed at the section 8 by electroplating. Thereafter, the pellet is fixed on the tab 1 with Ag paste, and the electrode provided thereto and the section 8 are brought into bonding connection by means of the Al fine wires. Afterwards, it is resin-sealed in usual manner.

Description

【発明の詳細な説明】 本発明は、半導体装置に係υ、特に樹脂封止血中導体装
置の構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to the structure of a resin-sealed blood conductor device.

樹脂封止型半導体装置を作るには、複数のリードを一体
に形成してなる、リードフレームを使用し、このリード
フレームの金（以下Ａｕ　）めっき又は銀（以下ＡＪ）
めっきされた半導体素子（以下ベレットと呼ぶ）載１ｔ
ｍ（以下タブ部と呼ぶ）にそのまま又は適当なろう材を
使用して、加熱圧着し、次いでペレットのＡＪ＠極と＠
記す−ドフし／−ムのＡｕめっき又はＡｇめりきされた
インナーリード該タブ近傍部とをφ２０〜５０μｍのＡ
ｌｌ線によって３００〜４００℃の載置でテールレス熱
圧着ボールボンディングしている。つまシベレット側で
は、Ｍ−Ａｕ接合が形成され、インナーリードｔ１すは
Ａ、　−Ａｕ又はＡｕ　−Ｎｉ接合が形成される。これ
らのＡｊ！！　−Ａｕ接合やＡｌｌ　−Ａｕ接合は、純
金属同志の接合と比べ硬くてもろい。そして電気抵抗の
大きい金属間化合物を形成する為、従来から、ルーズコ
ンタクトの原因とされて来た。To make a resin-sealed semiconductor device, a lead frame is used, which is formed by integrally forming multiple leads, and the lead frame is plated with gold (hereinafter referred to as Au) or silver (hereinafter referred to as AJ).
1 ton of plated semiconductor elements (hereinafter referred to as pellets)
M (hereinafter referred to as the tab part) is heat-pressed as it is or using a suitable brazing material, and then the AJ@ pole of the pellet and @
Inner lead plated with Au or Ag plated with a diameter of 20 to 50 μm.
Tailless thermocompression ball bonding is carried out by placing the wire at 300 to 400°C. On the toe side, an M-Au junction is formed, and an A, -Au or Au-Ni junction is formed on the inner lead t1. These Aj! ! -Au bonding and All-Au bonding are harder and more brittle than bonding between pure metals. Since it forms an intermetallic compound with high electrical resistance, it has traditionally been thought to be the cause of loose contacts.

さらに、従来の樹脂封止型の半導体装置の欠点は、生首
自動化によりスピード向上を計υ生座コストを下げたに
もかかわらすＡｕ　＋Ａｌｌを多謝に使用している為、
材料費は依然として、高いままとなっていることである
。Furthermore, the disadvantage of conventional resin-encapsulated semiconductor devices is that they use a large amount of Au + All, even though they have improved speed and lowered production costs through automation.
Material costs remain high.

本発明の目的は、このような従来の樹脂封止型の半導体
装置の欠点を除いた半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device that eliminates the drawbacks of such conventional resin-sealed semiconductor devices.

本発明の特徴は、リードフレームを用いた半導体装置に
おいて、このリードフレームのタブ部に近接するインナ
ーリードのペレットが載置される側の表面の先端領域の
みにアルミニウム層が設けられ、ペレットのＡＪ’を極
と該イン１−リードの先端領域とがアルミニウム合金線
によって接続されている半導体装置にある。そして、タ
ブ部１Ｆ−適当なろう材を１更用して、ペレットが固定
されでいて、紛径がφ２０へ５０μｍの人！合金−によ
って、０．５〜１０μｎ１の厚さで１層が櫃けられたイ
ンナーリードの先端領域（先端から０．３〜１．’Ｏｍ
ｉ＋以内）とペレットのＡｊ！　１を極とが接続され、
樹脂によって封とされていること枠；好ましい。　。A feature of the present invention is that in a semiconductor device using a lead frame, an aluminum layer is provided only in the tip region of the surface of the inner lead near the tab portion of the lead frame on the side where the pellet is placed, and ' is a semiconductor device in which the pole and the tip region of the in1-lead are connected by an aluminum alloy wire. Then, in the tab part 1F, use a suitable brazing filler metal once to fix the pellets, and the diameter of the pellets is 50 μm from φ20! The tip region of the inner lead is coated with one layer with a thickness of 0.5 to 10 μm depending on the alloy (0.3 to 1.0 μm from the tip).
i+) and pellet Aj! 1 is connected to the pole,
Preferably, the frame is sealed with resin. .

本発明ｒｃ工れは、Ａｕ　＋ＡＩの代シ＆ＣＡＪを用い
ることにより従来ｂ）製造工程をｉｔとんど変艇するこ
となく、安価な、・且つ電気的特性の優れた樹脂封止半
導体装置を供給することができるのである。The RC construction of the present invention uses Si&CAJ instead of Au + AI to produce a resin-sealed semiconductor device that is inexpensive and has excellent electrical characteristics without changing the manufacturing process. It is possible to supply it.

以下、図面を用しｉて本発明の一実施例を詳細に説明す
る。Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

第１図は樹脂封止面の半導体装置の断面図である。タブ
部「やインナーリードの該タブ近傍部２９は、従来Ａｕ
めっきやＡＩＩめっきであったが、これをｌめっきとし
、しかもインナーリードのタブ近傍部２ａのみとするこ
とでも、ダイボンディング及びワイヤーボンデインてを
可能にさせた。FIG. 1 is a sectional view of a semiconductor device with a resin-sealed surface. The tab portion and the tab vicinity portion 29 of the inner lead are conventionally made of Au.
Although plating or AII plating was used, die bonding and wire bonding were made possible by changing this to l plating and only forming the inner lead near the tab portion 2a.

つまシダイボンディングにはＡ、箔を使用せスＫＡＩペ
ースト及び半田等のろう材４でペレット３を安定Ｋ１．
ｉｉＩ定・ｔ４．さらにペレット３．のＡ１１ｉＬ極５
とインナーリードの人＃／！７との３妾を受には、Ｍ＃
ン使用して、ペレット側、インナーリード側ともに、Ａ
Ｊ−Ａｌの接合とした。該ｋｌ　Ａｕ接合やＡ１１−Ａ
ｕ接合に比べ、金摘間化合物を形成、しないので耐蝕性
や電気的！＋！ｆ性が改善される。さらに１リードフレ
ームのＡ１層は、材料費低減の為、最小範囲、すなわち
゛、インナーリードのタブ近傍部２ａのみに付けること
がｊｉ袈である。この技術は、現在実施しているリード
フレーム５の部分Ａｕ又は部分Ａ、９めりきの製造技術
をもってすれば容易なことである。Use A, foil for Tsumashidai bonding. Stabilize the pellet 3 with a brazing material 4 such as KAI paste and solder K1.
iii fixed・t4. Furthermore, pellets 3. A11iL pole 5
And the inner lead person #/! To receive 3 concubines with 7, M#
Using A, both the pellet side and inner lead side
J-Al bonding was performed. The kl Au junction and A11-A
Compared to U-junctions, it does not form intermetallic compounds, so it is corrosion resistant and electrically resistant! +! f properties are improved. Furthermore, in order to reduce material costs, the A1 layer of one lead frame should be attached only to the minimum area, that is, only to the area near the tab 2a of the inner lead. This technique is easy if the manufacturing technology of the lead frame 5 of the Au part or the part A, 9 plated, which is currently in use is used.

以下実施例によプさらに詳ｍＫ、説明する。第２図は本
実施列のリードフレームの図である。す゛−ドフレーム
は、４２％Ｎ１Ｆｅｆ金板をエツチング又はプレス打抜
き加工に工９所定のパターンに杉成し、第２図斜線部Ｂ
以外の領域を０．５〜５０顛のシリコンゴム尋によ＃）
覆い、′電気めっきによシ斜線部８にＡｌ７ｉｌｖ付け
る。こうしてできたリードフレームに第１図の工うＫＡ
、９ペースト４を用いて２００〜３００℃に加熱しなが
ら、ペレット３をダイボンディングする。Further details will be explained below with reference to Examples. FIG. 2 is a diagram of the lead frame of this embodiment. The wood frame is made by etching or press punching a 42%N1Fef metal plate into a predetermined pattern.
Cover the other areas with 0.5 to 50 cm thick silicone rubber.
Cover and apply Al7ilv to the shaded area 8 by electroplating. The KA shown in Figure 1 is machined on the lead frame made in this way.
, 9 paste 4 is used to die-bond the pellets 3 while heating at 200 to 300°C.

次にワイヤーボンディングは、φ３０μｍの人Ｉ　Ｓｉ
合金９６を用い、従来のＡｕ　ＩＩＡボールボンディン
グと同様な、超音波併用型の熱圧着ポールボンディング
装置を用いて、　Ａｒ雰囲気で電気放電トーチによりＡ
４１球を形成し、やはり、２０Ｄ〜３００℃に加熱しな
がらボンディングを行なう。Next, wire bonding is performed using a φ30μm ISi
Using Alloy 96, A was applied using an electric discharge torch in an Ar atmosphere using an ultrasonic thermocompression pole bonding device similar to conventional Au IIA ball bonding.
41 balls are formed, and bonding is also performed while heating to 20D to 300°C.

該ポンディング以降は、従来と同様で樹脂＠正を行い、
外装めっき行なった後、半導体装ｌ１１ｔを、リードフ
レーム伜から個々に分離して製造を完了する。After this pounding, perform resin @ positive as before.
After the exterior plating is performed, the semiconductor devices 11t are individually separated from the lead frame 2 to complete the manufacturing process.

以上の材料構成、裏道方法によれば従来の工程を大きく
変更することなく、材料費を低減し、且つ電気的特性の
良い半導体装置を得ることができるのである。According to the above-described material structure and back-path method, it is possible to reduce material costs and obtain a semiconductor device with good electrical characteristics without significantly changing the conventional process.

向、本実施例では、４２％Ｎｉ−Ｆｅ合金板のリードフ
レームな用いたがさらに材料費を低減する目的でＣｕ合
金又は、Ｆｅ主体の合金でも同様の効果が得られること
は明らかである。In this example, a lead frame made of a 42% Ni--Fe alloy plate was used, but it is clear that similar effects can be obtained by using a Cu alloy or an alloy mainly composed of Fe in order to further reduce material costs.

また、リードフレームのインナーリードタブ近傍のＡ７
層は、ＡＪの電気めっきの代りに、マスキングテープを
用いてＡ！真空蒸着により句けＣも、同様の効果が得ら
れることも明らかである。Also, A7 near the inner lead tab of the lead frame.
The A! layer was made using masking tape instead of AJ electroplating. It is also clear that the same effect can be obtained with the vacuum deposition C.

【図面の簡単な説明】[Brief explanation of drawings]

笛り図は半導体装置の楊成材料を説明する上で用いた明
脂封［Ｅ前の＃導体装置の断面図、第２図は、本発明の
実施例に用いた、リードフレームの図、である。 尚、図にお−いて、１・・・・・・タブ、２・・・・・
・インナーリード、２ａ・・・・・・インナーリードの
該タブ近傍部、３・・・・・・ベレット（Ｓｉ−１−ツ
ブ）、４・・・・・・Ａ、９ペースト、訃・・・・・ペ
レットの１’電極、６・・・・・・Ａｌ緑、７．８・・
・・・・Ａｌめっき層、９・・・・・・アウターリード
、である。The flute diagram is a cross-sectional view of the # conductor device before the plastic seal used to explain the Yang Chen material of the semiconductor device, and Figure 2 is a diagram of the lead frame used in the embodiment of the present invention. It is. In the figure, 1... tab, 2...
- Inner lead, 2a... Near the tab of the inner lead, 3... Bellet (Si-1-tube), 4... A, 9 paste, end... ...Pellet 1' electrode, 6...Al green, 7.8...
. . . Al plating layer, 9 . . . Outer lead.

Claims (1)

【特許請求の範囲】[Claims] 半導体素子を＠置したタブと、該タブに近接する複数の
インナーリードと、該半導体素子と該インナーリードと
！接続する金属細線と、該各インナーリードに連続して
外へ延びるアウターリードとを有する樹脂封と型の半導
体装置において、該各インナーリードの半導体素子が載
置される側の表面の先端領域にのみにアルミニウム層が
設けられ、前記半導体素子と前記インナーリード先端領
域とがアルミニウム合金線によって接続されていること
を特徴とする半導体装置。A tab on which a semiconductor element is placed, a plurality of inner leads close to the tab, and the semiconductor element and the inner leads! In a resin-sealed semiconductor device having thin metal wires to be connected and outer leads extending outward continuously from each inner lead, a tip region of the surface of each inner lead on the side on which the semiconductor element is mounted is provided. 1. A semiconductor device, wherein an aluminum layer is provided only on the semiconductor element, and the semiconductor element and the inner lead tip region are connected by an aluminum alloy wire.
JP58150773A 1983-08-18 1983-08-18 Semiconductor device Pending JPS6042853A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58150773A JPS6042853A (en) 1983-08-18 1983-08-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58150773A JPS6042853A (en) 1983-08-18 1983-08-18 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6042853A true JPS6042853A (en) 1985-03-07

Family

ID=15504102

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58150773A Pending JPS6042853A (en) 1983-08-18 1983-08-18 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6042853A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103035535A (en) * 2012-12-26 2013-04-10 常州银河世纪微电子有限公司 Preparation method for large current / high-voltage diode

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103035535A (en) * 2012-12-26 2013-04-10 常州银河世纪微电子有限公司 Preparation method for large current / high-voltage diode

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