JPS6062141A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6062141A JPS6062141A JP58169194A JP16919483A JPS6062141A JP S6062141 A JPS6062141 A JP S6062141A JP 58169194 A JP58169194 A JP 58169194A JP 16919483 A JP16919483 A JP 16919483A JP S6062141 A JPS6062141 A JP S6062141A
- Authority
- JP
- Japan
- Prior art keywords
- intermediate plate
- thermal expansion
- substrate
- plate
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、半導体装置に係シ、特に信頼性が高（、≠為
つ車這仕千ツブーｒｈ益ル→−人軌のＭｙ勅Ｊ）傳杓た
パワー半導体装置に関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a semiconductor device, which has particularly high reliability. Regarding the developed power semiconductor device.
パワー半導体装置においては、一般に金属など熱伝導性
の優れた基板上に半導体チップを軟ろう材等で接着し、
半導体テップで発生する熱を基板に放散している。In power semiconductor devices, semiconductor chips are generally bonded onto a substrate with excellent thermal conductivity, such as metal, using a soft brazing material, etc.
The heat generated by the semiconductor chip is dissipated to the substrate.
このような基板には、舟に熱伝導の良い銅、アルミニウ
ム、鉄などの金属が使われる。Such substrates are made of metals such as copper, aluminum, and iron, which have good thermal conductivity.
半導体チップが小さい場合には、これらの基板に直接、
半導体チップを軟ろう材等で接着しても使用可能な耐熱
サイクル性を持った装置が得られるが、半導体チップが
大きな゛場合には、基板と半導体チップとの熱膨張率の
差にょシ、半導体チップに大きな歪がかかシ、半導体チ
ップが破壊するか、軟ろう材に熱サイクルにょシ＜９返
し歪ががかシ、接着層に亀裂が生じ、そのたｂ半導体チ
ップから基板までの熱抵抗が増大し使用中に半導体装置
が、破壊するという問題がある。If the semiconductor chip is small, it can be directly attached to these substrates.
Even if the semiconductor chip is bonded with a soft brazing material, etc., a device with usable heat cycle resistance can be obtained, but if the semiconductor chip is large, the difference in thermal expansion coefficient between the substrate and the semiconductor chip may cause If a large strain is applied to the semiconductor chip, the semiconductor chip will be destroyed, or if the soft filler material is subjected to thermal cycle <9, the adhesive layer will crack, and the bond between the semiconductor chip and the substrate will be damaged. There is a problem in that the thermal resistance increases and the semiconductor device is destroyed during use.
故に、大きな半導体チップを用いる装置では基板と半導
体チップの間に中間Ｎ亭＆らは、？−ｈ瓜を軟ろう材等
で接着しこれによって、半導体チップに加わる歪や、接
層層に加わる歪を低減し上記問題の解決を計っている。Therefore, in a device using a large semiconductor chip, there is an intermediate space between the substrate and the semiconductor chip. The above problem is solved by bonding the -h melon with a soft brazing material or the like, thereby reducing the strain applied to the semiconductor chip and the strain applied to the contact layer.
この中間板には、熱膨張係数が半導体チップと基板の熱
膨張係数の中間の値を示し、しかも熱伝導率の＾いもの
が必要で、一般には、タングステン、モリブデン板が使
用されている。This intermediate plate must have a coefficient of thermal expansion between those of the semiconductor chip and the substrate, and must also have high thermal conductivity, and tungsten or molybdenum plates are generally used.
しかし、タングステン、モリブデンは、稀少金属で、し
かも加工が困難である。However, tungsten and molybdenum are rare metals and are difficult to process.
熱膨張係数が半導体チップに近い合金、たとえハ鉄、ニ
ッケル合金、鉄、ニッケル、コバルト合金などを中間板
に用いる試みもち）が、これは熱伝導が悪く、適してい
るとはいえない。Attempts have been made to use alloys with thermal expansion coefficients close to those of semiconductor chips, such as iron, nickel alloys, iron, nickel, and cobalt alloys, for the intermediate plate, but these have poor thermal conductivity and are not suitable.
これらの問題を解決するため、熱１尽導率の高い金属で
ある銅などと、熱膨張率の低い鉄、ニッケル合金や鉄、
ニッケル、コバルト合金などの合金を複合化したいわゆ
るクラツド板の適用が’Ｉ’！Ｊ公昭４２−２１９６９
号、特公昭５１−２７９８３、実公昭４４−２４４２８
号公報に示されている。To solve these problems, we developed metals such as copper that have a high thermal conductivity, and iron, nickel alloys, and iron that have a low coefficient of thermal expansion.
Application of so-called clad plates made of composite alloys such as nickel and cobalt alloys is 'I'! J Kosho 42-21969
No., Special Publication No. 51-27983, Utility Publication No. 44-24428
It is shown in the publication No.
しかし、このようなりラッド板を中間板とじて用いる場
合、銅と鉄合金との厚さ比によってクラツド板の見掛け
の膨張係数が定まυ、シリコンの膨張係数に近い膨張係
数にするためには、鉄合金を一定比以上にしなければな
らない。However, when using such a rad plate as an intermediate plate, the apparent coefficient of expansion of the clad plate is determined by the thickness ratio of copper and iron alloy. , the proportion of iron alloy must be above a certain level.
又、熱膨張係数の大きな基板の影響を半導体チップに与
えないようにするには、中間板が厚くなければならず、
それによって、介在する鉄合金層が厚くなシ、シかも鉄
合金の熱伝導率が低いため、半導体チップと基板間の熱
抵抗が大きくなるという問題があった。Also, in order to prevent the semiconductor chip from being affected by the substrate with a large coefficient of thermal expansion, the intermediate plate must be thick.
As a result, since the intervening iron alloy layer is thick and the thermal conductivity of the iron alloy is low, there is a problem that the thermal resistance between the semiconductor chip and the substrate increases.
本発明は、クラツド板を半導体装置の中間板として用い
るに際し、その中間板の形状を定めることによシ放熱・
性が優れ、しかも信頼性の高い半導体装置を提供するに
ある。When using a clad plate as an intermediate plate of a semiconductor device, the present invention improves heat dissipation by determining the shape of the intermediate plate.
To provide a semiconductor device with excellent performance and high reliability.
本発明の特徴とするところは、クラツド板で形成したキ
ャップ状の中間板を用い半導体チップをその内底部に搭
載することにある。この中間板は、信頼性を損すること
なく、クラツド板の膜厚を薄くでき、それによシ熱抵抗
を小さくでき、信頼性の高い半導体装置を得ることがで
きる。A feature of the present invention is that a semiconductor chip is mounted on the inner bottom of a cap-shaped intermediate plate formed of a clad plate. This intermediate plate allows the film thickness of the cladding plate to be made thinner without impairing reliability, thereby making it possible to reduce the thermal resistance, thereby making it possible to obtain a highly reliable semiconductor device.
〔発明の実施例〕−
まず、本発明に至った実験を含め本発明の実施例につい
て説明する。[Embodiments of the Invention] First, embodiments of the present invention, including experiments that led to the present invention, will be described.
第１図は、従来のパワートランジスタを示し、基板１に
は大型Ｔ Ｏ，３の平形ステムを用い、中間板２には銅
−インバー合金−銅のクラツド板を用いシリコントラン
ジスタチップ３と中間板２と、基板１は鉛９５チスズ５
％の半田４で接着されている。その後、絶縁板５を介し
て基板１に半田接着された外部端子６と、トランジスタ
チップ３はボンディングワイヤとしてのアルミワイヤ７
で接続され、キャップ８でもって、全体をシールされる
。Figure 1 shows a conventional power transistor, in which a large flat stem of TO,3 is used as the substrate 1, a copper-invar alloy-copper clad plate is used as the intermediate plate 2, and a silicon transistor chip 3 and the intermediate plate are used. 2, and the substrate 1 is made of 95 lead and 5 tin.
It is bonded with 4% solder. Thereafter, the external terminals 6 solder-bonded to the substrate 1 via the insulating plate 5 and the aluminum wires 7 as bonding wires are connected to the transistor chips 3.
and the whole is sealed with a cap 8.
実験に際しては半田４の厚さは、全て０．１ ａｍとな
し、中間板２の形状を種々に変えたキャップ８のない構
造のものについて、トランジスタチップ３から基板１の
底面までの熱抵抗を測定した。In the experiments, the thickness of the solder 4 was set to 0.1 am in all cases, and the thermal resistance from the transistor chip 3 to the bottom surface of the substrate 1 was calculated for structures without a cap 8 with various shapes of the intermediate plate 2. It was measured.
又、この装置を一５５Ｃ（２５分間）→常温（５分間）
→１５（１（２５分間）→常温（５分間）を−サイクル
とする熱サイクル試験に掛け、先きに述べた熱抵抗が１
．５倍になるまでのサイクル数をもって信頼性の評価と
した。Also, heat this device to -55C (25 minutes) → room temperature (5 minutes)
→ 15 (1 (25 minutes) → normal temperature (5 minutes) - cycle) The thermal resistance mentioned earlier was 1.
．． Reliability was evaluated based on the number of cycles required to increase five times.
トランジスタチップは８×８閣で厚さ０．３ ｔａｒの
ものでおる。The transistor chip is 8×8 and 0.3 tar thick.
第１表は中間板に銅、インノく一合金（妖６４％、ニッ
ケルａ ６＊ ） 、銅のクラツド板で、その厚さ構成
は１：４：１のものであり、板の横方向の熱膨張係数は
６．２ Ｘ １０”’／ｍｌ：のものを用い、ノ杉状は
直径１３咽の円形で、その厚さを衣向己すように変えた
ものを用いて、装置を製作し、その特性を測定した結果
を示す。Table 1 shows a clad plate with an intermediate plate of copper, Inno-Kuichi alloy (nickel 64%, nickel a 6*), and copper, and the thickness composition is 1:4:1. The device was fabricated using a material with a thermal expansion coefficient of 6.2 x 10''/ml, a circular shape with a diameter of 13 mm, and a thickness that was changed so as to be similar to the clothes. The results of measuring its characteristics are shown below.
第 １ 表
第２表は、本発明にかかわる中間板を用いた装置の結果
を示す。第２図に示すようなキャップ状２の中間板２を
用いたもので、その側面の高さは５圏であシ、底部は第
１表の装置と同じく、直径１３ｍの円形である。なお、
このキャ°ッグ状中間板は、プレス加工にして作成した
。また、キャップ８は外されている。Tables 1 and 2 show the results of devices using the intermediate plate according to the invention. It uses a cap-shaped intermediate plate 2 as shown in Fig. 2, the height of the side surface is 5 circles, and the bottom part is circular with a diameter of 13 m like the device shown in Table 1. In addition,
This cage-shaped intermediate plate was produced by press working. Further, the cap 8 has been removed.
第２表
第２表と第１表の結果を対比すると本発明の中間板を用
いることによる効果が判る。Comparing the results in Table 2 and Table 1 shows the effect of using the intermediate plate of the present invention.
なお、中間板が薄くなると耐熱サイクル性が低下するの
は、基板１が銅であシ、その熱膨張係数が１６．５ ｘ
１０−６／Ｃと大きく、熱膨張が半田層４を介して、
中間板２に作用し、中間板２の見掛けの熱膨張係数が犬
きくなｐ、中間板２とトランジスタチップ３との間の半
田層４に熱歪が掛るからでおる。Note that the heat cycle resistance decreases when the intermediate plate becomes thinner because the substrate 1 is made of copper and its thermal expansion coefficient is 16.5 x
The thermal expansion is as large as 10-6/C through the solder layer 4,
This is because the apparent coefficient of thermal expansion of the intermediate plate 2 increases, and thermal strain is applied to the solder layer 4 between the intermediate plate 2 and the transistor chip 3.
本発明の中間板では、側面の構造物が、底部の受ける基
板１の熱膨張の影響を防けるように作用し、中間板とト
ランジスタチップとの間の半田層に掛る熱歪が、クラツ
ド板本来の熱膨張係数によって生じるそれに近い値まで
に低減されているためと考えられる。。In the intermediate plate of the present invention, the side structure acts to prevent the effects of thermal expansion of the substrate 1 on the bottom, and the thermal strain applied to the solder layer between the intermediate plate and the transistor chip is reduced to the cladding plate. This is thought to be because the coefficient of thermal expansion has been reduced to a value close to that produced by the original coefficient of thermal expansion. .
さらに、この実験によって、中間板２の厚さが、１．５
圏位よシ薄い場合に本発明の効果だ著しく表われている
こともわかる。Furthermore, as a result of this experiment, the thickness of the intermediate plate 2 was determined to be 1.5
It can also be seen that the effect of the present invention is clearly visible when the cylindrical position is thinner than the cylindrical position.
又、この実験によって、本発明の中間板を適用した場合
、熱抵抗も低い値が得られている。これは、トランジス
タチップ３で発生した熱がクラツド板のトランジスタチ
ップ３ｉｌｌｌｌＬ７）熱伝導の良い組によつ広げられ
、広い面積にわたって、比較的熱伝導率の悪い鉄合金を
熱が流れるため、トランジスタチップ３から基板１間の
熱抵抗が小さくなるものと思われる。Furthermore, this experiment showed that when the intermediate plate of the present invention was applied, a low value of thermal resistance was obtained. This is because the heat generated in the transistor chip 3 is spread through the cladding plate of the transistor chip 3illllL7), and the heat flows through the iron alloy, which has relatively poor thermal conductivity, over a wide area. 3, it is thought that the thermal resistance between the substrates 1 becomes smaller.
第２表のものと同様な試作装置で、中間板２の厚さＩＷ
ｒ！ｎで、側面の高さを種々変えてみたが、側面の高さ
は、僅かであっても、その効果が十分に見られた。この
ことは、半導体チップの上面のワイヤボンデング等に際
して、本発明の中間板が支障を与えることなく、効果的
に使用できることを意味している。With a prototype device similar to that in Table 2, the thickness of the intermediate plate 2 is IW.
r! We tried varying the height of the side surfaces with n, but even if the height of the side surfaces was small, the effect was sufficiently seen. This means that the intermediate plate of the present invention can be effectively used without causing any trouble during wire bonding or the like on the upper surface of a semiconductor chip.
第３図に本発明の他の実施例として、複数個のパワー半
導体チップを搭載した半導体パワーモジュールに本発明
を適用した場合を示す。FIG. 3 shows another embodiment of the present invention in which the present invention is applied to a semiconductor power module equipped with a plurality of power semiconductor chips.
放熱板９の上にアルミナセジミックス絶縁板１０を介し
て、電極用銅板１１が半田層４で接着されており、その
上にキャップ状の銅・インバー合金・銅・クラツド板よ
シなる中間板２を半田層４で接着し、その上にパワート
ランジスタチップ３を同じく半田層４で接着し、トラン
ジスタチップからはベース、エミッタからの配線をアル
ミワイヤ７で、外部端子６に接続し、樹脂ケース１２体
パワーモジュールを得り。A copper plate 11 for electrodes is bonded to the heat dissipation plate 9 via an alumina sedimix insulating plate 10 with a solder layer 4, and a cap-shaped intermediate plate such as a copper/invar alloy/copper/clad plate is placed on top of the copper plate 11 for electrodes. 2 is bonded with a solder layer 4, and a power transistor chip 3 is bonded on top of it with the same solder layer 4. Wiring from the transistor chip to the base and emitter is connected to the external terminal 6 with an aluminum wire 7, and then the resin case is attached. Obtained 12 power modules.
この半導体パワーモジュールは、本発明に係かる中間板
２を使用しているため、耐熱サイクル性カ高く、パワー
トランジスタチップ３と放熱板９との間の熱抵抗が小さ
く、シかも、パワーモジュール全体として小型にできる
利点もある。Since this semiconductor power module uses the intermediate plate 2 according to the present invention, the heat cycle resistance is high, the thermal resistance between the power transistor chip 3 and the heat sink 9 is small, and the power module as a whole It also has the advantage of being able to be made smaller.
本発明の説明は、半導体チップとしては、パワートラン
ジスタについて述べたが、これはテイリスタ、ダイオー
ドなどのパワー半導体装置に適用でき、またそれぞれの
複合したパワー半導体装置に適用できる。In the description of the present invention, a power transistor has been described as a semiconductor chip, but this invention can be applied to power semiconductor devices such as a Tailristor and a diode, and can also be applied to a composite power semiconductor device.
又、中間板については、銅・鉄ニツケル合金・銅のクラ
ツド板について述べたが、その構成金属を制限するもの
でない。しかし、本発明の効果のみられるものは、中間
板の熱膨張係数が、半導体チップのそれと、基板となる
金属の熱膨張係数との間にあることが必要である。Regarding the intermediate plate, although a copper/iron-nickel alloy/copper clad plate has been described, the constituent metals thereof are not limited. However, for the present invention to be effective, the thermal expansion coefficient of the intermediate plate must be between that of the semiconductor chip and that of the metal serving as the substrate.
又、熱抵抗低減に効果のみられるのは、熱伝導の良い金
属が両面にあｐｌその中間に熱膨張係数□！ヤ−人＋＋
、一覧−−１も為１−−（−中間板の平面形状は円形矩
形等、各種の形のものが利用できる。Also, what is effective in reducing thermal resistance is that metal with good thermal conductivity is placed on both sides, and the coefficient of thermal expansion is □ in the middle! Ya-jin++
, List - 1 and 1 - (-The planar shape of the intermediate plate can be of various shapes such as circular and rectangular.
又、本発明に記載したクラツド板は、プレス加工によシ
容易に本発明の中間板の形状のもの作成することができ
る。Further, the clad plate described in the present invention can be easily produced in the shape of the intermediate plate of the present invention by press working.
本発明によれば、以上に述べるように、信頼性が高くか
つ半導体チップで発生する熱の放散の優れた半導体装置
を得ることができる。According to the present invention, as described above, it is possible to obtain a semiconductor device that is highly reliable and has excellent dissipation of heat generated in a semiconductor chip.
第１図は従来の半導体装置を示す断面図、第２図、第３
図は本発明の異なる実施例になる半導体装置を示す断面
図である。
１・・・基板、２・・・中間板、３・・・トランジスタ
チップ、４・・・半田層、５・・・絶縁板、６・・・外
部端子、７・・・アルミワイヤ、８・・・キャップ、９
・・・放熱板、ｌｏ・・・アルミナセラミックス絶縁板
、１１．、・電極用銅板、１２・・・樹脂ケース、１３
・・・モールド樹脂。
代理人 弁理士 高橋明夫
第１区
′ｈ′２− 図 。
第３国
二Figure 1 is a sectional view showing a conventional semiconductor device, Figures 2 and 3.
The figure is a sectional view showing a semiconductor device according to a different embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Intermediate board, 3... Transistor chip, 4... Solder layer, 5... Insulating plate, 6... External terminal, 7... Aluminum wire, 8...・Cap, 9
... Heat sink, lo... Alumina ceramics insulating board, 11. ,・Copper plate for electrode, 12...Resin case, 13
...Mold resin. Agent Patent Attorney Akio Takahashi 1st Ward 'h'2- Figure. 3rd country 2
Claims (1)
係数を有する中間板を介してろう月によシ接着し、基板
と反対側の表面から外部端子に導伝した半導体装置にお
いて、中間板は熱膨張係数が小さい金属の両側に熱伝導
性の良い金属をクラッドしたキャップ状の金属からなる
ことを特徴とする半導体装置。 ２、上記帛１項において、基板と中間板の間に基板側に
セラミック絶縁板、中間板側に電極用金属板があシ、相
互間はろう材で接着されていることを特徴とする半導体
装置。 ３、上記第１項において、中間板は１．５ ｔｗｎ以下
の厚さであることを特徴とする半導体装置。[Claims] 1. A semiconductor chip is bonded to a metal substrate through an intermediate plate having a coefficient of thermal expansion between the two, and conduction is conducted from the surface opposite to the substrate to external terminals. 1. A semiconductor device characterized in that the intermediate plate is made of a cap-shaped metal having a metal having a small coefficient of thermal expansion and cladding with a metal having good thermal conductivity on both sides. 2. The semiconductor device according to the above item 1, characterized in that between the substrate and the intermediate plate, there is a ceramic insulating plate on the substrate side, a metal plate for electrodes on the intermediate plate side, and they are bonded together with a brazing material. 3. The semiconductor device according to item 1 above, wherein the intermediate plate has a thickness of 1.5 twn or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58169194A JPS6062141A (en) | 1983-09-16 | 1983-09-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58169194A JPS6062141A (en) | 1983-09-16 | 1983-09-16 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6062141A true JPS6062141A (en) | 1985-04-10 |
Family
ID=15881959
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58169194A Pending JPS6062141A (en) | 1983-09-16 | 1983-09-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6062141A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0350593A2 (en) * | 1988-07-13 | 1990-01-17 | International Business Machines Corporation | Electronic package with heat spreader member |
-
1983
- 1983-09-16 JP JP58169194A patent/JPS6062141A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0350593A2 (en) * | 1988-07-13 | 1990-01-17 | International Business Machines Corporation | Electronic package with heat spreader member |
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