JPS60620U - electronic load device - Google Patents
electronic load deviceInfo
- Publication number
- JPS60620U JPS60620U JP9236783U JP9236783U JPS60620U JP S60620 U JPS60620 U JP S60620U JP 9236783 U JP9236783 U JP 9236783U JP 9236783 U JP9236783 U JP 9236783U JP S60620 U JPS60620 U JP S60620U
- Authority
- JP
- Japan
- Prior art keywords
- load
- inverting input
- nth
- emitter
- load transistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Testing Electric Properties And Detecting Electric Faults (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図、第2図は従来の各別の電子負荷装置の一例を示
すブロック図、第3図は本考案の一実施例を示すブロッ
ク図である。
Ein・・・・・・電源、Trl、 Tr2. Trn
・・・・・・負荷トランジスタ、DFl、 DF2.
DFn・・・・・・差動増幅器、Re・・・・・・エミ
ッタ抵抗器、Rs・・・・・・電流検出抵抗器、P、N
・・・・・・試験端子、VC・・・・・・制御電圧。FIGS. 1 and 2 are block diagrams showing examples of different conventional electronic loads, and FIG. 3 is a block diagram showing an embodiment of the present invention. Ein...Power supply, Trl, Tr2. Trn
...Load transistor, DF1, DF2.
DFn...Differential amplifier, Re...Emitter resistor, Rs...Current detection resistor, P, N
...Test terminal, VC...Control voltage.
Claims (1)
コレクタ・エミッタを並列に接続しかつ電流検出抵抗器
を直列に介して接続したn個の負荷トランジスタと、各
負荷トランジスタのエミッタに介挿したエミッタ抵抗器
と、第2乃至第nの各負荷トランジスタの各エミッタ抵
抗器の端子間電圧をそれぞれ反転入力へ与えられ非反転
入力を第1の負荷トランジスタのエミッタに共通接続と
し出力を第2乃至第nの負荷トランジスタのベースへ与
えて第2乃至第nの負荷トランジスタのコレクタ電流を
第1の負荷トランジスタのコレクタ電流に等しくするよ
うに制御する第2乃至第nの差動増幅器と、上記電流検
出抵抗の端子間電圧および外部から与えられる制御電圧
を反転入力および非反転入力へ与えられ出力を第1の負
荷トランジスタの他方のベースへ与えて上記電流検出抵
抗を流れる電流を上記制御電圧に応じて制御する第1の
差動増幅器とを具備することを特徴とする電子負荷装置
。A test terminal to which an external power supply is connected, n load transistors whose collectors and emitters are connected in parallel between these test terminals, and a current detection resistor connected in series, and the emitter of each load transistor is connected to the test terminal. The voltage between the terminals of the emitter resistor inserted and the emitter resistor of each of the second to nth load transistors is applied to the inverting input, and the non-inverting input is commonly connected to the emitter of the first load transistor, and the output is the second to nth differential amplifiers that are applied to the bases of the second to nth load transistors to control the collector currents of the second to nth load transistors to be equal to the collector currents of the first load transistors; The voltage between the terminals of the current detection resistor and the control voltage applied externally are applied to the inverting input and the non-inverting input, and the output is applied to the other base of the first load transistor, so that the current flowing through the current detection resistor is reduced to the control voltage. An electronic load device comprising: a first differential amplifier that is controlled according to a first differential amplifier;
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9236783U JPS60620U (en) | 1983-06-16 | 1983-06-16 | electronic load device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9236783U JPS60620U (en) | 1983-06-16 | 1983-06-16 | electronic load device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60620U true JPS60620U (en) | 1985-01-07 |
JPH0441370Y2 JPH0441370Y2 (en) | 1992-09-29 |
Family
ID=30222536
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9236783U Granted JPS60620U (en) | 1983-06-16 | 1983-06-16 | electronic load device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60620U (en) |
-
1983
- 1983-06-16 JP JP9236783U patent/JPS60620U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPH0441370Y2 (en) | 1992-09-29 |
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