JPS6059889A - Secam system chrominance signal generating circuit - Google Patents

Secam system chrominance signal generating circuit

Info

Publication number
JPS6059889A
JPS6059889A JP16793383A JP16793383A JPS6059889A JP S6059889 A JPS6059889 A JP S6059889A JP 16793383 A JP16793383 A JP 16793383A JP 16793383 A JP16793383 A JP 16793383A JP S6059889 A JPS6059889 A JP S6059889A
Authority
JP
Japan
Prior art keywords
signal
phase
color
locked loop
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16793383A
Other languages
Japanese (ja)
Inventor
Izumi Koga
泉 古賀
Kyosuke Sasaki
恭介 佐々木
Osamu Mizuhara
水原 修
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Hokushin Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Hokushin Electric Corp filed Critical Yokogawa Hokushin Electric Corp
Priority to JP16793383A priority Critical patent/JPS6059889A/en
Publication of JPS6059889A publication Critical patent/JPS6059889A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N11/00Colour television systems
    • H04N11/06Transmission systems characterised by the manner in which the individual colour picture signal components are combined
    • H04N11/18Transmission systems characterised by the manner in which the individual colour picture signal components are combined using simultaneous and sequential signals, e.g. SECAM-system
    • H04N11/183Encoding means therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Processing Of Color Television Signals (AREA)

Abstract

PURPOSE:To obtain a stable signal of the SECAM system by providing a phase locked loop at each chrominance signal system and applying phase lock to one system by means of a chrominance subcarrier signal while the other signal transmits a chrominance signal. CONSTITUTION:A movable contact (c) of changeover switches SW4, SW5 is selected to the position of a contact (a) of a phase locked loop PLLR side, a switch SW3R is opened and a switch SW3B is closed at a time t1. Thus, a signal S3 frequency-modulated by a color difference signal R-Y relating to a chrominance subcarrier signal fR stored in an integration device IR is transmitted from a voltage/frequency converter V/FR at the phase locked loop PLLR side, and the phase of the phase locked loop PLLB is locked at a chrominance subcarrier signal fB. Next, a signal S4 is transmitted at a time t2, the phase of the phase locked loop PLLR is locked by the signal fR. Thus, an output signal S5 shown in (f) and (g) is transmitted repetitively to an output terminal TO.

Description

【発明の詳細な説明】 (発明の分野) 本発明は、SECAM方式色信号発生回路に関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention relates to a SECAM color signal generation circuit.

(従来技術) カラーテレビジョン方式の一種に、5ECA111方式
がある。この方式は、二つの色差信号(n−y)と(B
−Y) を1水平走査毎に交互(線順次)に送シ、受像
機側で1ラインの遅延線を用いて同時信号に変換するも
のである。すなわち、(R−Y)に比例する第1の色差
信号DR+= −1,9(ER’ −EY’ )で周波
数4.40625 MHの第1の色副搬送信号fRを周
波数変調すると共に(B −Y)に比例する第2の色差
信号DB’ = 1.5 (EB’ −EY’ )で周
波数4.25000 MH2の第2の色副搬送信号fB
を周波数変調し、これら周波数変調された色副搬送信号
を交互にベルフィルタと称される成形フィルタを介して
輝度信号に多重することが行われている。ここで、ER
′、EY′B、Iのダッシュ記号はガンマ補正されてい
ることを表わす。
(Prior Art) One type of color television system is the 5ECA111 system. This method uses two color difference signals (ny) and (B
-Y) are sent alternately (line sequentially) for each horizontal scan, and are converted into simultaneous signals using a one-line delay line on the receiver side. That is, the first color subcarrier signal fR with a frequency of 4.40625 MH is frequency-modulated with the first color difference signal DR+=-1,9 (ER'-EY') proportional to (RY), and (B -Y) and a second color subcarrier signal fB of frequency 4.25000 MH2 with a second color difference signal DB' = 1.5 (EB'-EY' )
These frequency-modulated color subcarrier signals are alternately multiplexed into a luminance signal via a shaping filter called a Bell filter. Here, ER
The dashes in ', EY'B, and I represent gamma correction.

第1図は、このようなSECAM 方式における周波数
変調回路の従来の一例を示す回路図であって、位相同期
ループとして構成された例を示している。
FIG. 1 is a circuit diagram showing an example of a conventional frequency modulation circuit in the SECAM system, and shows an example configured as a phase-locked loop.

第1図において、入力端子T工に1水平走査毎に交互に
加えられる二つの色差信号(R−Y)、 (B−Y)は
スイッチSW1を介して加算器ADDの一方の入力端子
aに加えられる。加算器ADDの他方の入力端子bニハ
、スイ、 チsW3.ローパスフィルタLpF及びサン
プルホールド回路SRを介して位相比較器pcの出力信
号が加えられる。加算器ADDの出力信号は電圧周波数
変換器V/Fに加えられる。電圧周波数変換器V/Fの
出力信号は出力端子TOに送出されると共に、位相比較
器pcの一方の入力端子aに加えられる。位相比較器p
cの他方の入力端子すには、切換スイッチSW2を介し
て第1の色副搬送信号f−は第2の色副搬送信号fBが
選択的に加えられる。
In Fig. 1, two color difference signals (R-Y) and (B-Y) which are applied alternately to the input terminal T every horizontal scan are sent to one input terminal a of the adder ADD via the switch SW1. Added. The other input terminal b of the adder ADD is sW3. The output signal of the phase comparator pc is applied via the low-pass filter LpF and the sample-and-hold circuit SR. The output signal of adder ADD is applied to voltage frequency converter V/F. The output signal of the voltage frequency converter V/F is sent to the output terminal TO and is also applied to one input terminal a of the phase comparator pc. phase comparator p
The first color sub-carrier signal f- and the second color sub-carrier signal fB are selectively applied to the other input terminal of the color sub-carrier signal f- through a changeover switch SW2.

第2図は、第1図の動作説明図であって、(a)はスイ
ッチSW の動作を表わし、(b)は入力端子Tiに加
えられる色差信号S1を表わし、(C)は切換スイッチ
SW2を介して位相比較器pcに加えられる色副搬送信
号S2を表わし、(d)はスイッチSW3の動作を表わ
している。時刻toにおいて、スイッチSW□は閉成さ
れて加算器ADDの一方の入力端子aには色差信号S□
として(R−Y)が加えられ、スイッチSW3は開離さ
れて加算器ADDの他方の入力端子bKは図示しない前
段階においてサンプルホールド回路SHに保持されてい
る第1の副搬送信号fRに関連した信号が加えられる。
FIG. 2 is an explanatory diagram of the operation of FIG. 1, in which (a) shows the operation of the switch SW, (b) shows the color difference signal S1 applied to the input terminal Ti, and (C) shows the changeover switch SW2. (d) represents the operation of switch SW3. At time to, the switch SW□ is closed, and one input terminal a of the adder ADD receives the color difference signal S□.
(RY) is added, the switch SW3 is opened, and the other input terminal bK of the adder ADD is connected to the first subcarrier signal fR held in the sample-and-hold circuit SH in the previous stage (not shown). signal is added.

この状態では、位相比較器PCは位相同期ループから切
り離され、電圧周波数変換器V/Fは色差信号(R−Y
)とサンプルホールド回路SHの保持信号との加算信号
に応じた周波数信号、すなわち、色差信号(R−Y)で
第1の色副搬送信号fRを周波数変調した色信号を送出
する。
In this state, the phase comparator PC is disconnected from the phase locked loop, and the voltage frequency converter V/F is connected to the color difference signal (R-Y
) and the held signal of the sample-and-hold circuit SH, that is, a color signal obtained by frequency-modulating the first color subcarrier signal fR with a color difference signal (RY).

水平帰線区間が始まる時刻t□において、スイッチSW
1は開離されてスイッチSW3は閉成され、切換スイッ
チSW2の可動接点Cは第2の色副搬送信号−1’側の
固定接点すに接続される。これにより、位B 相同期ループは第2の色副搬送信号fBで位相がロック
される。そして、水平帰線区間が終わる時刻し、におい
て、スイッチSW は閉成されて加算器1 ADDの一方の入力端子色には色差信号0として(L1
2 (n−y)が加えられ、スイッチSW、、は開離されて
加算器ADT)の他方の入力端子すにはサンプルホール
ド回路SHに保持されている第2の色副搬送信号箱に関
連した信号が加えられる。これにより、電圧周波数変換
器V/Fは色差信号(B −Y)とサンプルホールド回
路SHの保持信号との加算信号に応じた周波数信号、す
なわち、色差信号(B −Y)で第2の色副搬送信号f
Bを周波数変調した色信号を送出する。次の水平帰線区
間が始まる時刻t3において、スイッチSW1は開離さ
れてスイッチSW3は閉成され、切換スイッチSW2の
可動接点Cは第1の色副搬送信号fR側の固定接点aに
接続される。これK・より、位相同期ループは第1の色
副搬送信号fRで位相がロックされる。そして、水平帰
線区間が終わる時刻t4において、スイッチSW□は閉
成されてスイッチSW は開離され、以下、時刻t。以
降と同様な一連の動作を繰り返すことになる。
At time t□ when the horizontal flyback section begins, switch SW
1 is opened and the switch SW3 is closed, and the movable contact C of the changeover switch SW2 is connected to the fixed contact C on the side of the second color subcarrier signal -1'. As a result, the phase of the phase B phase-locked loop is locked to the second color subcarrier signal fB. Then, at the time when the horizontal blanking interval ends, the switch SW is closed and the color difference signal 0 is sent to one input terminal color of the adder 1 ADD (L1
2 (n-y) is applied, switches SW, , are opened and the other input terminal of the adder (ADT) is connected to the second color subcarrier signal box held in the sample-and-hold circuit SH. signal is added. As a result, the voltage frequency converter V/F converts the second color into a frequency signal corresponding to the addition signal of the color difference signal (B - Y) and the holding signal of the sample hold circuit SH, that is, the color difference signal (B - Y). subcarrier signal f
A color signal obtained by frequency modulating B is sent out. At time t3 when the next horizontal retrace interval begins, switch SW1 is opened and switch SW3 is closed, and movable contact C of changeover switch SW2 is connected to fixed contact a on the side of first color subcarrier signal fR. Ru. Due to this K., the phase of the phase-locked loop is locked to the first color subcarrier signal fR. Then, at time t4 when the horizontal flyback section ends, switch SW□ is closed and switch SW is opened, and henceforth, time t. The same series of operations will be repeated from then on.

しかし、このような従来の構成によれば、色信号送出開
始時の位相を所定の位相に揃えるために約101Jsの
水平帰線区間内に第1の色副搬送信号fB又はM2の色
副搬送信号fRで位相同期ループの位相をロックしなけ
ればならず、セトリングの速い位相同期ループを構成す
る必要がある。このためには、位相同期ループを構成す
るローパスフィルタLPFの構成が複雑になるという欠
点がある。また、色信号送出開始時の位相安定度を高め
るために、水平帰線区間中に一旦電圧周波数変換器V/
Fの動作を停止させて再開させなければならず、電圧周
波数変換器V/Fの構成も複雑になるという欠点がある
However, according to such a conventional configuration, in order to align the phase at the start of color signal transmission to a predetermined phase, the color subcarrier of the first color subcarrier signal fB or M2 is transmitted within a horizontal retrace interval of approximately 101 Js. It is necessary to lock the phase of the phase-locked loop with the signal fR, and it is necessary to configure a phase-locked loop with fast settling. This has the disadvantage that the configuration of the low-pass filter LPF constituting the phase-locked loop becomes complicated. In addition, in order to increase the phase stability at the start of color signal transmission, the voltage frequency converter V/
This has the disadvantage that the operation of V/F must be stopped and restarted, and the configuration of the voltage frequency converter V/F becomes complicated.

(発明の目的) 本発明は、このような点に着目してなされたものであっ
て、その目的は、比較的簡単な構成で安定したSECA
M方式の色信号が得られる信号発生回路を提供すること
にある。
(Objective of the Invention) The present invention has been made with attention to these points, and its object is to provide a stable SECA with a relatively simple configuration.
An object of the present invention is to provide a signal generation circuit that can obtain an M-type color signal.

(発明の概要) このような目的を達成する本発明は生色信号系統毎に位
相同期ループを設け、一方の位相同期ループが色信号を
送出す高状態では他方の位相同期ループをそのループに
割り当てられている色副搬□ 送信号で位相ロックするようにしたことを特徴とする。
(Summary of the Invention) The present invention achieves the above object by providing a phase-locked loop for each raw color signal system, and in a high state in which one phase-locked loop sends out a color signal, the other phase-locked loop is connected to that loop. The assigned color subcarrier □ It is characterized by being phase-locked with the transmitted signal.

(実施例) 以下、図面を用いて詳細に説明する。(Example) Hereinafter, it will be explained in detail using the drawings.

第3図は、本発明の一実施例を示す回路図であって、w
、1図と同等部分には同一符号を付している。第3図に
おいて、入力端子Tiには、1水平走査毎に交互に二つ
の色差信号(R−Y)、 (B−Y)が加えられる。こ
れら色差信号は、1水平走査毎に切り換えられる切換ス
イッチsw4を介して一方の色差信号(It −Y)は
一方の加算器ADDRの一方の入力端子aに加えられ、
他方の色差信号(B −Y)は他方の加算器ADDBの
一方の入力端子8に加えられている。
FIG. 3 is a circuit diagram showing an embodiment of the present invention, w
, parts equivalent to those in Figure 1 are given the same reference numerals. In FIG. 3, two color difference signals (R-Y) and (B-Y) are applied alternately to the input terminal Ti every horizontal scan. These color difference signals are applied to one input terminal a of one adder ADDR through a changeover switch sw4 which is switched every horizontal scan, and one color difference signal (It-Y) is applied to one input terminal a of one adder ADDR.
The other color difference signal (B-Y) is applied to one input terminal 8 of the other adder ADDB.

一方の加算器ADDRの他方の入力端子すには1水平走
査毎に開離または閉成されるスイッチSW3.積分器鮮
を介して位相比較器PcRの出力信号が加えられている
。この加算器ADDRの出力信号は電圧周波数変換器V
/FRに加えられ、電圧周波数変換器V/Fの出力信号
s3は位相比較器PcRの一方の入力端子aK加えられ
ると共に1水平走査毎に切換スイッチSW4に連動して
切り換えられる切換スイッチSW5を介して出力端子T
oに送出される。位相比較器pCRの他方の入力端子す
には第1の色副搬送信号fRが加えられている。他方の
加算器ADDBの他方の入力端子すにはスイッチ5w3
Rと相補的に1水平走査毎に閉成または開離されるスイ
ッチsw。
The other input terminal of one adder ADDR is a switch SW3. which is opened or closed every horizontal scan. The output signal of the phase comparator PcR is added via an integrator. The output signal of this adder ADDR is transmitted to the voltage frequency converter V
/FR, the output signal s3 of the voltage frequency converter V/F is applied to one input terminal aK of the phase comparator PcR, and is passed through a changeover switch SW5 which is switched in conjunction with the changeover switch SW4 every horizontal scan. output terminal T
o. A first color subcarrier signal fR is applied to the other input terminal of the phase comparator pCR. The other input terminal of the other adder ADDB is connected to the switch 5w3.
A switch sw that is complementary to R and is closed or opened every horizontal scan.

B 積分器工8を介して位相比較器pcBの出力信号が加え
られている。この加算器ADDBの出力信号は電圧周波
数変換器vlFBに加えられ、電圧周波数変換器V/都
の出力信号s4は位相比較器pcBの一方の入カ端子a
lc加えられると共に前述の切換スイッチSW5を介し
て出力端子Toに送出される。位相比較器PCBの他方
の入力端子bKは第2の色副搬送信号fBが加えられて
いる。すガわち、第3図では、第1の色副搬送信号fR
9位相比較器pcR,積分器工□、加算器ADDR及び
電圧周波数変換器v/FRで第1の位相同期ループPL
LRが構成され、第2の色副搬送信号fB1位相比較器
pcB、積分器IB、加算器ADDB及び電圧周波数変
換器v/FBで第2の位相同期ループPLLBが構成さ
れている。これにより、一方の電圧周波数変換器vlF
Rからは色差信号(n −Y)で周波数変調された第1
の色副搬送信号fRが色信号S3として送出され、他方
の電圧周波数変換器V/FBからは色差信号(B −Y
)で周波数変調された第2の色副搬送信号fBが色信号
S4として送出されることになる。
B The output signal of the phase comparator pcB is added via the integrator 8. The output signal of this adder ADDB is applied to the voltage frequency converter vlFB, and the output signal s4 of the voltage frequency converter V/M is applied to one input terminal a of the phase comparator pcB.
lc is applied to the output terminal To via the aforementioned changeover switch SW5. A second color subcarrier signal fB is applied to the other input terminal bK of the phase comparator PCB. That is, in FIG. 3, the first color subcarrier signal fR
9 Phase comparator pcR, integrator □, adder ADDR and voltage frequency converter v/FR form the first phase locked loop PL.
LR is configured, and a second phase locked loop PLLB is configured by a second color subcarrier signal fB1, a phase comparator pcB, an integrator IB, an adder ADDB, and a voltage frequency converter v/FB. This allows one voltage frequency converter vlF
From R, the first signal is frequency-modulated by the color difference signal (n - Y).
The color subcarrier signal fR is sent out as the color signal S3, and the color difference signal (B - Y
), the second color subcarrier signal fB frequency-modulated is sent out as a color signal S4.

第4図は、第3図の動作説明図であって、(11)は入
力端子T1に加えられる色差信号S1を表わし、(b)
はスイッチ5W3Rの動作を表わし、(C)はスイッチ
5W3Bの動作を表わし、(d)は電圧周波数変換器V
/FRの出力信号S3の周波数変化を表わし、(e)は
電圧周波数変換器V/Fの出力信号S4の周波数変化な
表わし、(f)は出力端子TOに送出される出力信−号
S5の周波数変化を表わし、伝)は出力端子TOに送出
される出力信号S5の波形例を示している。時刻も1に
おいて、切換スイッチsw、、 SW5の可動接点Cけ
第1の位相同期ループPLLR側の固定接点aに切換接
続され、スイッチSW3退開離され、スイッチ5w3B
は閉成されている。これにより、第1の位相同期ループ
pLLR側の電圧周波数変換器V/FRからは積分器鮮
に保持されている第1の色副搬送信号fIIK関連しだ
信号を色差信号(R−Y)で周波数変調した信号s3が
送出され、第2の位相同期ループpLLBは第2の色副
搬送信号fBで位相がロックされることKなる。
FIG. 4 is an explanatory diagram of the operation of FIG. 3, in which (11) represents the color difference signal S1 applied to the input terminal T1, and (b)
represents the operation of the switch 5W3R, (C) represents the operation of the switch 5W3B, and (d) represents the operation of the voltage frequency converter V.
/FR represents the frequency change of the output signal S3, (e) represents the frequency change of the output signal S4 of the voltage frequency converter V/F, and (f) represents the frequency change of the output signal S5 sent to the output terminal TO. 2 represents a frequency change and shows an example of the waveform of the output signal S5 sent to the output terminal TO. At time 1, the movable contact C of changeover switch sw, SW5 is switched and connected to the fixed contact a on the first phase-locked loop PLLR side, switch SW3 is retracted and opened, and switch 5w3B is connected.
is closed. As a result, the voltage-frequency converter V/FR on the side of the first phase-locked loop pLLR converts the signal related to the first color subcarrier signal fIIK held in the integrator into a color difference signal (R-Y). A frequency-modulated signal s3 is sent out, and the second phase-locked loop pLLB is phase-locked with the second color subcarrier signal fB.

このような状態は、1水平周期区間が終了する時刻t2
まで保持され、第2の位相同期ループpLLBの電圧周
波数変換器vlFBの出力位相はその間に十分安定化さ
れる。次の水平周期区間が始まる時刻t2において、切
換スイッチsw4. sw5の可動接点Cは第2の位相
同期ループPLLB側の固定接点bK切換接続され、ス
イッチ5w3Rは閉成され、スイッチS)v 目開離さ
れている。これにより、第2の位相B 同期ループPLLB側の電圧周波数変換器vlFBから
は積分器工に保持されている第2の色副搬送−号fBに
関連した信号を色差信号(B−Y)で周波数変調した信
号Sが送出され、第1の位相同期ループPLLRけ第1
の色副搬送信号fRで位相がロックされるととになる。
This state occurs at time t2 when one horizontal period section ends.
During this period, the output phase of the voltage-frequency converter vlFB of the second phase-locked loop pLLB is sufficiently stabilized. At time t2 when the next horizontal cycle section begins, selector switch sw4. The movable contact C of sw5 is switched and connected to the fixed contact bK on the second phase-locked loop PLLB side, the switch 5w3R is closed, and the switch S)v is opened. As a result, the voltage-frequency converter vlFB on the side of the second phase B locked loop PLLB converts the signal related to the second color subcarrier number fB held in the integrator into a color difference signal (B-Y). A frequency modulated signal S is sent out to the first phase-locked loop PLLR.
When the phase is locked with the color subcarrier signal fR, the result is .

このような状態は、この水平周期区間が終了する時刻t
3まで保持され、第1の位相同期ループPLLユの電圧
周波数変換器V/FRの出力位相はその間に十分安定化
される。そして、続く次の水平周期区間が始まる時刻t
3において、前述の時刻t1と同様の状態に彷帰し、以
下、同様の動作を繰り返すことに々る。これにより、出
方端子Toには、第4図(f)及び(g)に示すような
出力信号S5が繰り返して送出されることになる。
This state occurs at the time t when this horizontal period section ends.
3, and the output phase of the voltage frequency converter V/FR of the first phase-locked loop PLL unit is sufficiently stabilized during that time. Then, the time t when the next horizontal periodic section starts
At step 3, the state returns to the same state as at time t1, and the same operation is repeated thereafter. As a result, the output signal S5 as shown in FIGS. 4(f) and (g) is repeatedly sent to the output terminal To.

このような構成によれば、従来のように水平帰線区間に
位相同期ループの位相口、りを行ったシミ圧周波数変換
器の動作を一旦停止させることなく、送出開始時の位相
が安定した色信号を得ることができる。また、各色副搬
送信号毎に位相同期ループを構成しているので、各位相
同期ループを各色副搬送信号に応じて設計すればよく、
従来のように両色副搬送信号で共用する場合に比べて比
較的安価な部品で構成することができ、全体としての回
路構成の簡単化も図れる。
According to such a configuration, the phase at the start of sending is stabilized without temporarily stopping the operation of the stain pressure frequency converter, which performs the phase opening of the phase-locked loop in the horizontal retrace interval as in the past. Color signals can be obtained. In addition, since a phase-locked loop is configured for each color subcarrier signal, each phase-locked loop can be designed according to each color subcarrier signal.
Compared to the conventional case in which both color subcarrier signals are used in common, components can be relatively inexpensive, and the overall circuit configuration can be simplified.

なお、上記実施例では、位相同期ループに積分器を用い
る例を示しているが、ローバスフィルりとサンプルホー
ルド回路の組み合わせを用いてもよい。
In addition, although the above embodiment shows an example in which an integrator is used in the phase-locked loop, a combination of a low-pass filter and a sample-and-hold circuit may be used.

(発明の効果) 以上説明したように、本発明によれに1比較的簡単な構
成で安定したSECAM方式の色信号を発生する信号発
生回路が実現できる。
(Effects of the Invention) As described above, according to the present invention, it is possible to realize a signal generation circuit that generates stable SECAM color signals with a relatively simple configuration.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の回路の一例を示す回路図、第2図は第1
図の動作説明図、第3図は本発明の一実施例を示す回路
図、第4図は第5図の動作説明図である。 T1・・・入力端子、TO・・・出力端子、ADD・・
・加算器、V/F・・・電圧周波数変換器、PC・・・
位相比較器、■・・・積分器 fRT fB・・・色副
搬送信号、SW3・・・スイッチ、SW、、 SW5・
・・切換スイッチ。
Figure 1 is a circuit diagram showing an example of a conventional circuit, and Figure 2 is a circuit diagram showing an example of a conventional circuit.
3 is a circuit diagram showing an embodiment of the present invention, and FIG. 4 is an explanatory diagram of the operation of FIG. 5. T1...input terminal, TO...output terminal, ADD...
・Adder, V/F...voltage frequency converter, PC...
Phase comparator, ■... Integrator fRT fB... Color subcarrier signal, SW3... Switch, SW, SW5.
...Choice switch.

Claims (1)

【特許請求の範囲】[Claims] 1水平走査毎に交互に(R−Y)の色差信号で周波数変
調された第1の色副搬送信号と(B−Y)の色差信号で
周波数変調された第2の色副搬送信号を色信号として送
出するように構成された5ECAlil方式色信号発生
回路において、各色信号系統毎に位相同期ループを設け
、一方の位相同期ループが色信号を送出する状態では他
方の位相同期ループをそのループに割り当てられている
色副搬送信号で位相口、りするようにしたことを特徴と
する5ECAλ1方式色信号発生回路。
The first color subcarrier signal frequency-modulated with the (R-Y) color difference signal and the second color sub-carrier signal frequency-modulated with the (B-Y) color difference signal are alternately used for each horizontal scan. In a 5ECAlil color signal generation circuit configured to send out a color signal, a phase-locked loop is provided for each color signal system, and when one phase-locked loop is sending out a color signal, the other phase-locked loop is connected to that loop. A 5ECA λ1 type color signal generation circuit characterized in that a phase shift is performed using an assigned color subcarrier signal.
JP16793383A 1983-09-12 1983-09-12 Secam system chrominance signal generating circuit Pending JPS6059889A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16793383A JPS6059889A (en) 1983-09-12 1983-09-12 Secam system chrominance signal generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16793383A JPS6059889A (en) 1983-09-12 1983-09-12 Secam system chrominance signal generating circuit

Publications (1)

Publication Number Publication Date
JPS6059889A true JPS6059889A (en) 1985-04-06

Family

ID=15858745

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16793383A Pending JPS6059889A (en) 1983-09-12 1983-09-12 Secam system chrominance signal generating circuit

Country Status (1)

Country Link
JP (1) JPS6059889A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2650142A1 (en) * 1989-07-24 1991-01-25 Perifelec Sa SECAM modulation system allowing easy locking of the colour sub-carrier oscillators by creating a measurement line

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5952987A (en) * 1982-09-20 1984-03-27 Sony Corp Modulator circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5952987A (en) * 1982-09-20 1984-03-27 Sony Corp Modulator circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2650142A1 (en) * 1989-07-24 1991-01-25 Perifelec Sa SECAM modulation system allowing easy locking of the colour sub-carrier oscillators by creating a measurement line

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