JPS5952987A - Modulator circuit - Google Patents

Abstract

PURPOSE:To simplify the constitution in an SECAM color TV system etc. by controlling the oscillation frequency of an oscillator so that the frequency becomes the frequency of the first and the second carriers line sequentially, and obtaining modulated waves obtained by modulating each carrier line sequentially. CONSTITUTION:An FM modulated R-Y signal and a B-Y signal of the SECAM color TV system are supplied to DC shifters 20, 23 respectively. Switches 21, 28 32 are switched from a terminal 24 by a control signal Sc to be a high and a low level at every one horizontal period. One of DC shifters is shifted according to the output value of a sample hold circuit 30, and supplied as the control voltage of a voltage control type variable frequency oscillator 25. The output is compared with one of terminals 27, 29 to which the reference oscillation signals of two carriers are supplied by a phase comparator 26 and the signal corresponding to a phase difference is supplied to the sample hold circuit 32. Thus, the two cariers frequencies are generated line sequentially by changing a PLL loop at each horizontal period.

Description

[Detailed description of the invention] Industrial usage jJ.

'Kienri' is suitable for use in obtaining line sequential signals of FM modulated R-Y (red difference) signals and B-Y (77 color difference) signals transmitted in the SFCAM color television system, for example. Related to modulation circuits.

Weight technology and its problems In the SECAM color television system, the carrier frequency is FM modulated at 4.40625 MFiz.
Y signal and the carrier frequency is 4.25M1-(-z T F
The M-modulated B-Y signal is transmitted every horizontal period, that is, line-sequentially. In this way, the R-Y signal and the B-Y
Since the carrier frequencies of the signals are different, conventionally this line 1 [next signal is ! To do this, a modulation circuit is used in which each modulator is provided for FM modulating each color difference signal.

FIG. 1 shows an example.

In the same figure, (1) is a terminal to which the RY signal is supplied, and the RY signal supplied to this terminal (1) is OFF for 1 minute!
It is supplied to one fixed terminal (2a) of the switch (2).

A predetermined voltage vl (is applied to the other force fixed terminal (2b) of this changeover switch (2).
ψ? 1, 1 child (3), the control signal S becomes high level "1" and low level "O" every horizontal period. is supplied as a switching signal. The changeover switch (2) is configured so that the control plI signal Sc is set to a high level "1" and a low level "0".
'', the movable terminals (2c) are switched to be connected to one fixed terminal (2a) and the other fixed terminal (2b), respectively.

The signal obtained at the movable terminal (2C) of this changeover switch (2) is supplied to an adder (4). The output of this adder (4) is supplied as a control voltage to a voltage controlled variable frequency oscillator (5). The oscillation output of this oscillator (5) is supplied to a phase comparator (6). This phase comparator (6) is supplied with a reference oscillation signal fRgp (rt) having a frequency of 4.40625 MIIz from a terminal (7), and the comparison error signal from this phase comparator (6) is sent to the Zambrepoort circuit. (8). This sample hold circuit (8) is also supplied with the control signal Sc from the DIL 5 (3), and this sample hold circuit (8) performs a sampling operation during one horizontal period when the control signal Sc is at a low level "0". , the hold mode is set to 1' during 1 horizontal period lI1 where the high level is "1".

The hold output of this sample and hold circuit (8) is supplied to an adder (4).

In this case, during one horizontal period when the control signal Sc is at a low level "0", the PL is controlled by the loop of the oscillator (5), phase comparator (6), sample and hold circuit (8), and adder (4).
An L (phase-locked loop) circuit is configured, and an oscillator (
nEp so that the output of 5) is synchronized with the reference oscillation signal f.
(Controlled by R1.) - On the other hand, the control signal Sc is at a high level "R1"
”, the sample and hold circuit (8) receives the reference oscillation signal fRK from the output of the oscillator (5).
The comparison error signal when synchronized with Fltl is held and supplied to the adder (4). And during this period,
The adder (4) is supplied with the RY signal. Therefore, during this one horizontal period, the sending frequency from the oscillator (5) is 4.
．． 40625 Mllz'T FM 9'fl modulated RY signal is obtained.

The output of this oscillator (5) is supplied to one fixed terminal (9a) of a changeover switch (9).

In this first diagram, (1Q is B - Y 4 knee)
This is the terminal to which the S signal is supplied, and the B-Y signal supplied to this terminal (11) is connected to one fixed terminal (1
1a). A predetermined voltage VB is applied to the other fixed terminal (llb) of the changeover switch αη. A control signal Sc supplied from a terminal (3) is supplied as a switching signal to this changeover switch 0] via an inverter α. Then, the changeover switch 0]) is controlled by the control signal S
When c is at a low level "0" and a high level "1", its movable terminal (llc) is switched to be connected to one fixed terminal (lla) and the other fixed terminal (llb), respectively.

The signal obtained at the movable terminal (llc) of this changeover switch αη is supplied to the adder QIK. The output of the adder α1 is supplied as a control voltage to the voltage controlled variable frequency oscillator α. The oscillation output of this oscillator 0→ is the phase comparator θ
supplied to. This phase comparator 0υ is connected to a reference oscillation signal having a frequency of 4.25 MHz from terminal 0Q.

F(11) is supplied, and the comparison error signal from this phase comparator 0υ is supplied to the Zanzor hold circuit α.The control signal Sc supplied from the terminal (3) is also supplied to this sample hold circuit a. Supplied via inverter 0■,
This sample and hold circuit α performs a sampling operation during one horizontal period when the control signal Sc is at a high level "1",
One horizontal period in which the low level is "0" is set to a hold mode.

The bold output of this sample hold circuit α is
: Supplied to vessel α1.

In this case, during one horizontal period when the control signal SC is at a high level "1", a PLL circuit is configured with a loop of oscillator α→, phase comparator θυ, sample and hold circuit 0η, and adder 01, and the output of oscillator α→ is the reference oscillation signal fREF (
It is controlled to be synchronized with Bl. On the other hand, the control signal Sc
During one horizontal period when is at a low level "0", the sample-and-hold circuit θ holds the difference signal of the comparator REFill when the output of the oscillator α→ is synchronized with the reference oscillation signal f, and this is the difference signal of the adder 0. During this period, the B-Y signal is supplied to the adder 0'3.Therefore, during this one horizontal period, the carrier frequency from the oscillator 0 is 4.25 Mllz''? ? An FM modulated 13-Y signal is obtained.

The output of this oscillator 0◆ is supplied to the other fixed terminal (9b) of the changeover switch (9).

The changeover switch (9) receives a control signal SC from the terminal (3).
is supplied as a switching signal. When the control signal Sc is at a high level "1" and a low level "0°", the changeover switch (9) has a movable terminal (9c) at one fixed terminal (9a) and another fixed terminal (9a), respectively. 9b).

In the end, the carrier frequency is 4.0 at terminal 0, which is derived from the movable terminal (9c) of this changeover switch (9). ．． 4062
5 MIIz FM modulated R-Y signal and FM modulated eJ, '6 carrier frequency 13-
The Y signal is sequentially turned on every horizontal period.

In this way, according to the example in FIG.
Modulators for f-tuning were provided individually (oscillators (5) and a→), and accordingly, loops constituting the PLL circuit were also provided individually, resulting in many unnecessary parts.

Furthermore, since it has two oscillation sources, there was a concern that they would interfere with each other.

OBJECTS OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to propose a modulation circuit which has a simple configuration and is free from the fear of interference from the oscillation source.

4 Existing Summary of the Invention In order to achieve the above object, the modulation circuit according to the present invention has the following features:
The first modulated wave obtained by modulating the general transmission wave and the second modulated wave obtained by modulating the second carrier wave are line-sequentially 14
A single variable frequency oscillator gold film is used in the modulation circuit, and the wave number of the oscillator film layer of this oscillator is controlled line-sequentially to become the frequency of the first and second carrier waves. It is something.

Since the present invention is configured with a single variable frequency oscillator in this manner, the configuration is simple, and since there is only one oscillation source, there is no need to worry about interference.

Embodiment Hereinafter, with reference to FIG. 2, a modulation circuit according to the present invention will be explained.
Line J! of FM modulated R-Y and B-Y signals transmitted in the SECAM color television system. I
Let us explain an example in which the D-order signal is used to generate all signals.

In the figure, α1 indicates a terminal to which the RY signal is supplied, and the RY signal supplied to this terminal α is supplied to the DC shifter core. In this DC shifter (1),
R for the hold output of the sample and hold circuit, which will be described later.
-Y signal is DC shifted.

The output of this DC shifter (A) is supplied to one fixed terminal (21a) of the changeover switch (C).

Further, 02 indicates a terminal to which a BY signal is supplied, and the BY signal supplied to this terminal (A) is supplied to a DC shifter. Also in this DC shifter (to), the BY signal is DC-shifted by the hold output of the sample-and-hold circuit, which will be described later. The output of this DC shifter (e) is supplied to the other fixed terminal (21b) of the changeover switch QI).

The changeover switch Q) is connected to a control signal S that changes to a high level "1" and a low level "0" every horizontal period from terminal 0 to terminal 0.
C (shown in the third diagram) is supplied as a switching signal. Then, when the changeover switch Qυ is selected, the control signal Sc is at a high level.
■” and low level “0”, respectively, the movable terminal (2
1c) is one fixed terminal (21a) and the other fixed terminal 51
It is connected to the DAM child (21b). Therefore, the movable terminal (21c) of this changeover switch Q]) is supplied with line sequential signals (the third (Illustrated in Figure C) is obtained.

The signals obtained at the Q movable terminals (21c) of the changeover switches are supplied as control voltages to the voltage-controlled variable frequency oscillator (c). The oscillation output of this oscillator (c) is supplied to the phase comparator Q0.

In addition, 4.406251 VU (
A reference oscillation signal f having a frequency of y is supplied,
This is supplied to one fixed terminal (2811) of the switching switch RFiFtR1 Sochi Co., Ltd. Also, terminal 17! A reference oscillation signal f having a frequency of 4.25 MfTz is supplied to jl, and this is supplied to the other fixed terminal (28b) of the changeover switch (c) gFlsl. This selector switch (c) receives a control signal Sc from the terminal (c).
is supplied as a switching signal. Then, select the changeover switch (
C) is such that when the control signal Sc is at a high level "■" and a low level "0", the movable terminal (28c) is connected to one fixed terminal (28a) and the other fixed terminal (28b), respectively. Therefore, during one horizontal period when the control signal S is at a high level "1" (the R-Y signal is supplied to the oscillator), the movable terminal (28e) of the changeover switch 9 is switched to The reference oscillation signal fREFt.
Control signal S. During one horizontal period when is at a low level "ON" (the B-Y signal is supplied to the oscillator (c)), reference oscillation signals fRP and FtB+ are obtained, which are output by the phase comparator (
supplied to

The comparison error signal from this phase comparator (c) is supplied to a sample and hold circuit (g). This sample hold circuit O0 has a horizontal blanking period TB
, a signal PG (shown in FIG. 3B) is supplied which has a high level "1" only during the period 'ro' up to the trailing edge of horizontal synchronization No. 44 1b + sync, and has a low level "0" during the other periods. Therefore, this Sansol hold circuit CM performs a sampling operation during one horizontal period when the No. 48 PG is at a high level "1", and is in a hold mode during one horizontal period when the low level is "On".

The bold output of this Sansol hold circuit (g) is supplied to the movable terminal (32c) of the changeover switch 03.

This changeover switch 0 is connected to the control 41 from the terminal (c).
□ SC is supplied as a switching signal. When the control signal SC is at a high level "1" and a low level "0", the changeover switch 02 has a movable terminal (32c) on one fixed terminal (32a) and the other fixed terminal (32b,
). Therefore, one fixed terminal (32a) of this changeover switch 02 is connected to one horizontal period (oscillator (
A hold output is supplied at (b) where the R-Y signal is supplied, and this is rarely supplied to the DC shifter.

On the other hand, the changeover switch (32 fixed terminal (32b)
) is supplied with a hold output during one horizontal period when the control signal Sc is at a low level "O" (the B-Y signal is supplied to the oscillator (c)), and this is supplied to the DC shifter (a). .

In addition, the oscillation output SO of the oscillator (c) is connected to the gate circuit 01.
supplied to An output terminal 0→ is derived from this gate circuit 01. This gate circuit 0) receives a signal P from a terminal 3]). is supplied as a dart signal,
This signal P. The gate is opened only during the period when the signal is at a low level "0".

The example shown in FIG. 2 is constructed as described above, and at the time point 1°, the control signal S is activated. (Illustrated in the third diagram) is at a low level ゛O''
When the high level "1" is reached, the selector switch (21)
, (c), and 0 area are respectively switched as shown in the figure.

Then, from this time point t1 to t2-1, the time period of To is 1,
The signal P, (shown in FIG. 3B) goes to a high level 61'', and the sample-and-hold circuit (g) performs a sampling operation.

Therefore, during this period of To, the oscillator (c), the phase comparator (
C), Sansol hold circuit (G), Dc shifter (1)
A PLL circuit is constructed by the loop of , and the oscillator (c)
The oscillation output So (shown in Figure 3E) is 4.40625
MJ (reference oscillation signal fR with frequency z
It is done so that 1 is the same as 1. Furthermore, this To period,
I) The n-Y signal supplied to c shiftahi 0 is no signal.

At time t2 when the period To ends, the sample and hold circuit Of is put into the hold mode, and the oscillator 0
The comparison error signal from the phase comparator Q when the oscillation output SO of 9 and the reference oscillation output fRytn+ are synchronized is held, and is supplied to the DC shifter (1) via the changeover switch o2. Therefore, after this, the control signal SC
During JIJJ where is high level "1", ■) c shifter (
The R -Y (Q) supplied to the oscillator (Company) is shifted by the supplied bold output and is supplied as a control voltage to the oscillator (c) via the changeover switch Qυ.

Therefore, this control signal S. During the period when is at high level "1", the oscillation output So of the oscillator (c) is 4.40625
The RY signal FM modulated with a MHz carrier wave is multiplied by +3.

On the other hand, the control signal sC changes from the high level ``1'' to the low level ``O''.
When this happens, the changeover switches Qρ, (c) and 0→ are respectively switched to the opposite side from that shown in the figure. After that, the operation is the same as described above. Therefore, this control signal S. During the period when is at low level “0”, the oscillation output So of the oscillator (c)
As, FM with 4.25 MFIz lli, i' transmission
A modulated B-Y signal is obtained.

According to the example in FIG. 2, since the oscillator (c) of η1- is formed in 11 units, the ↑1゛·v formation is simple. Moreover, since the oscillation source is only the oscillator (c), mutual interference between the L and L oscillation sources cannot occur.

Next, FIG. 4 shows another '=A embodiment of the present invention, in which β
The oscillation output So of the oscillator is reliably fixed at a predetermined carrier frequency during the period To when the signal PG is at a high level "1". In this Figure 4,
Portions corresponding to those in FIG. 2 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

In the figure, the comparison error signal of the phase comparator (20) is supplied to the movable terminal (32c) of the changeover switch 02.

Therefore, one fixed terminal (3
In 2a), a comparison error signal is supplied during one horizontal period when the control signal sc is at a high level "1" (the oscillator (25) is supplied with R-Y (i'i signal), and this is supplied to the sample and hold circuit. () 9. On the other hand, between the control
C) A comparison error signal is supplied to the sample and hold circuit (10) in which the B-Y signal is supplied.

Also, a control signal S is supplied to the terminal (c). is supplied to AND circuit 0, and is inverted and output to AND circuit 0.
1>. It's ox, these AND circuits Ono and 0
→ is signal P from terminal 0. is supplied. Therefore, the AND circuit outputs the signal P in one horizontal period when the oscillator (c) KRY signal is supplied. The signal P is at a high level only during the period To when the signal P is at a high level "1". 1 is obtained, which is supplied to the special hold circuit C35). And this Zanzor hold circuit 0 rubber, this signal P. The period in which 1 is at the low level "0" is set as a hold mode. 1, AND circuit. →Gara is an oscillator (
211I), the signal PG is at a high level during one horizontal period when the 13-Y signal is supplied with 1↓(It 1 #j). is supplied to IFG, and
This sample and hold circuit a0 is connected to this unit P. 2 is at a low level It_OII is set as a hold mode.

Excellent number hold circuit O') and c! The hold outputs of 6 are supplied to DC7 lid) and lZ3+, respectively.

The rest is 47 pieces in the same way as the example in Figure 2.

In this figure 4 example? and control signal S. is at a low level
When the level changes from 0" to high level "'l", the selector switch t2
il.

, !+9 and 0→ are respectively switched as shown in the figure. Then, during the period To when the signal P is at a high level "'1", the sample and hold circuit Q performs a sampling operation.

Therefore, during this period of To, the oscillator u5), the phase comparator u
li), a sample hold circuit (four), a PLL circuit is formed by the loop of the DC shifter (e), and the oscillation output of the oscillator (2!i) is a reference oscillation signal fnosui with a frequency of 4.40625 MHz. Thereafter, the operation is the same as in the example shown in FIG.
As the oscillation output So, an RY signal FM-modulated with a carrier wave of 4.40625 MHz is obtained.

On the other hand, the control signal Sc changes from high level "1" to low level "0".
'', the changeover switches (c), (c), and (32) are switched to the opposite side from the one shown in the figure.Then, during the period T when No. 41 Po is at the high level "1", the sample and hold circuit is turned on. OQ performs a sampling operation. Therefore, C1 During this To period, a PLL circuit is constructed by the loop of the oscillator (C), phase comparator (2G, wrangle hold circuit (3f'9, ]), C shifter body Y, The oscillation output S0 of the oscillator (c) is synchronized with 4.25 MHz.After that, the operation is the same as in the example in Fig. 2, and during the period when this control signal Sc is at the low level "0", As the oscillation output So, FM modulation is performed with a carrier wave of 4.25 MFrz to obtain B-Ya@.In the end, even in this example in Fig. 4, the output terminal 0→ has 4
．． R-Y FM modified with 40625 MHz carrier wave
A line-sequential signal of the B-Y signal is obtained which is FM modulated with a carrier wave of 4.25 M+-1z.

According to the example in FIG. 4, since it is composed of a single oscillator (c), the same effect as the example in FIG. 2 can be obtained. Furthermore, according to the example in FIG.
Since the hold output supplied to the C shifter (A) and the soft ◆ is held to that extent, the oscillation output of the oscillator (to the oscillator) can be suddenly changed as shown in FIG. 4F, and the signal P. T whose height is 4 le "1".

The oscillation output 80 of the oscillator is reliably fixed at the predetermined general transmission frequency within the period of . Therefore, more stable FM modulation can be performed.

Effects of the Invention As is clear from the embodiments described above, the modulation circuit according to the present invention is composed of a single oscillator, so its configuration is w3#J-. Moreover, since there is only one oscillation source, there is no fear of mutual interference between the oscillation sources.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a conventional modulation circuit, FIG. 2 is a block diagram showing an example of a modulation circuit according to the present invention, FIG. 3 is a diagram for explaining the same, and FIG. 4 is a block diagram showing an example of the present invention. It is a tl'\\ composition diagram showing another example. (C) is a voltage-controlled variable frequency oscillator, and 0◆ is an output terminal. Same as Hidemori Matsukuma 1. ,＞. , j 11. ,,,,,,. '(, "Hot 11'- Figure 7, 40

Claims (1)

[Claims] Modulate the first modulated wave obtained by modulating the first carrier wave and the second carrier wave? In a modulation circuit such that the second modulated wave generated by G is obtained on the line j■, a variable frequency oscillator is provided, and the oscillation layer mK9 of this oscillator is set to T%! A modulation circuit characterized by controlling the frequencies of the first and second carrier waves sequentially.