JPS6058715A - Circuit for preventing oscillation stop - Google Patents

Abstract

PURPOSE:To suppress the increase in the number of wires and circuit scale even with multi-stage of pseuso random signal (PN) generating circuits by providing an NOR circuit and an integration circuit inputting two inputs to an EX-OR circuit constituting the PN signal generation circuits. CONSTITUTION:An output of SR(shift registers) 1-3 is all 0, an output of an NOR circuit 11 goes to 1 and a potential at a point (f) of an inegration circuit 12 is risen according to the time constant as shown in Fig. When the potential at the point (f) is higher than the reference potential of an OR circuit 10, a point (a) goes to 1 level as shown in A and a potential of a point (b) goes to 1 level as shown in B. When an output of any one of the SRs goes to 1, the circuit starts generation of a PN signal and when the level at a point (c) goes to 1, an output of an NOR circuit 11 goes to 0, a potential at the point (f) is changed rapidly to 0 by the operation of a diode D as shown in (f) and no effect is given to the generation of signal. In this case, even if the SR is constituted in multi- stage, input lines to the NOR circuit 11 will do with two input lines to the EX-OR circuit 6. Further, the wires through the NOR circuit, integrating circuit and the diode are as shown in Fig.

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to an oscillation stop prevention circuit when a pseudo-random signal generation circuit is in an oscillation stop state (the output of a shift register is all 0 level). The present invention relates to an oscillation stop prevention circuit whose circuit scale does not change even when the number of oscillation stops increases.

(b) Prior art and problems Figure 1 shows a conventional pseudo-random signal generation M path (hereinafter referred to as PN).
FIG. 2 is a block diagram of a signal generation circuit (referred to as a signal generation circuit).

In the figure, 1 to 5 are shift registers (hereinafter referred to as SR), 6 is an exclusive OR circuit (hereinafter referred to as EX-OR circuit), 7,
8. to indicates an OR circuit, and 9 indicates a NOR circuit.
The X-OR6 constitutes a PN signal generation circuit.

The PN signal generation circuit becomes SR when the power is turned on or due to noise, etc.
The outputs of I to 5 may become all 0 level and stop oscillation.For this reason, conventionally all outputs of SR1 to 5 are passed through OR circuit 7.8 and the output of this OR circuit 7.8 is passed to NOR circuit 9.
and pass the output of the NOR circuit 9 through the OR circuit 10,
For example, input it to the SRI input, and SR1
When the outputs of ~5 become all 0 level, a level is input to the SRI input to automatically oscillate.

In this conventional method, if the output of any one of SR1 to SR5 is level, the output of NOR circuit 9 is at 0 level and does not affect the PN signal generation, and all outputs of SR1 to 5 are θ.
In order to set the output of the NOR circuit 9 to the L level when the output reaches the L level, all outputs of SR1 to SR5 must be passed through the OR circuit 7.8 and the NOR circuit 9 (the NOR circuit for high speed is currently (There is nothing more than 5 manpower) The more stages of SR, the more S.
There is a drawback that the number of wires to the circuit increases from the output of R, and the (b) circuit size of the OR circuit NOR circuit increases.〇(c
OBJECT OF THE INVENTION In view of the above drawbacks, the object of the present invention is to provide an oscillation stop prevention circuit in which the number of wiring from the SR output side does not increase and the circuit size does not increase even if the number of SR stages in the PN signal generation circuit increases. It's on offer.

(d) Structure of the Invention In order to achieve the above object, the present invention provides an EX
- A NOR circuit that inputs two inputs to the OR circuit, and an integrator circuit that takes the output of the NOR circuit as input and connects the output to the SR input of the PN signal generation circuit, and the output of the integrator circuit and the NOR circuit The outputs of the PN signal generating circuit are connected through a diode, and when the outputs of all SRs of the PN signal generating circuit reach the θ level, the output of the SR connected to the reading integrating circuit is set as a level by the output of the integrating circuit. It is characterized in that when the output of the NOR circuit reaches the θ level, the output level of the reading and integrating circuit becomes the O level.〇(e) Embodiment of the Invention An embodiment of the present invention will be described below with reference to the drawings. 0th 2nd
The figure is a block diagram of a PN signal generation circuit according to an embodiment of the present invention.
FIG. 3 is a time chart of waveforms of various parts in the case of FIG. 2, where CLK is a clock, and corresponds to points (A) to (a) to f in FIG. 2.

In the figure, components having the same functions as those in FIG. 1 are designated by the same symbols. 011 is a NOR circuit, 12 is an integrating circuit, D is a diode, R is a resistor, and C is a capacitor.

FIG. 2 shows an example in which a three-stage PN signal generating circuit repeatedly sends out a pattern of tttooto as a PN signal. Further, the integrating circuit 12 uses a circuit constituted by a resistor R capacitor C.

When the outputs of SR1 to SR3 become all 0 level and the oscillation is stopped, the output of the NOR circuit 11 becomes level, and the potential at point f of the capacitor C of the integrating circuit [2] becomes equal to the resistor R as shown in Fig. 3 (G). When the potential at point 01, which gradually rises according to the time constant of capacitor C, becomes higher than the reference potential for identifying the 0 level and level of the OR circuit 10, the output point a of the OR circuit 10 becomes as shown in FIG. 3 (4). Became Rubel, SR
Point b of the output of L becomes a level as shown in Figure 3 (03).When the output of any one SR of the OPN signal generation circuit becomes a level, this circuit starts generating a 0 pattern, which starts generating a pattern of tttooto. In the circuit shown in FIG. 2, when the level at point C becomes L level, the output of the NOR circuit 11 becomes the θ level, and the potential at point f is changed to the diode D as shown in FIG.
Due to the action of , it rapidly changes to the θ level and no longer affects pattern generation. In this case, even if S and R are multi-staged, the input lines to the NOR circuit 11 only need to be two input lines to the EX-OR6 circuit, and there is no need to increase wiring.

Wiring via a NOR circuit, an integrator circuit, and a diode is also
With the help of a diagram, the more stages there are, the smaller the circuit size can be compared to the conventional one.In addition, the output of the integrator circuit 12 can be determined by using an OR circuit that takes the logical sum with the output of the signal line. It may also be added to the input of the SR.

(f) Effects of the Invention As explained in detail above, according to the present invention, even if the number of SR0'' stages of the PN signal generation circuit increases, the number of wires in the oscillation stop prevention circuit does not increase and the circuit scale does not change. Therefore, as the number of stages increases, there is an effect that the oscillation stop prevention circuit can be made smaller than the conventional one.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional pseudo-random signal generation circuit, FIG. 2 is a block diagram of a pseudo-random signal generation circuit according to an embodiment of the present invention, and FIG. 3 is a time chart of waveforms of various parts in FIG. be. In the figure, 1 to 5 are shift registers, 6 is an exclusive OR circuit, 7, 8.10 is an OR circuit, 9.11 is a NOR circuit, and 12
is an integrator circuit, D is a diode, R is a resistor, and C is a capacitor.

Claims (1)

[Scope of Claims] A pseudo-random signal generation circuit includes a NOR circuit whose input is the input to the exclusive OR circuit, and whose output is input and whose output is input to a shift register of the pseudo-random signal generation circuit. A connecting integrating circuit is provided, and the output of the integrating circuit and the output of the NOR circuit are connected via a diode. When the outputs of all shift registers of the pseudo-random signal generating circuit reach the θ level, the outputs of the shift registers connected to the integrating circuit are set as a level by the output of the integrating circuit,
An oscillation stop prevention circuit characterized in that when the output of the NOR circuit reaches the θ level, the output level of the integrating circuit becomes 0 level.