JPS6058683A - Manufacture of light receiving element - Google Patents

Manufacture of light receiving element

Info

Publication number
JPS6058683A
JPS6058683A JP58167780A JP16778083A JPS6058683A JP S6058683 A JPS6058683 A JP S6058683A JP 58167780 A JP58167780 A JP 58167780A JP 16778083 A JP16778083 A JP 16778083A JP S6058683 A JPS6058683 A JP S6058683A
Authority
JP
Japan
Prior art keywords
layer
film
impurity
guard ring
dielectric film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58167780A
Other languages
Japanese (ja)
Inventor
Kazuo Shigeno
重野 和男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58167780A priority Critical patent/JPS6058683A/en
Publication of JPS6058683A publication Critical patent/JPS6058683A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Light Receiving Elements (AREA)

Abstract

PURPOSE:To manufacture the titled element so as to reduce the surface leakage current by a method wherein a guard ring and a channel stopper are formed at a time of process of heat treatment by the use of a double-layer or a three-layer dielectric film as a selective mask in the formation of the guared ring by the thermal diffusion of impurity. CONSTITUTION:The dielectric film of the first layer is patterned so as to serve as a selective mask for a channel stopper, and the dielectric film of the second layer adhesion-formed thereon uses a film containing an impurity which cannot penetrated through the first layer at a diffusion temperature for guard ring formation and has the same conductivity type as that of a substrate. Further, in some case, the third layer to prevent the evaporation of the second layer impurity is adhered and then made as a selective diffusion mask for an impurity to form the guard ring as a whole of the double layer or the three layers. Thereby, the number of the process of heat treatment during the manufacturing process and that of the process wherein the exposed part of the P-N junction loses a film are made as small as possible, and accordingly the surface leakage current can be reduced.

Description

【発明の詳細な説明】 本発明は半導体受光素子の製造方法に関するものでアシ
、特にガードリング形成時の拡散マスクに関するもので
ある。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor light-receiving device, and particularly to a diffusion mask used when forming a guard ring.

光通信用の受光器等に使用される牛導体受光素子、中で
も高速高感度のアバランシェ・フォト・ダイオード等に
於ては、その受光領域が一導電型を示す半導体基板表面
に、基板と導電型の異なる極めて浅い高濃度不純物領域
を形成することでなっておシ、その外周部分の局所的降
伏を防ぐために受光領域と同じ導電型の深い低濃度不純
物領域が前記受光領域外周部を含むようにガードリング
を形成し、さらにその外側に、表面漏れ電流を低減する
ために基板と同じ導電型の不純物を導入してチャネルス
トッパーを形成するという構造をとっているものが多い
In conductor light receiving elements used in optical receivers, etc., especially in high-speed, high-sensitivity avalanche photodiodes, the light-receiving area is located on the surface of a semiconductor substrate that exhibits a single conductivity type. In order to prevent local breakdown at the outer periphery, a deep low concentration impurity region of the same conductivity type as the light-receiving region is formed to include the outer periphery of the light-receiving region. Many devices have a structure in which a guard ring is formed, and an impurity of the same conductivity type as the substrate is introduced outside the guard ring to reduce surface leakage current to form a channel stopper.

従来、このチャンネルストッパを形成するには基板と同
一の導電型ケ示す不純物を選択的に拡散するかあるいは
イオン注入を行なった後熱処理を行なう専の手法が用い
られてきたが、要するに、チャンネルストッパ形成のた
めに熱処理工程1 一つ要したわけでるる。
Conventionally, to form this channel stopper, a special method has been used in which impurities having the same conductivity type as the substrate are selectively diffused or ion implantation is performed followed by heat treatment. One heat treatment step was required for formation.

一般に、受光素子は熱処理の際にマスク材料とウェハー
ス表面との界面の熱歪によシ、ウェハース表面に結晶欠
陥が発生しやすく、これが表面漏れ電流の増大全招く要
因となることが多い。この結晶欠陥を低減するには、マ
スク材料の選定、熱処理速度の緩40.キャップレスの
熱処理等の手法があυ、また結晶欠陥奮除去するために
熱処理後結晶表面をエツチングする等の手法があるが、
全ての欠陥を回避するのは困難であるのが現状で、熱処
理工程が多いことはそれだけ界面状態を悪化させると考
えてよい。特に、基板材料がGe、−?N −V族化合
物である場合には適切な表面保護膜が見出されていない
ため、この熱処理工程で発生する表面の結晶欠陥による
表面漏れ電流の増大即ち暗電流の増大には著[7いもの
がある。
In general, in a light receiving element, crystal defects are likely to occur on the wafer surface due to thermal strain at the interface between the mask material and the wafer surface during heat treatment, and this is often a factor that causes an increase in surface leakage current. To reduce these crystal defects, select a mask material and slow the heat treatment rate.40. There are methods such as capless heat treatment, and methods such as etching the crystal surface after heat treatment to remove crystal defects.
At present, it is difficult to avoid all defects, and it can be considered that increasing the number of heat treatment steps will worsen the interface condition. In particular, if the substrate material is Ge, -? In the case of N-V group compounds, no suitable surface protective film has been found, so the increase in surface leakage current, that is, the increase in dark current due to crystal defects on the surface generated in this heat treatment process is significant [7]. There is something.

一方、受光素子の製造工程は、受光領域、ガードリング
、チャネルストッパなどの諸機能領域を順次不純物を選
択的に熱拡散あるいはイオン注入することによシ形成し
てゆくわけであり、前述のように、GeやJI[−V族
化合物の場合、ウェハースの熱酸化による保護膜形成と
いう手法が用いられないので各不純物導入工程の選択マ
スクはその都度被着形成し次工程で除去することをくシ
返さなければならない。即ち、工程間でGeg板表面が
?茸呈する機会が多い。表面漏れ電流が流れる箇所はp
n接合の表面露呈部分であシこの箇所も被着形成、エツ
チング除去が繰り返されると界面状態が悪化し、即ち、
界面単位を増やすことに表り、表面漏れ電流の増大を招
く。
On the other hand, in the manufacturing process of a photodetector, various functional regions such as a photodetection region, a guard ring, and a channel stopper are sequentially formed by selective thermal diffusion or ion implantation of impurities. In addition, in the case of Ge and JI[-V group compounds, the method of forming a protective film by thermal oxidation of the wafer is not used, so the selection mask for each impurity introduction process needs to be deposited each time and removed in the next process. I have to give it back. In other words, is the surface of the Geg plate between processes? There are many opportunities for mushrooms to appear. The point where surface leakage current flows is p
If adhesion formation and etching removal are repeated at the surface exposed portion of the n-junction, the interface condition deteriorates, that is,
This results in an increase in the number of interface units, leading to an increase in surface leakage current.

要するに、GeやN−V族基板を用いた受光素子に於て
はその製造工程にて熱処理の工程およびpn接合露呈部
が被膜を失う工程を出来るだけ少なくすることが、表面
漏れ電流を低減し、即ち暗電流を小さく押えることに通
じる。
In short, in the manufacturing process of a photodetector using a Ge or N-V group substrate, minimizing the heat treatment process and the process in which the exposed pn junction loses its coating reduces surface leakage current. In other words, this leads to keeping the dark current low.

本発明の目的は、上記の様な工程上の問題を克服し、従
来方法に比べ暗電流を低減した受光素子の製造方法を提
供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a light-receiving element that overcomes the process problems described above and reduces dark current compared to conventional methods.

本発明による製造方法によれば、ガードリングを不純物
の熱拡散で形成する際の選択マスクとして2層あるいは
3層の誘電体膜を用い、その時各層は下記の要件を溝た
すように形成されることによシ、一度の熱処理工程でガ
ードリングおよびチャネルストッパ双方が形成でき、上
記目的を満足させることができる。即ち、第1層の誘電
体膜はチャネルストッパのための選択マスクになる様に
パターニングされ、その上に被着形成される第2層の誘
電体膜は、ガードリング形成の拡散温度では第1層を透
過できない基板と同電導型の不純物を含むものを用い、
さらに場合によっては第2層の不純物の蒸発を防ぐため
の第3Mを被着させ、これら2層あるいは3層の総体と
してガードリング形成用不純物の選択拡散マスクと成り
得ることである。
According to the manufacturing method of the present invention, a two-layer or three-layer dielectric film is used as a selective mask when forming a guard ring by thermal diffusion of impurities, and each layer is formed so as to satisfy the following requirements. Particularly, both the guard ring and the channel stopper can be formed in one heat treatment process, and the above object can be satisfied. That is, the first layer dielectric film is patterned to serve as a selective mask for the channel stopper, and the second layer dielectric film deposited thereon is patterned at the diffusion temperature for guard ring formation. Using a material containing impurities of the same conductivity type as the substrate that cannot pass through the layer,
Further, in some cases, a third layer M is deposited to prevent evaporation of impurities in the second layer, and these two or three layers as a whole can serve as a selective diffusion mask for impurities for forming a guard ring.

以下に図面を参照しながらゲルマニウム(Ge)の受光
素子の製造工程例をとって説明する。
An example of a process for manufacturing a germanium (Ge) light receiving element will be described below with reference to the drawings.

Geのp+n型受光受光素子成するために、そのガード
リングを亜鉛(Zn)の熱拡散によって形成する場合、
ノンドープのシリコン酸化膜(8i02膜)ではマスク
としての役割を果たさず、Znを透過させてしまうので
、拡散マスクには燐(ト)を5mo1%程度以上含むシ
リコン酸化膜(PSG膜)を用いなければならない。と
ころが、このPはGeに対してn型不純物として働くた
めに、Pの拡散を防ぐ5f02 J[tiを下敷とする
必要がある。また、PSG膜は潮解性が大きいために、
表面のホトレジストの密着性が劣悪であシ、キャップ層
としての5I02膜を被着させなければならない。
When a guard ring is formed by thermal diffusion of zinc (Zn) to form a Ge p+n type light receiving element,
A non-doped silicon oxide film (8i02 film) does not function as a mask and allows Zn to pass through, so a silicon oxide film (PSG film) containing 5 mo1% or more of phosphorus must be used as a diffusion mask. Must be. However, since this P acts as an n-type impurity for Ge, it is necessary to use 5f02 J[ti as an underlay to prevent P diffusion. In addition, since the PSG film is highly deliquescent,
The adhesion of the photoresist on the surface is poor, and a 5I02 film must be deposited as a cap layer.

従来工程では第1図に示す通シネ鈍物濃度1×10”/
cm3 程度のn型Ge基板1の上に1500λのの5
in2膜4を(a)図の様に全面に被着形成する。
In the conventional process, the concentration of through-cinene blunt material is 1×10”/
5 of 1500λ on an n-type Ge substrate 1 of about cm3
An in2 film 4 is deposited on the entire surface as shown in (a).

次に、この3層膜2,3.4を(b)図の様にパターニ
ングしZnの封管拡散を行い、ガードリングとなるZn
拡散領域5を形成する。次に3層膜2,3゜4をエツチ
ングで取シ去)、新たにチャネルストッパ選択マスク用
のSiO2膜6を被着形成する((C)図)。8402
膜6をパターニングした後、砒素(As)のイオン注入
あるいは熱拡散により (dJ図のn型領域7が形成さ
れる。その後、8i02膜6を除去して受光領域形成の
ためのホトレジスト8をGe表面に直接塗布しく(e)
図)、これをリソグラフィによりパターニングしてホウ
素(ハ)のイオンを打ち込みP+m領域9を形成する(
(f)図)。イオン注入領域の活性化のためにホトレジ
スト8を除去し。
Next, the three-layer film 2, 3.4 is patterned as shown in (b), and Zn is diffused in a sealed tube to form a Zn guard ring.
A diffusion region 5 is formed. Next, the three-layer films 2, 3 and 4 are removed by etching), and a new SiO2 film 6 for a channel stopper selection mask is deposited (FIG. (C)). 8402
After patterning the film 6, an n-type region 7 in the dJ diagram is formed by ion implantation or thermal diffusion of arsenic (As).Then, the 8i02 film 6 is removed and a photoresist 8 for forming a light-receiving region is formed using Ge. Apply directly to the surface (e)
), this is patterned by lithography and boron (III) ions are implanted to form a P+m region 9 (
(f) Figure). Photoresist 8 is removed to activate the ion implantation region.

5io2膜10を被着形成しこれをキャップとして熱処
理を行う((g)図)。熱処理キャップとした8i02
膜10には不純物が混入するためコンタクトマスク用の
5in2膜11はキャップであった膜10を除去して新
たに形成する((h)図)。この8i02膜11をパタ
ーニングしてP型領域9の一部と接触するようにアルミ
ニウム(Al)電極12を形成して、受光素子の表面加
工を完了するわけである((ill)。従って、従来工
程に於ては最終的なpn接合の表面露呈部分、即ち、ガ
ードリンク5の外周部は、全工程通じて5回の被膜被着
、4回の被膜除去を繰)返すことになりAsd拡散によ
シ導入するとすれば3回の熱処理を受けることになる。
A 5io2 film 10 is deposited and heat treated using this as a cap (Figure (g)). 8i02 with heat treated cap
Since impurities are mixed into the film 10, a 5in2 film 11 for a contact mask is newly formed by removing the film 10 which was a cap (FIG. (h)). This 8i02 film 11 is patterned to form an aluminum (Al) electrode 12 in contact with a part of the P-type region 9, and the surface processing of the light receiving element is completed ((ill). In the process, the surface exposed part of the final pn junction, that is, the outer periphery of the guard link 5, is coated five times and removed four times throughout the entire process, resulting in Asd diffusion. If it were to be introduced, it would have to undergo heat treatment three times.

前にも述べた通シ、熱処理の回数およびpn接合が表面
に露呈する回数の多いことが暗電流の増大につながるこ
とであハ暗電流を低減させるにはこれらの回数を出来る
だけ少なくしなければならない。
As mentioned earlier, the number of times of heat treatment and the number of times that the pn junction is exposed to the surface lead to an increase in dark current, and in order to reduce dark current, these times must be reduced as much as possible. Must be.

本発明をGeの受光素子の製造工程に実施した例を第2
図に示す。即ち、本実施例に於ては従来方法のようVC
3層1i2,3.4を一度に成長させず、5in2膜2
のみをn型Ge基板1の上に形成した((a)図)後、
これをチャネルストッパ用選択マスクのパターニングを
して((b)図)、この上に、PEG膜3,5io2膜
4を全面に被着形成する((CJ図)。
A second example of implementing the present invention in the manufacturing process of a Ge photodetector is shown in the second example.
As shown in the figure. That is, in this embodiment, unlike the conventional method, the VC
5in2 film 2 without growing 3 layers 1i2, 3.4 at once
After forming only on the n-type Ge substrate 1 (Figure (a)),
This is patterned into a channel stopper selection mask ((b) figure), and the PEG film 3, 5io2 film 4 is deposited on the entire surface ((CJ figure)).

この状態の3層膜2,3.4を(d)図のようにノ(タ
ーニングしてZnの封止拡散を行うとp型のZnwli
領域5が従来と同様に形成されると同時に、5io22
のパターニングによシP8G膜3がGe基板1に接触し
ている箇所ではPSGSaO2に含まれるPが熱拡散さ
れ、n型のP拡散領域21が形成されることになる。以
下3層膜2,3.4を除去してホトレジスト8′5r:
塗布する工程((e)図)からは従来方法と全く同じで
アシ、従って本発明による製造方法ではガードリング5
の外周部は全工程で4回の被膜被着、3回の被膜除去、
2回の熱処理を受けるのみで済むこととなる。これは従
来方法に比べて各1回ずつ少ない回数であシs J”l
’ち、ガードリングとチャネルストッパの画領域を同時
に形成する分だけ工程を簡素化でき暗電流を低減するこ
とができる。
When the three-layer film 2, 3.4 in this state is turned and sealed and diffused with Zn as shown in (d), it becomes p-type Znwli.
At the same time as region 5 is formed in the same manner as before, 5io22
By this patterning, P contained in PSGSaO2 is thermally diffused at the locations where the P8G film 3 is in contact with the Ge substrate 1, and an n-type P diffusion region 21 is formed. The following three-layer film 2, 3.4 is removed and photoresist 8'5r:
The coating process (Figure (e)) is completely the same as the conventional method, so the guard ring 5 is
The outer periphery of the film is coated 4 times and removed 3 times in the entire process.
Only two heat treatments are required. This is one fewer number of times than the conventional method.
Furthermore, since the guard ring and channel stopper image areas are formed simultaneously, the process can be simplified and dark current can be reduced.

上記実施例ではGeのn型基板上にp+−n型素子を作
成する際の製造工程に関して説明したが、p型基板を用
いた場合でも、また、i−v族化合物の受光素子を用い
た場合でも全く同様の効果があることは言うまでもない
In the above example, the manufacturing process for creating a p+-n type element on a Ge n-type substrate was explained, but even if a p-type substrate is used, it is also possible to Needless to say, the same effect can be obtained in both cases.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜0)はGe受光素子の従来の製造工程の
一例を示した断面図であシ、第2図(a)〜(e)は本
発明をGe受光素子の製造工程に適用した一実施例であ
る。尚、第2図(e)よシ以後は第1図(e)より(i
)までの領域7が領域21となるのみでその他は同一な
ため省略した。 図中に於て、1はn[Ge基板、2は5i02jli)
、3はP S G膜、4は5in2膜、5はp型を示す
Zn拡散領域、6は8i02膜、7はn型を示すAs注
入領域、8はホトレジスト、口はp+型を示すB注入領
域、10はSiO2膜、11は5in2膜、12はAJ
電極、21はn型を示すP拡散領域を表わす。 第1図 第1図 第2図 「−]「□−−
FIGS. 1(a) to 0) are cross-sectional views showing an example of the conventional manufacturing process of a Ge photodetector, and FIGS. 2(a) to (e) show the present invention in the manufacturing process of a Ge photodetector. This is an example of application. In addition, from FIG. 2(e) onward, from FIG. 1(e), (i
) up to area 7 becomes area 21, and the rest are the same, so they are omitted. In the figure, 1 is n[Ge substrate, 2 is 5i02jli)
, 3 is a PSG film, 4 is a 5in2 film, 5 is a Zn diffusion region indicating p-type, 6 is an 8i02 film, 7 is an As implantation region indicating n-type, 8 is photoresist, and the opening is B implantation indicating p+ type. area, 10 is SiO2 film, 11 is 5in2 film, 12 is AJ
The electrode 21 represents a P diffusion region exhibiting n-type. Figure 1 Figure 1 Figure 2 “-” “□--

Claims (1)

【特許請求の範囲】 1、第1の導電型を示す結晶表面に該導電型と逆の第2
の導電型不純物を導入してPN接合を形成する受光素子
の製造方法において、第2の導電型不純物を拡散してガ
ードリングを形成する際の選択マスクとして、不純物を
含まない第1の誘電体膜と、第1の導電型を示す不純物
を含む第2の誘電体膜の2層膜を用い、かつ第2の誘電
体膜の被着形成に先立ちガードリング外縁より外側にあ
たる第1の誘電体膜の所望部分をエツチングによシ除去
しておき、かつ、該ガードリング形成のだめの拡散工程
で該エツチング部分の結晶表面に第2の誘電体膜中の第
1の導電型不純物が同時に選択拡散されることを特徴と
する受光素子の製造方法。 2、特許請求範囲第1項による製造方法において、2層
誘電体膜上に不純物を含まない第3の誘電体膜を被着形
成し、3層膜とすることを特徴とする受光素子の製造方
法。
[Claims] 1. A crystal surface exhibiting a first conductivity type has a second conductivity type opposite to the first conductivity type.
In a method for manufacturing a light receiving element in which a PN junction is formed by introducing an impurity of a conductivity type, a first dielectric material containing no impurity is used as a selection mask when forming a guard ring by diffusing an impurity of a second conductivity type. A two-layer film of a film and a second dielectric film containing an impurity exhibiting the first conductivity type is used, and prior to depositing the second dielectric film, the first dielectric film is placed outside the outer edge of the guard ring. A desired portion of the film is removed by etching, and in the final diffusion step for forming the guard ring, the impurity of the first conductivity type in the second dielectric film is simultaneously selectively diffused onto the crystal surface of the etched portion. A method of manufacturing a light receiving element, characterized in that: 2. In the manufacturing method according to claim 1, a third dielectric film containing no impurities is deposited on the two-layer dielectric film to form a three-layer film. Method.
JP58167780A 1983-09-12 1983-09-12 Manufacture of light receiving element Pending JPS6058683A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58167780A JPS6058683A (en) 1983-09-12 1983-09-12 Manufacture of light receiving element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58167780A JPS6058683A (en) 1983-09-12 1983-09-12 Manufacture of light receiving element

Publications (1)

Publication Number Publication Date
JPS6058683A true JPS6058683A (en) 1985-04-04

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP58167780A Pending JPS6058683A (en) 1983-09-12 1983-09-12 Manufacture of light receiving element

Country Status (1)

Country Link
JP (1) JPS6058683A (en)

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