JPS6058645A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPS6058645A
JPS6058645A JP58167741A JP16774183A JPS6058645A JP S6058645 A JPS6058645 A JP S6058645A JP 58167741 A JP58167741 A JP 58167741A JP 16774183 A JP16774183 A JP 16774183A JP S6058645 A JPS6058645 A JP S6058645A
Authority
JP
Japan
Prior art keywords
metal
semiconductor element
substrate
electrode
projections
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58167741A
Other languages
English (en)
Japanese (ja)
Other versions
JPS644341B2 (enrdf_load_stackoverflow
Inventor
Kenzo Hatada
畑田　賢造
Minoru Hirai
平井　稔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP58167741A priority Critical patent/JPS6058645A/ja
Publication of JPS6058645A publication Critical patent/JPS6058645A/ja
Publication of JPS644341B2 publication Critical patent/JPS644341B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
JP58167741A 1983-09-12 1983-09-12 半導体装置の製造方法 Granted JPS6058645A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58167741A JPS6058645A (ja) 1983-09-12 1983-09-12 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58167741A JPS6058645A (ja) 1983-09-12 1983-09-12 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS6058645A true JPS6058645A (ja) 1985-04-04
JPS644341B2 JPS644341B2 (enrdf_load_stackoverflow) 1989-01-25

Family

ID=15855253

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58167741A Granted JPS6058645A (ja) 1983-09-12 1983-09-12 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS6058645A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5081520A (en) * 1989-05-16 1992-01-14 Minolta Camera Kabushiki Kaisha Chip mounting substrate having an integral molded projection and conductive pattern

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4869471A (enrdf_load_stackoverflow) * 1971-12-22 1973-09-20

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4869471A (enrdf_load_stackoverflow) * 1971-12-22 1973-09-20

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5081520A (en) * 1989-05-16 1992-01-14 Minolta Camera Kabushiki Kaisha Chip mounting substrate having an integral molded projection and conductive pattern

Also Published As

Publication number Publication date
JPS644341B2 (enrdf_load_stackoverflow) 1989-01-25

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