JPS605637A - Spread spectrum communication system - Google Patents

Abstract

PURPOSE:To enable demodulation of a high-speed data signal by selecting the maximum output from a group of correlating circuits which is in charge of a weight corresponding to the phases of plural false random noise PN code strings of different phases a coefficient and restoring said output. CONSTITUTION:The transmitting side forms a signal from a PN code generating circuit 3 and plural PN codes of different phases by a PN code forming circuit 4. A multiplexer circuit 8 selects a PN code of phase corresponding to information data d(t) from the circuit 4 and set it as a code string SP and modulates 14 a carrier wave by this code string and transmits as a signal S(t). The receiving side demodulates 20 the signal S(t) and inputs to correlation circuits 22, 23. The circuits 22, 23 outputs signals SH, SI by setting the weight corresponding to the phase of PN code selected by the transmitting side as a coefficient. The maximum output is selected by comparators 24, 25 and an exclusive OR circuit 38 from the signals SH, SI at the time of specified sampling timing and inputted to a shift register circuit 28. The circuit 28 restores information data d(t) from the phase of the selected PN code.

Description

[Detailed description of the invention] <Field of invention> The present invention relates to a spread spectrum communication system.

<Prior art and its problems> The spread spectrum communication system is a system that uses signals spread over a much wider frequency band than the minimum necessary band to transmit the information to be sent out. This spread spectrum signal as a transmission signal converts the data signal into d(t
) (value is →-1 or -1 binary time series signal), PN
(Pseudorandom noise) If the code is P(t) (the value is a binary code of +1 or -1) and the carrier is cosωc1,
It is given by the following formula.

B (t) = eL (t) ・P (t) −co
s ωct However, ωC-2πfC1fC is the carrier frequency, and on the receiving side, this spread spectrum signal S (t)
is received as a received signal, and from this data signal a (t
) is demodulated. For this demodulation, in the conventional method, the first
As shown in the figure, the received signal 5(t) is mixed with the regenerated carrier wave COSωctwo by a mixer a, and the components of tl (t) and P (t) are extracted by a low-pass filter b, and this signal d (t)・p (t) and the same type of PN code as on the transmitting side is performed by a correlation circuit C, and by giving the output signal sA of this correlation circuit C to the sample circuit d, the data signal eL ( t). By the way, the output signal SA of the correlation circuit C is shown in FIG.
), it has sharp peaks on the positive and negative sides. If this output signal SA is sampled at a sample timing near the center of its peak as shown in Fig. 2(b), Fig.
The data signal tl (t) is demodulated as shown in C).

For such demodulation, one period of the PNN code (t) must correspond to one bit of the data signal. However, in this demodulation, if the number of bits in one period of the I)N code is N, the S/N ratio is improved by 10 logN. By the way, since there are N bits of PN code in one bit of the data signal, the input signal a to the correlation circuit C
(t)・P (t) communication speed is NX (data speed)
bps. Therefore, if the S/N ratio improvement is the same, the communication speed of this input signal d(1)·p(t) is proportional to the data speed.

On the other hand, there is a limit to the operating speed of the correlation circuit C. Therefore, when the data speed If becomes high and the speed of the input signals a (t) and p (t) to the correlation circuit C increases beyond the above-mentioned limit, the data signal cannot be restored. becomes impossible.

OBJECTS OF THE INVENTION It is an object of the present invention to make it possible to demodulate data signals even at higher data rates.

<Structure and Effects of the Invention> In order to achieve the above object, the present invention has a PN code generation circuit and a PN code generation circuit that repeatedly distributes PN codes of different phases to the transmitting side in a spread spectrum communication system. P of the phase corresponding to the circuit to be formed and the information data
A multiplexer circuit that selects and outputs the NN code from the output of the PN code forming circuit is provided, and the receiving side includes a group of correlation circuits whose coefficients are weighted according to the phase of the PN code that can be selected on the transmitting side, and a predetermined sample. A selection circuit that selects a correlation circuit for determining the maximum output from the group of correlation circuits at a timing, and a restoration circuit that restores information data from the phase of the selected PN code are provided. Therefore, according to the present invention, even if the communication speed of the input signal to the correlation circuit increases in proportion to the data speed I, data can be restored without exceeding the operating speed limit of the correlation circuit. can.

<Description of Examples> First, before entering into a detailed description of the present invention, the principle of the present invention will be explained with reference to FIG. 3. Information/) Recorder 2
The bit combination is “00” [OIJ [10Jr
There are four ways. Figure 3 (a) corresponds to each combination.
) Consider a PN code string of the 4ai class. The upper bit of the information data changes the phase of the PN code by 1 bit, and the lower bit reverses the PN hunting code.

Then, the first combination "00" of 2 bits of '11'j 4 data is pN:, p,..., the first P N g column of PN-1, dust, and the second combination 101
” is the second PN code string of PN, P, . . . , PN-1, and the third combination “10” is p, , p2 .
..., the 3rd PN I'2 column of PN-1, 8134
0 combination "11j Th, jPI+"21...
+ is the fourth PN code string of PN. Therefore, when transmitting "1= o o 011011" as information data, the 1st, 2nd, . Third. Since this is the fourth combination, each PN code string has the first . Second. The order of 3rd 8A4 is different. On the transmitting side, this PN code string is modulated and transmitted.

On the other hand, two correlation circuits are provided on the receiving side, and each correlation circuit has a weight depending on the phase of the PN code selected on the transmitting side. For example, in one phase circuit A, O,
P,,L? 2. , PH-1, and the other correlation circuit B has a weight of O, P2 . ..., has a weight of PN.

Then, as shown in FIG. 3(c), the peaks of the correlation outputs of the correlation circuits A and B are shifted by 1 bit. Therefore, depending on the sign of the peak at the sampling timing of each cycle of the PN number and whether the correlation circuit in which the peak is detected is A or B, it is possible to distinguish between the four types. This distinction allows information data to be restored.

Such an approach allows doubling the data rate without increasing the PN code rate. Of course, the same method can be used to restore data even if the data rate is tripled or quadrupled.

The present invention is based on this principle, and allows information data to be restored even if the data speed of group I increases. Hereinafter, the present invention will be explained in detail based on the embodiments shown in FIGS. 4 to 1.

FIG. 4 is a circuit diagram of the transmitting side in the spread spectrum communication system according to this embodiment, and FIG. 5 is a time chart of signals at each part of the circuit.

In FIG. 4, reference numeral 1 denotes an oscillation circuit that oscillates at a frequency N times the communication speed of the tt'i' information data. Here, N is the number of bits in one cycle of the PN code (pseudorandom noise code). The outputs i and j of the oscillation circuit 1 are divided into four by a binary counter 2. The output of binary counter 2 is PN as a clock.
The signal is applied to the code generation circuit 3.

The PN code generation circuit 3 periodically generates a PN code as shown in FIG. 5(a) in response to this clock.

The output of the PN code generating circuit 3 is applied to the input terminal of the flip-flop 5 of the PN code forming circuit 4. P'N
The code forming circuit 4 includes a @1 sieve flip-flop 5 and two NOT circuits 6 and 7. The PN code forming circuit 4 has four output terminals 4a+4b, 4c, and 4d. 1st
For the output terminal 4a, change the sign of the PN code in Fig. 5(a) to N.
The OT circuit 6 outputs an inverted PN code. The PN code shown in FIG. 5(a) is output as is from the second output terminal 4b. From the third output terminal 4C, the
) is delayed by one bit by a flip-flop 5 and further inverted by a NOT circuit 7 to output a PN code. From the fourth output terminal 4d, Fig. 5(a)
A PN code obtained by delaying the PN code by 1 bit by a 7-lip flop 5 is output.

Therefore, the PN code string from the third output terminal 4C is the first PN code string when the information data bit is "00".
The second PN code string from the fourth output terminal 4d is the information data bits 1-01, and the second PN code string from the first output terminal 4a is the information data bits 1-01.
'', the PN code string from the second output terminal 4b is the information data bit, or the fourth PN code string when the bit is "11" is output.

The multiplexer circuit 8 includes the first to
8+! The first to fourth output terminals correspond individually to the four output terminals 4a to 4d.
It has fourth input terminals MU a and 3 d. The multiplexer circuit 8 selects the PN code from the valley output terminals 4a to 4d according to a signal SH, which will be described later, and outputs the selected output terminal C.
4a to 4d] is output as the output signal SF.

On the other hand, the output of the oscillation circuit 1 is frequency-divided by 4 by an N-ary counter 9. Output signal Sc of N-ary counter 9 (Fig. 5(C)
]i, j, are given to the binary counter 10, and the first . i'j;2 is also given as a clock signal to flip-flops 11 and 12. First flip-flop 110
At the input terminal, the information data is No. 1 So (Fig. 5(b)
] or given. This information data signal SB is delayed by the first flip-flop 11, and then is delayed by the launch circuit 13.
One input stream of . Ox octopus signal SB
is delayed by the first flip-flop 11 and further delayed by the second flip-flop 12, and then applied to the other input terminal of the latch circuit 13.

Since the launch timing of the latch circuit 13 is controlled by the output signal SD of the binary counter 10 [FIG. 5(d)], both output terminals Q of the latch circuit 13.

For Q, jJ l+ 2nd Furinogfurosop 11.12
A signal SE of 2 bits of the data signal sB, which is the output of the data signal sB, is generated as shown in FIG. 5(e). The multiplexer circuit 8 selects the PN code forming circuit 4 according to the contents of the signal SE.
The output terminals 4a to 4d are selected and switched. By switching the multiplexer circuit 8, a signal SF of a PN code string as shown in FIG. 5(f) is output. This signal Sr, is mixed with a carrier wave cosωct by a mixer 14, and then transmitted from a transmission antenna (not shown) as a transmission signal 5(1).

FIG. 6 is a circuit diagram of the receiver (F, i circuit) of this embodiment,
FIG. 7 is a time chart of the signals of each fib in the circuit. A received signal S (t) l-j received by a receiving antenna (not shown) is mixed with a reproduced carrier wave by a mixer 20 and then input to a low-pass filter 21 .

In this way, the received signal S (t) is filtered through the low-pass filter 21
The low frequency components shown in Figure 7(a) are collapsed from 4.
, a +5B G. This signal SG is the first signal. It is applied to the second correlation circuit 22,23. 1st. The second correlation circuits 22 and 23 each have an analog shift register 2
2a, 23a, and PN code registers 22b, 23b,
"product first" circuits 22C and 23C. Each product-sum circuit 22
C and 23C are composed of a plurality of mixers (indicated by ■ in the figure) and a synthesizer (indicated by ■ in the figure) corresponding to each bit of each register 22a+23a. 1st. Second correlation circuit 2
2.23 are O, P, respectively, as explained in FIG. 3(C).

... The weight of PN-1, O, P2. . 1st. Output signal 13H of second correlation circuit 22.23
, Sl are shown in FIGS. 7(b) and 7(c), respectively.

One output signal SR is the first. Second comparison circuit 24°25
The other output signal S+ is applied to each positive phase side input section of the first comparison circuit 24 and the multiplier 26 . The other output signal s given to the multiplier 26
l is multiplied by -1 and then applied to the negative phase side input section - of the second comparison circuit 25. In the first comparison circuit 24, the power signals SH and S1 are compared in magnitude, and as a result, the first comparison circuit 24 outputs a signal SM shown in FIG. 7(g). Also, in the second comparison circuit 25, one output signal 19H and the output of the multiplier 26 are compared, and as a result, the output signal from the second comparison circuit 25 is shown in FIG. 7(h). The lower bit of the 2-bit combination of the signal SNc report data is output. The signals sM and sN are input to the exclusive OR circuit 38, and from this OR circuit 3B, the seventh
A signal SO (upper focus of the 2-bit combination of information data) shown in FIG. 1 is output. Therefore, the signals sN and SO are applied in parallel to the shift lens star circuit 2B.

The output signal 81 of the second correlation circuit 23 is transmitted to the third comparison circuit 27.
The magnitude is compared with the threshold level TH, and as a result of this comparison, the third comparison circuit 27 outputs the signal SJ shown in FIG. 7(d). This signal SJ is
It is applied to one input section of the AND circuit 29. At this time, the flip-flop 31 outputs a high-level signal from its output terminal in response to the reset signal received at the reset terminal RKJ, and the signal SJ is also transmitted via the NOT circuit 30 to ! A low level signal is output from the output terminal P when the output terminal SK is input, but when the signal SJ is applied to one input terminal of the A N D circuit 29, the NOT circuit 30 outputs a low level signal from the output terminal P. The timing of applying the signal SJ to S is distorted. During this time, the level of the signal at the other input terminal of the AND circuit 29 is the same as that of the output signal at the output terminal of the flip-flop 31.
Depending on the issue...it's on the wrong level. Therefore, A.N.
A signal SJ shown in FIG. 7(d) is applied to the latch circuit 33 via the D circuit 29. At this time, the latch circuit 33
latches the output signal SK of the ring counter 34 shown in FIG. 7 (θ). When the matching circuit 32 matches the signal between the latch circuit 33 and the counter 34 (/
(, via the OR circuit 39, the signal S shown in FIG. 7(f)
14 as a sample gate signal to the shift register circuit 2.
Give to 8. Each time the sample gate signal St matches the count value of the ring counter 34 or the count value latched by the latch circuit 33,
arises from. The ring counter 34 performs a counting operation using the output obtained by partially rotating the output of the oscillation circuit 1 36 by the binary counter 35 as a clock. This oscillation circuit 36 f
It has an excavation frequency that is N times the same data communication speed as the d transmitter, and this output is divided into 4 by the N-ary counter 37 and becomes 81
As shown in FIG. 47(k), this is provided as a transfer lock for the soft register circuit 28. It's ox, binary b counter 35
0 output I''i is used as a transfer lock for the analog shift registers 22a and 23a of the first and second phase male circuits 22 and 23.

Therefore, the seventh
Figure (h) (i) signals SN and SO, Figure 7 Cf)
By being sample gated by the sample gate signal shown in FIG. 7, both ld signals SN and SO are sampled in the shift register circuit 28 as shown in FIG. In accordance with the lock Sp, a signal SQ as shown in FIG.

In addition, when starting communication, all bits of ``rl'' are transmitted.
It is assumed that

[Brief explanation of drawings]

Fig. 1 (d) is a receiving circuit diagram of a conventional example, Fig. 2 is a time chart of signals of each part, which is used to explain the operation of the receiving circuit shown in Fig. 1;
FIG. 3 is a diagram for explaining the present invention in detail, and 8)!
Figure 3<a) shows a PN code string corresponding to a combination of 2 bits of information data, and Figure 3(b) shows the PN code string of Figure 3(a).
Figure 3 (C) shows a transmission signal according to N code strings.
The peak waveform and lean pull timing of the output of the correlation circuit a on the reception side are shown. 8134 is a transmitting circuit diagram of an embodiment of the present invention, FIG. 5 is a time chart of signals of each part in FIG. 4, FIG. It is a time chart of signals of each part of the figure. 3...PN code generation circuit, 4...PN code formation circuit, d
...Multiplexer circuit, 22.23...1st. 2nd correlation circuit, 24+25...1st. Second comparison circuit, 28...
/Futrenstar circuit. Applicant: Tateishi Electric Co., Ltd. Agent: Kazuhide Okada, patent attorney

Claims (1)

[Claims] (11 PN code generation circuit, a circuit that generates a plurality of types of PN codes with different phases from the PN code generation circuit, and a multiplexer circuit that selects and outputs a PN code with a phase corresponding to information data from the output of the PN code formation circuit) a transmitting circuit including a transmitting circuit, a group of correlation circuits whose coefficients are ζ weights according to the phase of the P A spread spectrum communication system comprising a selection circuit for selecting a correlation circuit, and a reception circuit including a restoration circuit for restoring emotional data from the phase of the selected /ζPN code.