JPH0247911A - Digital matched filter - Google Patents

Abstract

PURPOSE:To supply an always stable signal to an A/D converter even if a disturbing wave having a frequency close to a communication signal frequency is caused and to attain synchronization detection within a prescribed time at all times by giving an output of an LPF to the A/D converter via a capacitor. CONSTITUTION:An output of a local oscillator 2 is multiplied with an input spread spectrum signal at a frequency converter 3 and the resulting signal is fed to a 1-bit A/D converter 5 via an LPF 4 and a capacitor 11. The cut-off frequency by the capacitor 11 is set to a prescribed frequency, the frequency component of a fluctuated bias due to a disturbing wave is eliminated by a low frequency component elimination effect, and the result is fed to the 1-bit A/D converter 5 and a digital code series is stored in a shift register 6. When the sum of a spread code series at the sender side of a shift register 7 and one output from a correlation group where the codes of both the series are made coincident through the processing reaches a maximum value, a synchronizing signal detector 9 discriminates the synchronization of the codes of both the series. Through the constitution above, a stable signal is subject to A/D conversion and the synchronization detection is applied at all times within a prescribed time.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a digital matched filter used in a synchronization acquisition circuit that detects the synchronization timing of a code sequence. [Prior Art] Conventionally, in direct sequence spread spectrum communication systems, etc., in order to detect synchronization timing of code sequences on the receiving side, a shift register is set to the same sequence as the spreading code sequence used on the transmitting side. A digital matched filter is used in the synchronization acquisition circuit, which compares the output code of each bit with the input signal code and detects a correlation value. A conventional digital matched filter is shown in FIG. In the figure, (1) is a signal input terminal, (2) is a local oscillator, (3) is a frequency converter, (4) is a low-pass filter,
(5) is a 1-bit A/D converter, (6) is the first shift register, (7) is the second shift register, (8)
is a correlator composed of a plurality of correlators, (9) is a synchronization signal detector, and Q (l is a detection signal output terminal. Next, the operation will be explained. The spread spectrum signal input to the signal input terminal (1) is Y, (t) m d (t)
Let PN(tl co s(ω1t+θ:).Here, d(

[) is the code string of the sending data, PN(Ll
indicates a spread spectrum code string. Now, for simplicity, d(
Let it be tl -1. Also, the oscillation signal of the local oscillator (2) is Yg(t)■co
Let it be s(ωo1+θ.). A spread spectrum signal input from a signal input terminal (1) is multiplied by a signal from a local oscillator (2) by a frequency converter (3). The output signal of the frequency converter (3) passes through a low-pass filter (4) to remove harmonic components, resulting in Y, (t) m PN (tl
(co8ω6(t)+θ・) (however, ω0−ωl−ω0
．． θe−θl−θ0). FIG. 1 shows a waveform diagram of a spread spectrum signal after passing through a low-pass filter (4) that has been subjected to base-hantney frequency conversion. In the figure, the envelope of the signal is cos (ω.(+θ.)
Ingredients are shown. The above-mentioned spread signal is converted by a 1-bit A/D converter (5) using Y-〇 as a threshold into a digital signal represented by two values of ] or 0, and input to the first shift register (6). do. Now, if the number of stages of the first shift register (6) is n, the digital codes entered in registers l to n are transferred to n correlators (
8). By the way, the second shift register (
7) contains a code set to the same sequence as the spreading code sequence used on the transmitting side, and code information is sent to each of the n correlators (8). The correlators (8) each compare the signs of the first shift register (6) and the second shift register (7), and send out 1 if the signs are the same. Then, the synchronization signal detector (9) adds up the signals from the n correlators (8), and when the sum reaches the maximum, the first... The second shift register (61,
It is assumed that the signs of +71 match, and a synchronization detection signal is sent from the detection signal output terminal σO. If the codes do not match, the first shift register (6) shifts the data by 1 bit and performs synchronization detection again on the new code string. The above operations are repeated until synchronous detection is obtained. [Problems to be Solved by the Invention] In conventional spread spectrum communication using digital matched filters, interference waves often exist within the transmission band.
) and hail. Now, the frequency of the interference wave is very close to the communication signal frequency, ω6〉〉ωj−ω. Then, in the conventional digital matched filter, a component cost(machi-ωo)t+(θj-θ.]) generated by multiplying the interference wave and the local oscillation signal is added to the output signal of the low-pass filter (4). , f, 1st time, so 1 bit
(There is a time when the threshold value of the A/D converter (5) cannot be crossed. During this period, the output signal of the 1-bit A/D converter always sends out 1 or 0, and the spread code data is erroneous. This poses a problem in that the probability that the signs of the first shift register (6) and the second shift register (7) match decreases, and the time required for synchronization detection increases. Even if an interference wave with a frequency close to the communication signal frequency occurs, bias fluctuations in the baseband converted received signal can be eliminated, and the A/D converter input can be stabilized. It is an object of the present invention to provide a digital matched filter that can always perform synchronization detection within a certain period of time using a signal. It is connected to the A/D converter via a capacitor. [Operation] The digital matched filter of this invention has a capacitor connected in series between the low-pass filter and the A/D converter, and serves as a bypass filter. Therefore, the frequency component of the bias fluctuation of the baseband signal due to interference waves is removed, and only the frequency band of the necessary signal can be passed. [Embodiment] Fig. 1 is a diagram showing an embodiment of the present invention. In the figure, (υ~αG are exactly the same as the above conventional circuit, and the east side is a capacitor. Next, the operation will be explained. In the digital matched filter, the spread spectrum signal Y input from the signal input terminal (1) □(1) 舅d(t) PN(t) eos(ω
it+θI) is the signal Y*(tl
Sono cos (ω0

+00) by a frequency converter (3), and passes through a low-pass filter (4) to obtain a baseband signal from which harmonic components have been removed. If interference wave Y3(t)gxcoa(ω1(t)+θi) now exists, the output signal of the low-pass filter (4) will be Y3(
tla PN(tl (cogω5(t) 10,)+c
os(ωj([)+θj), and the waveform becomes as follows: rA>turn. The above baseband signal Y3(t) is input when a capacitor is used, and the cutoff frequency ω of the capacitor. ω. > If the frequency component ωj of the bias fluctuation due to the interference wave is removed by the low frequency component removal effect of the capacitor, Y, (t) z PN (t
) (nos a+*(tl+θ・).The above spread signal is converted into a digital signal by a 1-bit A/D converter (4) using Yo as a threshold value, and then sent to the first shift register (6). ] The digital codes that have entered the first stage of registers are sent to n correlators (3). Also, the codes that are set to the same sequence as the transmitter are sent to the second shift register (7). The correlators (8) each compare the signs of the first shift register (6) and the second shift register (7), and are sent to n correlators (8). In the case of , it sends out 1. Then, the synchronization signal detector (9) adds up the signals from n correlators, and when the sum is maximum, the signs of the first and second shift registers match. The synchronization detection signal is sent from the detection signal output terminal αG.If the signs do not match,
The first shift register (6) shifts the data by 1 bit and performs synchronization detection again for the new code string. The above operations are repeated until a synchronization detection signal is obtained. Note that in Figures 1 and 2, the A/D converter has a 1-bit A/D converter that converts it into a 1-bit digital signal.
Although an example using a D converter has been shown, an A/D converter with 2 or more bits may also be used. [Effects of the Invention] As described above, according to the present invention, since the low-pass filter and the A/D converter are connected through the capacitor, even if interference waves with frequencies close to each other are superimposed on the input signal, This has the effect that synchronization detection can be performed in the same way as when there is no interference wave.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a digital matched filter according to an embodiment of the present invention, and FIGS. 2 and 4 are for explaining the operation of the present invention and the conventional digital matched filter. A diagram showing an A/D converter input signal waveform, and FIG. 3 is a diagram showing a conventional digital matched filter. In the figure, (1) is the signal input terminal, (2) is the local oscillator, (3) is the frequency converter, (4) is the low-pass filter, +51 is the 1-bit A/D converter, and (6) is the first shift register, (7) is the second shift register, (8
) represents n correlators, (9) represents a synchronous signal detector, QG represents a detection signal output terminal, and (11) represents a capacitor. In addition, in FIG. 1, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In a digital matched filter that detects reception synchronization timing from a spread spectrum signal that has been subjected to secondary modulation using a spreading code sequence, a local oscillator that generates a frequency close to the received signal and the signal from the local oscillator are multiplied by the received signal. a frequency converter, a low-pass filter that removes harmonic components from the output signal of the frequency converter, a capacitor that removes bias fluctuation frequency components from the output baseband signal of the low-pass filter, and converts the capacitor output signal into a digital signal. An A/D converter for conversion, a first shift register for inputting the digital code sequence converted by the A/D converter and shifting it bit by bit, and a first shift register set to the same sequence as the spreading code sequence on the transmitting side. 2 shift registers, n correlators that multiply the output of the first shift register and the output of the second shift register bit by bit and send out 1 when the codes match, and the n correlators 1. A digital matched filter comprising a synchronization signal detector that generates a synchronization detection signal when the total of signals from the filter reaches a maximum.