JPH0597145U - Digital correlator - Google Patents

Abstract

(57) [Summary] (Correction) [Purpose] To provide a digital correlator that requires few components. Configuration: A first register 10A on the first correlator side in which a first PN sequence is set, a second register 10B on the second correlator side in which a second PN sequence is set, and reception A shift register 20 common to the first and second correlators to which a signal and a clock are input, and a match / mismatch between the value of each stage of this shift register 20 and the value of the corresponding stage of the first register is detected. And a first adder 30A for adding the output value of each of the matching circuits, the value of each stage of the shift register and the value of the corresponding stage of the second register. Second match circuit group EX for detecting mismatch
It is composed of an OR and a second adder 30B for adding the output value of each matching circuit.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a digital correlator used on the receiving side of spread spectrum communication, which is suitable for communication using a power line as an information transmission line.

[0002]

[Prior Art]

 Since power lines are used in all homes, when viewed as an information transmission medium in homes, they are very effective information transmission media that are highly economical and expandable. Since a wide variety of electric devices such as lights, air conditioners, and TVs are connected, the transmission characteristics of power lines change momentarily depending on the use / non-use of these electric devices (power ON / OFF, etc.). However, for example, in the case of a TV or a device using a switching power supply, the phase characteristic changes rapidly in synchronization with the power supply frequency.

As described above, since the transmission characteristic of the power line is not flat and unstable, there is a problem that it is difficult to transmit high quality data.

As measures against this, for example, the literature “Light line communication (data transmission)”, the second technical report SS TA89-7 (1989), the document “High performance SS power line modem” NEC technical report Vol.42 No9 As described in pp.98-106 (1989), the introduction of the spread spectrum communication method (hereinafter referred to as SS communication method), which is said to be strong against the fluctuation of the transmission line, is being considered.

In this SS communication method, a code modification method is used for transmitting data, in which a PN (Pseudo Nois) sequence is inverted each time a transition from 1 to 0 or 0 to 1 occurs, and a received signal is transmitted. In order to demodulate, the same sequence as the PN sequence used on the transmission side must be generated on the receiver side. Therefore, the correlation between the received signal and the received PN sequence generated in the receiver is monitored, and the synchronization acquisition (synchronization detection) is performed depending on whether or not the correlation value exceeds a certain threshold value. After capturing, synchronization is maintained (synchronization tracking) to maintain synchronization. After the synchronization is established, if the correlation value is on the + side with respect to the threshold value, it is demodulated as a logic “1”, and if it is on the − side, a logic “0” is demodulated.

A digital correlator for obtaining the above correlation value is disclosed in Japanese Patent Application No. 2-246542. FIG. 4 shows this correlator. In the figure, reference numeral 10A denotes a k-stage register for setting a PN code, in which Manchester-encoded M-sequence code PN0 is stored in advance. Reference numeral 20A denotes a k-stage shift register to which a signal obtained by digitizing the received signal is input and is shifted by clock c every clock. Corresponding stages of the stages 1 _{R to} k _{R of the} register 10A and the stages 1 _{SR to} k _SR of the shift register 20 A are connected to coincidence circuits (in this example, exclusive OR circuits) EXOR1 _{A to} K _A. The outputs of the exclusive OR circuits EXOR1 _{A to} K _A are input to the adder 30A. 10A, 20A, EXOR1 _A ~K _A and 30A constitute a correlator 100A for PN0. Further, 10B is k-register for PN code setting, 20B is k-stage shift register, EXOR1 _B ~K _B coincidence circuit, 30B are a summer, we constitute a correlator 100B for PN1, Les In the register 10B, a sequence PN1 in which the phase of the Manchester-encoded M sequence PN0 is shifted by one chip or more is set.

[0007]

[Problems to be solved by the device]

 Since this conventional digital correlator requires the correlators 100A and 100B having exactly the same configuration, there is a problem that the number of constituent parts increases.

The present invention has been made to solve the above problem, and an object of the present invention is to provide a digital correlator that requires fewer components than the conventional ones.

[0009]

[Means for Solving the Problems]

 In order to achieve the above object, the present invention is used in claim 1 on the receiving side of spread spectrum communication in which transmission data is code-modulated with a PN sequence for communication, and the correlation between a received signal and a first PN sequence is used. A digital correlator comprising a first correlator that outputs a value and a second correlator that outputs a correlation value between the second PN sequence and the received signal, the second PN sequence having a predetermined phase shift with respect to the PN sequence, A first register for setting a PN code on the side of the first correlator in which a first PN sequence is set, and a PN code for setting the side of the second correlator in which a second PN sequence is set Second register, a shift register common to the first and second correlators to which the received signal and the clock are input, a value of each stage of the shift register and a corresponding stage of the first register. To detect a match / mismatch with the value of Match circuit group and the first adder for adding the output values of each match circuit, and the match / mismatch between the value of each stage of the shift register and the value of the corresponding stage of the second register is detected. The configuration is made up of a second matching circuit group and a second adder that adds the output values of the matching circuits.

In the second aspect, the first correlator and the second correlator share one PN code setting register.

[0011]

[Action]

 In the present invention, since the shift register or the shift register and the register for setting the PN code are shared by the first correlator side and the second correlator side, the number of components is reduced.

[0012]

【Example】

 An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, the shift register 20 is shared by the PN0 correlator 100A and the PN0 correlator 100B. The output of each stage 1 _SR to k _SR of the shift register 20 is input to the EXOR1 _A ~EXO RK _A capturing output of a corresponding stage 1 _R to k _R of the register 10A, the register 10B corresponding stage 1 _R ~ It is input to EXOR1 _B to EXORK _B that take in the output of k _R.

Therefore, in this embodiment, one PN code setting register can be omitted.

FIG. 2 shows another embodiment of the present invention, in which not only the shift register 20 for setting the PN code but also the register 10 is shared. The received signal is transmitted, for example, from the transmitter shown in FIG. 3 through the transmission path.

In FIG. 3, reference numeral 1 is a 5-stage shift register, and 2 is an EXOR gate, which together constitute a first PN sequence generator 3. The EXOR gate 2 inputs the output of a specific stage of the shift register 1, and the output of the EXOR gate 2 is fed back to the input of the shift register 1. In this embodiment, the output of the shift register 1 is input to the shift register 1. A value other than "00000" is set as the initial value so that an M-sequence code with a code length of 31 is obtained. The output of the PN sequence generator 3 is PNO. It is assumed that the clock speed of the clock c supplied to the PN sequence generator 3 is much faster than the data transmission speed. Reference numeral 4 denotes a second PN sequence generator, which is composed of a delay unit consisting of a 15-stage shift register, receives the output of the PN sequence generator 3, and has the same clock c as the clock c given to the PN sequence generator 3. It is driven by c and generates a PN sequence (PN1) delayed in phase from PN0 by 15 chips. Reference numeral 5 denotes a timing signal generator, which is composed of an AND gate, takes AND of outputs of all stages of the shift register 1, and outputs PT of the AND gate 5 (a signal representing one cycle of the M sequence code). It serves as a timing signal PT for synchronizing the transmission data D with the PNO and PNS. Reference numeral 6 denotes a selector, which selects PN1 when the logic is 1 for 1 bit of the transmission data D and PN1 when the logic is 0 and sends the SS signal. Is band-limited (10 KHz to 450 KHz in the case of a power line) by a low-pass filter LFP7, amplified by a transmission amplifier (not shown) to a predetermined level, and then sent out to a transmission line via a coupler (not shown). .

[0017]

[Effect of the device]

 As described above, according to the present invention, the shift register for receiving the received signal or the shift register and the register for setting the PN code are shared by the first correlator side and the second correlator side. Fewer components required.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

FIG. 3 is a block diagram showing an example of a transmission unit used in SS communication.

FIG. 4 is a block diagram showing an example of a conventional digital correlator.

[Explanation of symbols]

 1 shift register 2 EXOR gate 2A, 2B, 2C EXOR gate 3 first PN sequence generator 4 delay device which is a second PN sequence generator 5 timing signal generator 6, 16-selector 7 LPF 10 Power line which is a transmission line 10, 10A, 10B PN code setting register 20 Shift register 30A, 30B Adder 100A, 100B Correlator

Claims (2)

[Scope of utility model registration request] 1. A first correlator, which is used on the receiving side of spread spectrum communication in which transmission data is code-modulated with a PN sequence and is used for outputting a correlation value between a received signal and a first PN sequence. , A second P shifted by a predetermined phase from the PN sequence
A digital correlator comprising an N sequence and a second correlator that outputs a correlation value between the received signal and a first PN code setting PN code setting side on which the first PN sequence is set. 1 register and a second register for setting a PN code on the second correlator side where a second PN sequence is set,
A shift register common to the first and second correlators to which the received signal and a clock are input, and a match / mismatch between the value of each stage of the shift register and the value of the corresponding stage of the first register Of the second coincidence circuit group for detecting the coincidence of the output values of the coincidence circuits, the value of each stage of the shift register and the value of the corresponding stage of the second register A digital correlator comprising a second matching circuit group for detecting a mismatch and a second adder for adding output values of the matching circuits. 2. The digital correlator according to claim 1, wherein the PN code setting register is shared by the first correlator and the second correlator.