JPS5974741A - Digital data transmitting system - Google Patents

Abstract

PURPOSE:To realize discrimination of plural channels and at the same time to simplify a constitution, by adding a pilot signal to the channel and detecting the presence of the pilot signal at the demodulation side. CONSTITUTION:An L channel signal of an input terminal 1 of the output side is added with a pilot signal to a digital modulator 3 through an adder 6; while an R channel signal of an input terminal 2 is supplied to a modulator 4 respectively. These channel signals are sampled through a terminal 7 and the clock signal of an inverter 8 and extracted at the output sides of modulators 3 and 4, respectively. These signals are switched by a switching circuit 9, and the series signals of L and R channel signals arrayed alternately are delivered to an output terminal 10. Then these signals are supplied to demodulators 12 and 14 at the reception side. A signal obtained by giving 1/2 division to a clock signal of the transmission side is applied to a terminal 18, and the clock signal is supplied to an FF circuit 19. Then the clock signals supplied from an output terminal and an anti-output terminal are supplied to demodulators 13 and 12 respectively. Based on these clock signals, the demodulators 12 and 13 deliver L and R channel signals to output terminal 16 and 17 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital data transmission system, and particularly to a digital data transmission system suitable for transmitting multiple channels of digital data.

BACKGROUND TECHNOLOGY AND PROBLEMS Conventionally, when transmitting digital data, a synchronization signal is transmitted at the same time as the digital data -L2 * L3
When transmitting °', ', : >, R
2+ R3・O has disadvantages such as being expensive.

Summary of the Invention In this invention, a pilot signal is added to at least one of a plurality of channels for transmission, the demodulation side detects the presence or absence of the pilot signal, and each channel is identified based on this detection output. Therefore, various embodiments of the present invention will be described in detail with reference to FIGS. 2 to 12.

2 to 7 show a first embodiment of the present invention, and this embodiment is an example of transmission of a two-channel signal such as a stereo signal. First, Figure 2 shows the circuit configuration on the transmitting side.
) and (2) are supplied with, for example, an L channel signal and an R channel signal, which are audio information 1'lfi, respectively. And these signals are each passed through a delta modulator (3)
and (4), and for one of these signals, for example, the L channel signal, a pilot signal for channel identification is supplied to the pilot generation circuit (
5) The input terminal (1) is generated by the adder (6).
' is added to the L channel signal from '. Furthermore, this JJ?
For example, as shown in FIG. 3, the Ilot signal is added in such a way that it has a spectrum in which, for example, a sine wave-like signal S, - is present at a position slightly apart from the band of the audio signal Sa. . In addition, ・Yairotto signal S
p may be located within the band of the audio signal Sa.

(7) is a clock input terminal to which a sampling clock signal is supplied, and the clock signal from this terminal (7) is directly supplied to the delta modulator (3) and is inverted by the inverter (8). It is then fed to the delta modulator (4). The clock signal from the terminal (7) is also supplied for switching to a switch circuit (9) which switches the outputs of the delta modulators (3) and (4). In addition, this switch circuit (9) is connected to the contact a side when the clock signal is at a low level (L), and is switched to the contact side when the clock signal is at a high level (i). being done. And this switch circuit (9)
Output terminal θQ is taken out from the output side of.

Next, the operation of the circuit shown in FIG. 2 will be explained with reference to the signal waveforms shown in FIG. Now, when the j5L channel signal is supplied to the input terminal (1), this signal is added to the noilot signal from the noilot generation circuit (5) in the adder (6) and is then supplied to the delta modulator (3). On the other hand, the R channel signal from the input terminal (2) is supplied as is to the delta modulator (4). and a delta modulator (
The signal fed to the delta modulator (4) is modulated by the lock signal as shown in FIG. 4A fed from the terminal (7), while the signal fed to the delta modulator (4) is
7) The other clock signal is sampled by the lock signal as shown in FIG. 4B, which is inverted by the invanitor (8). Therefore, L channel signals and R channel signals as shown in FIG. 4C and D are taken out from the output sides of delta modulators (3) and (4), respectively. These signals are then sent to the terminal (7) in the switch circuit (9).
) is sequentially switched by the lock signal as shown in FIG. The L channel signal is taken out, while when the clock signal is at high level, the switch circuit (9)
is switched to the contact side, so the R channel signal is taken out to its output side. Therefore, a serial signal in which L channel signals and R channel signals are alternately arranged as shown in FIG. 4E is taken out from the output terminal (10).

FIG. 5 shows an example of the circuit configuration on the receiving side of this embodiment. In the figure, 0 is an input terminal to which the transmitted signal processed as described above is supplied, and this input terminal 0 The signals from the delta al! AV equipment θ and α
supplied to the field. The signals modulated by the delta demodulators 0 and 01 have unnecessary components such as the pilot signal and harmonic components removed by the low-pass p-wave generators α and αυ, respectively, and then are sent to the output terminals oQ and α, respectively. The signal is extracted as an L channel signal and an R channel signal.

0 → is the same Jut L as the clock signal on the transmitting side, although it is not shown in the figure.
It is assumed here that the clock input terminal is supplied with a regenerated clock signal, and here, for example, a clock signal whose frequency is divided by the clock signal used on the transmitting side is supplied. The clock signal from this terminal M is supplied to a frequency dividing means, such as a D-type flip f70 circuit α, and the output signal from the inverted output terminal Q of this flip frog circuit α is used for sampling and is used for delta demodulation. The output signal from the output terminal Q of the flip-flop circuit 01 is also supplied to the delta demodulator α→ for the same purpose.

Furthermore, as mentioned above, a pilot detection circuit (c) is provided for detecting the /F pilot signal inserted into the L channel signal on the transmitting side, and this pilot detection circuit (1) detects the output signal of delta demodulator 01. A large sword signal is used, and its output is supplied to one input terminal of an AND circuit Qρ.

The other input terminal of the AND circuit Qη is the output terminal of the flip-flop circuit OI. output signals are supplied. The output of the AND circuit Q is then supplied to the reset terminal R of the free lag flop circuit α, thereby resetting this circuit.

Next, the operation of the circuit shown in FIG. 5 will be explained with reference to the signal waveforms shown in FIG. Now, a series signal of an L channel signal and an R channel signal as shown in FIG. 6C similar to FIG. 4E described above is applied to the input terminal (Ill), and this signal is applied to the delta demodulator 1, supplied to I.

In addition, a lock signal as shown in FIG. 6B, which is obtained by dividing the lock signal (i.e., the clock signal on the transmitting side) by i, as shown in FIG. 6A, is applied to the terminal θ→, and this clock signal is supplied to the clock terminal C of the flip-flop circuit α1, and therefore, a lock signal as shown in Figure 6 is output from the inverted output terminal 4 of the flip-flop circuit α1, and a lock signal as shown in Figure 6 is output from the output terminal Q. Clock signals are output as shown in FIG. 1 and supplied to delta demodulators α and 0, respectively. Based on this clock signal, the data information from the input terminal α■ is transferred to the delta demodulator α→ and α1.
It is demodulated by the low-frequency F-wave generator 04 and αQ, and unnecessary components such as the pilot signal and harmonic components are removed by the low-frequency F wave generator 04 and αQ, and the output terminals θQ and α are output with the signals F and G shown in FIG. 6, respectively.
An L channel signal and an R channel signal as shown in FIG. The operation based on FIG. 6 is a normal stable state operation in which the L channel signal is taken out at the output terminal αQ and the R channel signal is taken out at the output terminal αη, as described above.

Next, when the operation is not localized to a stable state, in this case, the L channel signal appears on the output terminal Q side and the pilot signal is detected, and the operation will be explained with reference to the signal waveform in Fig. 7. .

Now, in FIG. 7, FIG. 7A is the clock signal supplied to terminal 0, FIG. 7B is the data signal supplied to the input side of the delta stamper α, and FIG. 7C is the free signal. These are the waveforms of the clock signals obtained at the output terminal Q of the lag flop circuit O. In the case of the delta demodulator 01, the normal state is to demodulate and output the R channel signal in synchronization with the falling edge of the clock signal from the output terminal Q of the flip-flop circuit α. In Figure 7, time T1
Assuming that synchronization has occurred at the time point C, the first falling edge of the clock signal shown in FIG. Become. However, since the pilot signal Sp is added to this L channel signal on the transmitting side as described above, this pilot signal S is detected by the pilot detection circuit (c). The pilot detection circuit ■ has a predetermined threshold level TH as shown in Figure 7,
The detected mother signal Sp is at this threshold level TH! , a high level signal as shown in FIG. 7E is output to the output side. This high-level signal opens the gate of the AND circuit Qρ, and the output signal resets the flip-flop circuit (II), causing the output voltage of the output terminal Q to instantaneously go to low level, thereby causing the AND circuit fi! A pulse-shaped output signal as shown in Figure 7F is generated on the output side of ρ.Then, the free-lag frog circuit αI line is driven by this pulse-shaped output signal until it enters a stable state. As a result, the clock signal from the output terminal Q of the free-lag flop circuit 0 is substantially shifted by one clock as shown in FIG. As shown in FIG. 7H, after time T2, the normal operating state is entered, and the 114th R channel signal is continuously output.

Also, since the i9 pilot signal is not detected at this time, the output of the pilot detection circuit (1) goes to a low level as shown in FIG. 7E. It should be noted that the change of the output of the pilot detection circuit to low level may be made to change to low rail with some margin after entering the normal operating state. In this way, the circuit is in a stable state, and the output terminal α
An L channel signal and an R channel signal are taken out from Q and A, respectively.

In this way, in this embodiment, the pilot signal inserted on the transmitting side is detected on the demodulating side, the L channel signal and the R channel signal are discriminated depending on the presence or absence of the pilot signal, and information can be transmitted accurately.

FIGS. 8 to 12 show a second embodiment of the present invention, and this embodiment is an example of transmitting multi-channel signals, for example, four channels.

FIG. 8 shows an example of the circuit configuration on the transmitting side. In the figure, 01) to 04 are data signals D! corresponding to each of the first to fourth channels. ~D4 are input terminals to which each of these signals is supplied to the delta modulator 0.
Supplied from 9 to (to). In the case of this channel as well, a pilot generation circuit (i.e., ) is supplied to an adder OI for addition. However,
This IP pilot signal is not only a single channel,
It may be added to multiple channels.

@9 is a clock input terminal to which a clock signal having the same period as the clock signal on the transmitting side is supplied, and this terminal Gl
The clock signal from the clock signal is divided by 100 (to the free-lag flob circuit). The output signals of the flip-flop circuit (/4 and @1 are respectively output from terminals A and B of the decoder θ).
It is designed to be supplied to As a result, each clock signal sequentially delayed by a predetermined period of time is supplied from the output terminal e6''-63 of the decoder ←◆ to the delta modulators 00 to (2). (also supplied to this multiplexer)
The output signals of the flip-flop circuits θ→ and 01 are supplied to terminals A and B, respectively, for switching purposes. Therefore, flip-flop circuit @) and −
Data from the delta modulator on-on is selected in a time-division manner by each output signal (clock signal) from This will be explained with reference to the signal waveform in Figure 9.Now, the delta modulator C (input terminals 0 to I to (2))
The data signals D1 to D4 of each channel are supplied to the data signal D4 from the input terminal (B), and the data signal D4 from the input terminal (B) is input to the data signal D4 from the pilot generation circuit (A) at the adder θ1. An identification signal is added. On the other hand, a lock signal as shown in FIG. 9A is supplied to terminal θ, and this clock signal is supplied to terminal B.
A clock signal whose frequency has been divided by 1 as shown in FIG. 9C is then supplied. As a result, clock signals delayed by a predetermined time are sequentially taken out from the output terminals C8-03 of the decoder 04 as shown in FIG. be done. Therefore, based on these clock signals, input terminal 0
Data signals D1 to D4 supplied from η~0 are modulated by delta modulators 09 to C3, respectively, and sent to the multiplexer (
c). This multiplexer θ0 is supplied with lock signals to its terminals A and B, respectively, as shown in FIG. are sequentially switched in the multiplexer (c), so that the output terminal θ receives data signals D1 to D1 as shown in FIG. 9H.
I) 4 is taken out in the form of a serial signal.

FIG. 10 shows an example of the circuit configuration on the receiving side of this embodiment. In the figure, 6υ is an input terminal to which the data signal transmitted from the transmitting side as described above is supplied. The data signal from the input terminal 6η is supplied to the delta demodulator and the input terminal 6, respectively. These data signals are then demodulated and then supplied to the low-frequency transducer and the oscilloscope, respectively, where unnecessary components such as the motherboard signal and harmonic components are removed, and then sent to the output terminals) and The signal is then extracted as the original data signal. As described later, the output terminal (
data signals D1 to D4 corresponding to each channel.
is selectively taken out, and only the data signal D4 corresponding to the fourth channel is taken out from the output terminal.

) is a clock input terminal to which a clock signal with the same period as the clock signal on the transmitting side is supplied;
The clock signal from the clock signal is divided into 10 by the free-lag frog circuit (2), and then further divided by 100 by the next-stage free-lag frog circuit. and to the free-lag frog circuit) and −
Each output signal is supplied to terminals A and B of decoder O◇, respectively. The decoder Iη synchronizes with each of these output signals and outputs its output terminal t.

A clock signal having a predetermined delay time is sequentially generated at ~t3, and a clock signal is sent to the switch circuit ti4 for channel selection.
supply. The switch circuit (2) operates to select each clock signal from the decoder (il) according to the channel selection signal supplied to the terminal - and supply it to the delta demodulator 79 for sampling. The clock signal for sampling to the delta 49 adjuster 0 is supplied from the output terminal t3 of the decoder 0.

輔 is a pilot signal detection circuit for detecting a pilot signal, and this detection circuit e is a delta repeater←1
Look at the output of the controller, and if it contains a pilot signal, it will operate in such a way that the output will be the same. This no'
? The output signal of the pilot detection circuit t, 4 is an OR circuit tri
is supplied to one input terminal of the OR circuit (2), and a monostable multi-pie break-0 output is supplied to the other input terminal of the OR circuit (2). The output of the OR circuit (to the OR circuit) is supplied to one input end of the tour circuit (2).
The output terminal t of the decoder r+1) is at the input terminal on the tb side of
A clock signal from No. 3 is supplied. The output signal of the notch circuit 1 is supplied as a reset signal to each reset terminal R of the free-lag frog circuits 1 and 1, and is also supplied to the single-wire multi-pie break U as an input signal.

Next, the operation of the circuit shown in FIG. 10 will be explained with reference to the signal waveforms shown in FIG. 11. Data signals D1 to D4 are supplied to the delta demodulators Q and υ from the input terminal No. 1, respectively, as shown in FIG. Six clock signals of the same period as shown in FIG. 11 are fed (JC), and this clock signal is divided by 1 in the free lag flop circuit Cf and converted into a 0 clock signal as shown in FIG. 11B. After that, the frequency is further divided by 1 by the flip-flop circuit Φ and converted into a clock signal as shown in FIG. A and B. Therefore, in synchronization with these clock signals, clock signals sequentially delayed by a predetermined time as shown in Figure 11 E to H are taken out from the output terminals to-t8 of the decoder plow. It will be done.

Any one of the extracted clock signals is selected by a channel selection signal supplied from a terminal of the switch circuit Ie, and is supplied to a delta demodulator I2 for sampling. Therefore, only the data signal corresponding to the clock signal of the selected channel is demodulated and taken out at the output side of the delta demodulator II. After removing unnecessary components such as the pilot signal and harmonic components from the extracted data signal in the low-frequency F-wave generator 6◆, it is sent to the output terminal →W.
It is extracted as playback information.

In addition, the clock signal from the internal output terminal t3 of the clock signal from the decoder Oυ is supplied to the delta demodulator branch for sampling, so that only the data signal D4 is demodulated on the output side, and the low-frequency r wave is also demodulated. After unnecessary components such as the motherboard signal and harmonic components are removed by the output terminal 6f), the signal is output as reproduction information to the output terminal 6f). Then, whether or not the output signal from the delta demodulator includes a pilot signal injected on the transmitting side is detected by the pilot detection circuit Iψ.

Next, the first case is to detect the presence or absence of this signal.
This will be explained with reference to the signal waveform in Figure 2. ・Is there a 1 in the output signal of the delta demodulator 6? If a pilot signal is included, it is detected by the pilot detection circuit 01, and its output becomes high level, and the output of the OR circuit also becomes high level.As a result, the output of Noah's epilogue becomes low level. Therefore, the free-lag frog circuit and the ring are never reset. In other words, in this state, the output signal of the delta demodulator trunk is the data signal D4 of the fourth channel into which the pilot signal is injected, so that the received data information is demodulated in the correct order and is in a stable operating state. Ah, there is no need to use the flip-flop circuit■ or reset the ring. The operation of the monostable multivibrator wheel in this case is a so-called don't care operation.
e).

On the other hand, there is no in the output signal of the delta demodulator! If the pilot signal is not included, the output of the pilot detector circuit will be the first
As shown in Figure 2B, the output of the OR circuit is low level (the output of the monostable multivibrator ring is also low level in the initial state), so the output of the NOR circuit Q'1 is low level. On the side, the falling edge of the clock signal from the output terminal t3 of the decoder 0η shown in FIG.
A differential pulse as shown in Figure G is produced. Due to this differential pregnancy, the flip-flop circuit) and the phrase are reset and this reset! 11 cycles (4 clocks)
The phase is shifted by an amount, and at time T1, Dl of the data signal shown in FIG. 12A, which is supplied to the input terminal φη, is demodulated based on the clock signal from the output terminal t3 of the decoder OO shown in FIG. 12F. The output terminal of the decoder is 1. The demodulation is performed based on the clock signal (FIG. 12C) from However, as shown in Fig. 12, during the time To%TI when synchronization is lost, the clock signal from the output terminal to-t2 of the decoder shown in Fig. 12 C to E, respectively, is 3 clocks. 12C immediately after
An operation of four clocks at times T1 to T3 in synchronization with the falling edge of the clock signal from the output terminal to of the decoder IO shown in (operation in which the clock signals from the output terminals to to t3 of the decoder IO are continuously output) ). However, the pilot detection circuit I◆ has a predetermined time constant, and therefore its output does not reach the high level immediately as shown in FIG. 12B. Due to the monostable multipipe rake set to a longer time constant than the constant,
As shown in FIG. H, the flip-flop circuits - and ←) are not reset for a predetermined time T.

Note that this predetermined time T can be set to any range in which a demodulated output including the 4-lot signal can be obtained. If the state is not stable even after shifting the phase by one cycle as described above, the above operation is repeated for a predetermined time T, and a stable state is entered when the pilot signal is completely detected. Make it. Therefore, at the output terminal -,
Among the data signals D1 to D4, the data signal corresponding to the channel selected by the switch circuit is taken out, and the data signal D4, which is the fourth channel, is taken out to the output terminal Iη.

In this way, in this embodiment, when the pilot signal inserted on the transmitting side is detected, this state is considered normal and the flip-flop circuits ① and 6) are maintained in a stable state without being reset, but the pilot signal is not detected. It is regarded as an abnormality, and the free lag frog circuit and ring are reset.
Since the phase is shifted by a cycle to enter a stable state, even in the case of multi-channel signals, it is possible to accurately transmit them without using equivalent synchronization signals.

Application Examples Although the above-mentioned embodiments have mainly been described using the case of transmitting audio digital information as an example, the present invention is not limited to this, and can be similarly applied to the case of transmitting other digital data. .

Effects of the Invention As described above, according to the present invention, a signal is added to at least one of a plurality of channels and transmitted, and the demodulation side detects the presence or absence of this mother signal. Since multiple channels are identified based on the output, it is possible to perform the same operation as a synchronization signal with a small-scale circuit simply by using a motherboard signal inserted into the data, which eliminates the need for conventional signal processing. RAM
There is no need for such storage devices or other related equipment, and the structure becomes a cylindrical portion, which reduces the cost.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an example of a conventional signal format, Fig. 2 is a system diagram showing an example of the transmitting side of an embodiment of the present invention, and Figs. 3 and 4 are explanations of the operation of Fig. 2. Figure 5 is a diagram for explaining the operation of Figure 5. Figure 5 shows an example of the configuration of the receiving side of an embodiment of the present invention. Figures 6 and 7 are diagrams for explaining the operation of Figure 5. , FIG. 8 is a system diagram showing an example of the transmitting side of another embodiment of the present invention, FIG. 9 is a diagram for explaining the operation of FIG. 8, and FIG. 10 is a diagram showing another embodiment of the present invention. FIGS. 11 and 12 are diagrams for explaining the operation of FIG. 10. FIGS. (3) , (4) , <(→, 0su, 0no, (2)
is a delta modulator, (5). (to) is the pilot generation circuit, (6), and θ0 is the adder, (9). 2) is a switch circuit, (2), (11, i, 轡 is delta demodulation i, ct*, o city, (a) 2 wheels is a flip-flop circuit, H, IC is a motherboard detection circuit, QI
) is an AND circuit, M, I is a decoder, ni) is a multiplexer, I is an OR circuit, and ring is a monostable multi-pie break/child circuit.

Claims (1)

[Claims] A pilot signal is added to at least one of the plurality of channels for transmission, the presence or absence of the pilot signal is detected on the demodulation side, and each channel is identified based on the detection output. A digital data transmission method.