JPS6054788B2 - Tape for tape carrier - Google Patents
Tape for tape carrierInfo
- Publication number
- JPS6054788B2 JPS6054788B2 JP53115605A JP11560578A JPS6054788B2 JP S6054788 B2 JPS6054788 B2 JP S6054788B2 JP 53115605 A JP53115605 A JP 53115605A JP 11560578 A JP11560578 A JP 11560578A JP S6054788 B2 JPS6054788 B2 JP S6054788B2
- Authority
- JP
- Japan
- Prior art keywords
- hole
- plastic film
- tape
- metal foil
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
本発明は、テープキャリア用テープ（以下テープと呼ぶ
）の構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a tape carrier tape (hereinafter referred to as tape).
本発明の目的は、立体的な回路構成により回路実装上信
頼性の高いテープを与えることにある。An object of the present invention is to provide a tape with high reliability in terms of circuit mounting due to its three-dimensional circuit configuration.
最近の半導体実装方法としてテープキャリア方式が採用
され、電卓等の回路実装が該方式により生産されている
。A tape carrier method has been adopted as a recent semiconductor mounting method, and circuit packages such as calculators are manufactured using this method.
テープキャリア方式は、第１図に示す様に例えば高い耐
熱性を有するポリイミド等の薄いプラスチックフィルム
１にエポキシ系接着剤（図示せず）を介して、金属箔２
が接着されている。該プラスチックフィルム１には半導
体素子３の外形よりやや大きめな孔４があらかじめあけ
られており、該金属箔２は該半導体素子３のＡｕ、Ｓｎ
、Ｃ馬ハンダ等を用いて盛り上げられた・外部電極導通
端子（以下パンプと呼ぶ）５と整合されており、該孔４
の中心部に向かつて片持ち粱りになる様にエッチングさ
れる。半導体素子３のバンプ５と金属箔２は熱と圧力を
与える事で接合される。接合後、エポキシ樹脂等を含ん
だモール門ド材６でモールドされ、モールド材６はモー
ルド材流れ止め用孔７の切断面で止められた形状となる
。必要ならば、他の回路構成素子等が搭載されてテープ
より切落され、他基板へ接合されるか、又はそのまま機
器へ組立てられる。テープキャリファ方式においては最
終工程で切落されるまで、加ＴＴ程中はすべて連続した
テープで搬送されており、連続生産、加工の自動化に適
した方式といえる。しカル第１図に示した形状では次の
欠改がある。５（１）機器への組立時、金属箔２が表面
へ露出する為、外周が金属である部品との積み重ね実装
が出来ない。As shown in Fig. 1, the tape carrier method uses a thin plastic film 1 made of polyimide or the like having high heat resistance, and a metal foil 2 via an epoxy adhesive (not shown).
is glued. The plastic film 1 is pre-drilled with a hole 4 slightly larger than the outer shape of the semiconductor element 3, and the metal foil 2 is made of Au, Sn of the semiconductor element 3.
, is aligned with the external electrode conduction terminal (hereinafter referred to as pump) 5 which is raised using solder etc., and the hole 4
It is etched in a cantilevered manner towards the center. The bumps 5 of the semiconductor element 3 and the metal foil 2 are bonded by applying heat and pressure. After joining, the mold material 6 is molded with a mold gate material 6 containing epoxy resin or the like, and the mold material 6 has a shape that is stopped by the cut surface of the mold material flow stopper hole 7. If necessary, other circuit components are mounted, cut off from the tape, and bonded to another board, or assembled into a device as is. In the tape carrier method, the tape is conveyed continuously during the TT process until it is cut off in the final process, and can be said to be a method suitable for continuous production and automation of processing. The shape shown in Figure 1 has the following defects. 5(1) Since the metal foil 2 is exposed to the surface during assembly into a device, it is not possible to stack and mount components with metal outer peripheries.
（２）樹脂モールド時にモールド形状の平面的、立体的
な寸法規制が困難でスペース有効活用設計がやりずらい
。（３）金属箔２上に他の回路構成素子を搭載する時位
置決めがないので作業性が悪い。(2) During resin molding, it is difficult to control the two-dimensional and three-dimensional dimensions of the mold shape, making it difficult to design for effective space utilization. (3) When mounting other circuit components on the metal foil 2, there is no positioning, so work efficiency is poor.
本発明は、上記の欠点を解決し、信頼性の高いテープキ
ャリア用テープを提供するもであり、その要旨は、半導
体素子３が挿入される大きさの孔４が設けられ上面の金
属箔２が前記孔４の内方にオーバーハングされるよう形
成された下部プラスチックフィルム１と、前記下部プラ
スチックフィルム１の前記金属箔２が配設された上面に
積層され、且つ前記孔４と対応する位置に前記孔４とほ
ぼ同じ大きさの孔１１と、回路構成素子１０が挿入され
てその回路構成素子１０の位置決めがなされる部品位置
決め孔９とが形成された上部プラスチックフィルム８と
、前記下部プラスチックフィルム１の下方より前記孔４
内に挿入され前記オーバーハングされた金属箔２とボン
ディングされる半導体素子３と、前記孔４と孔１１内に
充填されるモールド剤６と、前記部品位置決め孔９内に
挿入され前記金属箔２に接合される回路構成素子１０と
を有することを特徴とするテープキャリア用テープであ
る。The present invention solves the above-mentioned drawbacks and provides a highly reliable tape carrier tape.The gist of the present invention is to provide a tape for a tape carrier with high reliability. a lower plastic film 1 formed to overhang inside the hole 4; and a lower plastic film 1 laminated on the upper surface of the lower plastic film 1 on which the metal foil 2 is disposed, and at a position corresponding to the hole 4. an upper plastic film 8 in which a hole 11 having approximately the same size as the hole 4 and a component positioning hole 9 into which a circuit component 10 is inserted and the circuit component 10 is positioned; The hole 4 is viewed from below the film 1.
A semiconductor element 3 inserted into the overhanging metal foil 2 and bonded thereto, a molding agent 6 filled in the holes 4 and 11, and a semiconductor element 3 inserted into the component positioning hole 9 and bonded to the overhanging metal foil 2. This tape carrier tape is characterized by having a circuit component 10 joined to the tape carrier.
次に本発明を図に基づき説明する。Next, the present invention will be explained based on the drawings.
第２図は本発明の実施例テープを使用した回路実装であ
る。FIG. 2 shows circuit mounting using the tape according to the embodiment of the present invention.
本実施例では下部のプラスチックフィルム１の金属箔２
が形成された表面に他のプラスチックフィルム８を積層
して一体構成となる構造となつている。モールド材６は
上部のプラスチックフィルム８に設けられた孔１１内に
充填され．この孔１１によつて形状を規制され、スペー
ス有効活用設計が出来る。又、金属箔２の上部は積層さ
れた上部プラスチックフィルム８によつて絶縁されてい
る為、外周が金属である部品との積み重ね実装が出来る
様になつており、さらにプラスチックフィルム８に部品
位置決め孔９を設置する事で回路構成素子１０は位置ズ
レする事なくテープ上に搭載する事が出来る。半導体素
子３と前記孔４内にオーバーハングされた金属箔２のボ
ンディングは下部プラスチックフィルム１にあけた孔４
よりやや大きめかもしくは同じ形状の孔１１を上部プラ
スチックフィルム８にあける事により第１図と同じ方法
でボンディング出来、製造工程及び製諾機械の変更をほ
ぼ必要としないものである。しかし欠点としてテープ厚
みが増えるが、上部プラスチックフィルム８に２５μｍ
以下のプラスチックフィルムを使用すれば実用上ほとん
ど問題はない。以上の如く本発明は、まず下部プラスチ
ックフィルム１と上部プラスチックフィルム８が積層さ
れその間に金属箔２がサンドイッチ配置されることから
上部プラスチックフィルム８上面には金属箔２が露出し
ないこととなり、外周が金属に形成された部品との積み
重ね実装が出来、この種の部品との組込み構造において
無駄なスペースが生じることがないばかりか、この種の
部品とのショートの心配もない。In this embodiment, the metal foil 2 of the lower plastic film 1 is
Another plastic film 8 is laminated on the surface on which is formed to form an integral structure. The molding material 6 is filled into the holes 11 provided in the upper plastic film 8. The shape is regulated by the hole 11, allowing for a design that utilizes space effectively. Furthermore, since the upper part of the metal foil 2 is insulated by the laminated upper plastic film 8, it is possible to stack and mount components with metal outer peripheries, and the plastic film 8 also has component positioning holes. 9 allows the circuit component 10 to be mounted on the tape without shifting its position. Bonding between the semiconductor element 3 and the metal foil 2 overhanging in the hole 4 is performed through the hole 4 made in the lower plastic film 1.
By making holes 11 of slightly larger size or the same shape in the upper plastic film 8, bonding can be carried out in the same manner as in FIG. 1, and there is almost no need to change the manufacturing process or the processing machine. However, the disadvantage is that the tape thickness increases, but the upper plastic film 8 has a thickness of 25 μm.
There are practically no problems if the following plastic films are used. As described above, in the present invention, first, the lower plastic film 1 and the upper plastic film 8 are laminated, and the metal foil 2 is sandwiched between them, so that the metal foil 2 is not exposed on the upper surface of the upper plastic film 8, and the outer periphery is It can be stacked and mounted with parts formed of metal, and there is no wasted space in the assembly structure with these types of parts, and there is no fear of short circuits with these types of parts.
又、上部プラスチックフィルム８に、半導体素子３が挿
入される下部プラスチックフィルム１の孔４に対応して
孔１１が設けられ、これらの孔１１，４に半導体素子３
の接点部をモールドするモールド剤６が充填されるから
、モールド剤６は従来の第１図の如く表面上にダラダラ
流れることがなくきちんと孔１１内に収まることができ
るから、モールド剤のモールド形状が平面的に、立体的
に極めて容易に定まり、従つて半導体素子３の接点部の
モールドが確実になされ、且つモールド剤の無駄も生じ
ないものである。Further, holes 11 are provided in the upper plastic film 8 in correspondence with the holes 4 of the lower plastic film 1 into which the semiconductor elements 3 are inserted, and the semiconductor elements 3 are inserted into these holes 11 and 4.
Since the molding agent 6 is filled with the molding agent 6 for molding the contact portion of the molding agent 6, the molding agent 6 does not flow loosely on the surface as in the conventional case shown in FIG. can be determined very easily in a two-dimensional and three-dimensional manner, so that the contact portion of the semiconductor element 3 can be molded reliably, and no molding agent is wasted.
加えて上部プラスチックフィルム８には回路構成素子１
０が挿入される部品位置決め孔９が設けられているから
、下部プラスチックフィルム１の金属箔２上に接合され
る回路構成素子１０の接合位置が定まり、金属箔２との
接合が確実となり、且つ外部より回路構成素子１０に働
く押圧等に対しても上部プラスチックフィルム８が保護
する役目を有する。以上の如く本発明は、上部プラスチ
ックフィルム８を前述の如く有効利用することにより、
他の金属部品との積み重ねが可能となり、半導体素子３
のモールド剤６の形成が確実となり、且つ回路構成素子
１０の位置決めと外部からの保護という多機能がもたら
されたものであり、その回路実装上の信頼性向上は実用
上はかり知れないものである。In addition, the upper plastic film 8 includes the circuit component 1.
Since the component positioning hole 9 into which 0 is inserted is provided, the bonding position of the circuit component 10 to be bonded onto the metal foil 2 of the lower plastic film 1 is determined, and the bonding with the metal foil 2 is ensured. The upper plastic film 8 also has the role of protecting the circuit component 10 from pressure exerted on the circuit component 10 from the outside. As described above, the present invention effectively utilizes the upper plastic film 8 as described above.
It is possible to stack with other metal parts, and the semiconductor element 3
The molding agent 6 can be formed reliably, and the multifunctionality of positioning the circuit component 10 and protecting it from the outside has been provided, and the reliability improvement in circuit mounting is immeasurable in practical terms. be.
第１図は従来のテープキャリア用テープを用いた回路実
装図を表わす。
第２図は本発明のテープキャリア用テープを用いた回路
実装図を表わす。１・・・・・・プラスチックフィルム
、２・・・・・・金属箔、３・・・・・・半導体素子、
４・・・・・・プラスチックフィルムに設けられた半導
体素子より大きい孔、５・・・・・・バンプ、６・・・
・・・モールド剤、７・・・・・・モールド材流れ止め
孔、８・・・・・・プラスチックフィルム１に積層され
た上部プラスチックフィルム、９・・・・・・部品位置
決め孔、１０・・・・・・回路構成素子、１１・・・・
・・上部プラスチックフィルムに設けられ前記孔４に対
応して設けられた孔。FIG. 1 shows a circuit implementation diagram using a conventional tape carrier tape. FIG. 2 shows a circuit implementation diagram using the tape carrier tape of the present invention. 1...Plastic film, 2...Metal foil, 3...Semiconductor element,
4... Hole larger than the semiconductor element provided in the plastic film, 5... Bump, 6...
...Molding agent, 7...Mold material flow prevention hole, 8...Top plastic film laminated on plastic film 1, 9...Part positioning hole, 10. ...Circuit component, 11...
...A hole provided in the upper plastic film and corresponding to the hole 4.
Claims (1)
上面の金属箔２が前記孔４の内方にオーバーハングされ
るよう形成された下部プラスチックフィルム１と、前記
下部プラスチックフィルム１の前記金属箔２が配設され
た上面に積層され、且つ前記孔４と対応する位置に前記
孔４とほぼ同じ大きさの孔１１と、回路構成素子１０が
挿入されてその回路構成素子１０の位置決めがなされる
部品位置決め孔９とが形成された上部プラスチックフィ
ルム８と、前記下部プラスチックフィルム１の下方より
前記孔４内に挿入された前記オーバーハングされた金属
箔２とボンディングされる半導体素子３と、前記孔４と
孔１１内に充填されるモールド剤６と、前記部品位置決
め孔９内に挿入され前記金属箔２に接合される回路構成
素子１０と、を有することを特徴とするテープキャリア
用テープ。1. A lower plastic film 1 formed with a hole 4 having a size into which a semiconductor element 3 is inserted, and a metal foil 2 on the upper surface overhanging the hole 4; The metal foil 2 is laminated on the upper surface, and a hole 11 having approximately the same size as the hole 4 is formed at a position corresponding to the hole 4, and a circuit component 10 is inserted and the circuit component 10 is positioned. an upper plastic film 8 in which a component positioning hole 9 is formed; a semiconductor element 3 to be bonded to the overhanging metal foil 2 inserted into the hole 4 from below the lower plastic film 1; , a tape carrier comprising: a molding agent 6 filled in the holes 4 and 11; and a circuit component 10 inserted into the component positioning hole 9 and bonded to the metal foil 2. tape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53115605A JPS6054788B2 (en) | 1978-09-19 | 1978-09-19 | Tape for tape carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53115605A JPS6054788B2 (en) | 1978-09-19 | 1978-09-19 | Tape for tape carrier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5541780A JPS5541780A (en) | 1980-03-24 |
| JPS6054788B2 true JPS6054788B2 (en) | 1985-12-02 |
Family
ID=14666762
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP53115605A Expired JPS6054788B2 (en) | 1978-09-19 | 1978-09-19 | Tape for tape carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6054788B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01113173U (en) * | 1988-01-26 | 1989-07-31 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52153478A (en) * | 1976-06-15 | 1977-12-20 | Matsushita Electric Ind Co Ltd | Electronic watch |
| JPS532078A (en) * | 1976-06-28 | 1978-01-10 | Citizen Watch Co Ltd | Sealing structure for semiconductor device |
-
1978
- 1978-09-19 JP JP53115605A patent/JPS6054788B2/en not_active Expired
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52153478A (en) * | 1976-06-15 | 1977-12-20 | Matsushita Electric Ind Co Ltd | Electronic watch |
| JPS532078A (en) * | 1976-06-28 | 1978-01-10 | Citizen Watch Co Ltd | Sealing structure for semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01113173U (en) * | 1988-01-26 | 1989-07-31 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5541780A (en) | 1980-03-24 |
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