JPS6052730U

JPS6052730U - pulse generator

Info

Publication number: JPS6052730U
Application number: JP14350583U
Authority: JP
Inventors: 賢一天野
Original assignee: 株式会社明電舎
Priority date: 1983-09-16
Filing date: 1983-09-16
Publication date: 1985-04-13

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は従来のパルス発生器の具体的な回路構成を示す
回路図、第２図はその動作を示す波形図でイはリセット
スイッチの一方のトランジスタのベース電極に印加され
るパルス電圧波形図、同図口は出力側に表われる鋸歯状
波の電圧波形図、第３図は本考案に係るパルス発生器の
具体的な回路構成図、第４図は本考案のパルス発生器の
動作を示す図で同図イはリセットスイッチの一方のトラ
ンジスタに印加されるベース電極に印加されるパルス電
圧波形図、同図口は出力側に表わされる鋸歯状波の電圧
波形図。第５図は得られる鋸歯状波のオフセット電圧の
状態を示す説明図で、同図イは第１図に示す従来のパル
ス発生器による場合、同図口、ハ、二は本考案によるパ
ルス発生器で得られるオフセット電圧の具体例。１は高利得増幅器、２は積分用コンデンサ、３、　４．
　１０．　１２はトランジスタ、５．７は固定抵抗器、
６はダイオード、８，１１は可変抵抗器、９は零になら
ない場合のオフセット、１３は可変抵抗器を調整して零
になった場合のオフセット。！Ａ −譬１　　第２図ｅｂ’　　Ｊｔ　　　ｆｈ “　　Ａ１ノ（ンーｔ：ｌ　　　　　　ｌ　　　　　　　　　　Ｉ！Ｌ−−−
−一−ゞ似第５図９１Ｌ−ｍ−− １１１ −、−：　　　゛Figure 1 is a circuit diagram showing the specific circuit configuration of a conventional pulse generator, Figure 2 is a waveform diagram showing its operation, and A is a pulse voltage waveform diagram applied to the base electrode of one transistor of the reset switch. , the opening of the same figure is a voltage waveform diagram of the sawtooth wave appearing on the output side, FIG. 3 is a specific circuit configuration diagram of the pulse generator according to the present invention, and FIG. 4 is a diagram showing the operation of the pulse generator according to the present invention. In the figure, A is a pulse voltage waveform diagram applied to the base electrode of one transistor of the reset switch, and the opening of the diagram is a sawtooth wave voltage waveform diagram expressed on the output side. Fig. 5 is an explanatory diagram showing the state of the offset voltage of the sawtooth wave obtained. A specific example of the offset voltage obtained with the device. 1 is a high gain amplifier, 2 is an integrating capacitor, 3, 4.
10. 12 is a transistor, 5.7 is a fixed resistor,
6 is a diode, 8 and 11 are variable resistors, 9 is an offset when the value does not become zero, and 13 is an offset when the variable resistor is adjusted to become zero. ! A - Parable 1 Figure 2 eb' Jt fh "A1ノ(n-t :l l I!L---
-1-ゞSimilar Figure 5 91L-m-- 1 11 -,-: ゛

Claims

[Scope of utility model registration request]

an integrating amplifier consisting of a high gain amplifier and an integrating capacitor; a first variable resistor connected between the integrating capacitor and the terminal of the input power source and determining a time constant during charging of the integrating capacitor; and the integrating capacitor. a reset switch that is connected in parallel between the terminals of the transistors and that resets the integrating amplifier by connecting a PNP transistor and an NPN transistor in reverse; a connection point that connects the emitter and base of each transistor of the reset switch; A second variable resistor connected between the terminals of the input power source to adjust the offset voltage of the sawtooth wave, and an output circuit provided on the output side of the integrating amplifier and consisting of a diode and an output resistor. pulse generator.