JPS6050071B2 - semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to memory cells known as FAMOS, and is particularly directed to preventing the conventional problem of weak writing during reading.

An 8×IK bit FA using a dual-layer gate FAMOS memory cell shown in Figure 1 and a memory cell shown in Figure 2.
The configuration of MOSLSI memory is shown. In FIG. 1, 1 is a semiconductor substrate made of P-type silicon (si);
2 and 3 are the drain and source of the FAMOS memory cell, both of which are constructed of N-type semiconductor regions, 4 is a floating gate made of polysilicon, 5 is a control gate made of, for example, aluminum (Al), and 6 is a silicon gate. An insulating film 6 is interposed between the semiconductor substrate 1, the gate 4, and the gate 5, and is an insulating film such as an oxide film. Furthermore, in FIG. 2, 7 is a Y-decoder for selecting a column of memory cells, 8 is an X-decoder for selecting a row of memory cells, and 9 is a vertical 6-decoder for selecting a row of memory cells.
It is a group consisting of 1024 memory cells arranged in 4 rows and 16 columns, and there are 8 groups, so there are 8192 memory cells in total.
memory cells are installed. Further, 10 is a control input terminal for sending a control gate signal, 11 is an output terminal for reading the contents of the memory cell and sending the output to the output buffer, and 12 is connected to the drain of the memory cell in the row. 16* drain line, 13
are 64 signal lines connected to the control gate 5 of the memory cell. J First, the operating mechanism of the FAMOS memory cell will be explained with reference to FIG. When information is written in the memory cell, electrons are injected into the floating gate 4, and even if a positive read control signal is applied to the control gate 5, the transistor does not turn on and remains OFF, but the memory When no information is written to the cell or when information is erased, no electrons are injected into the floating gate and it is neutral, and when a read control signal is applied to the control gate 5, the memory cell transistor turns 0N. do.
Almost all commercially available 8.times.1024-bit LSI memory systems using memory cells that operate in this manner have the configuration shown in FIG. However, in such a conventional LSI memory system, 64 x 1024-bit memory cells are configured at the intersections of 64 signal lines to control gates and 16 memory cell drain lines, and control The signal to the gate is selected by six address signals (23=64),
Since the drain line of the memory cell is selected by four address signals (7=16), the signal to the control gate is necessarily applied later than the signal to the memory cell drain.

Such delays create major problems, especially when erased memory cells are read. That is, as shown in FIG. 3, since a positive bias is applied to the control gate 5 while the drain 2 is positively biased, the N+ type channel 14 is applied at the same time as a positive bias is applied to the control gate 5. extends from the source side, which has a low potential, to the drain side, and when the depletion region 15 becomes less than a certain length, avalanche breakdown occurs in the depletion region 15, and current begins to flow from the drain 2 to the source 3.

At this time, some of the hot electrons generated by the avalanche breakdown are injected into the floating gate and weak writing occurs. This can lead to memory malfunctions. The present invention has been made to eliminate the above-mentioned drawbacks of the conventional technology, which are caused by the delay in applying bias to the control gate. Based on the recognition that this is the case, a bias is applied to the control gate earlier than a bias is applied to the drain, thereby suppressing the occurrence of the above-mentioned weak writing.

Hereinafter, the present invention will be explained in detail with reference to its embodiments.

Embodiment 1 First, a decoder circuit is generally constructed as shown in FIG. 4, and since it is well known, a detailed explanation will be omitted here, but it basically consists of a series connection of transistors. Therefore, as the number of address signals increases, the signals must be output through more transistors, and the delay time increases.

Therefore, in this embodiment, the signal to be sent to the control gate is selected by four address signals, and the signal to be sent to the memory cell drain is selected by six address signals. In FIG. 4, 16 is a signal source. ) To explain this with reference to Figure 2, first, the number of signal lines corresponding to the selection of the signal to the control gate by four address signals is 7 = 16, and the number of signal lines to the drain of the 1'Mori cell is set to 16. Corresponding to the selection of signals by six address signals, the number of drain lines 12 of one group of memory cells 9 may be set to 7=64.

Example ■ A simple way to delay the signal to the memory cell drain line is to provide a delay circuit in the address buffer circuit that selects the drain line. good.

That is, since the buffer circuit basically consists of several stages of inverters, a delay time is generated corresponding to the increased number of stages, and the signal to the drain line is delayed. As still another means, selection of the control gate may be detected and drain line selection may be permitted based on the detected output.

In the present invention as described above, when a memory cell in an erased state is read out, the situation is as shown in FIG. 5.

That is, since a positive bias is applied to the control gate 5 earlier than to the drain, a channel is uniformly formed between the drain 2 and the source 3. In this state, a positive bias is applied to the drain side, but since the channel has already been formed, the drain potential instantly changes to S.
゛It falls to the same potential as the source potential. Therefore, hot electrons are not generated, so weak writing does not occur, and the memory does not malfunction. Although the present invention has been described above with reference to several embodiments, it goes without saying that the present invention is not limited to the above-described embodiments, and can also be implemented, for example, in a P-channel type FAMOS memory cell.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view a showing the structure of a two-layer gate N-channel FAMOS memory cell, and its equivalent view b1. FIG. I
A system configuration diagram of a memory. FIG. 3 is a cross-sectional view showing the read state of a FAMOS memory cell in a conventional memory system. FIG. 4 is a circuit diagram showing an example of a well-known decoder circuit. 2 is a cross-sectional view showing a state of a FAMOS memory cell during reading. 1...Silicon substrate, 2...FAMOS
Drain of memory cell, 3... Source of FAMOS memory cell, 4... Floating gate, 5... Control gate, 6... Oxide film, 7... ...Y-decoder, 8...X
- Decoder, 9...1K bit memory cell, 1
0...Input terminal for control gate control, 1
1... Output terminal that goes into the output buffer, 12...
...16 memory cell drain lines, 13.
・Signal lines to 64 control gates, 14・
...N+inverted channel part, 15...
- Depletion region, 16... Signal source.

Claims (1)

[Claims] 1. A source and a drain of a second conductivity type are formed on a semiconductor surface portion of a first conductivity type, a floating gate is formed on the semiconductor surface between them with an insulating film interposed therebetween, and an insulating film is further provided on the floating gate. In a semiconductor memory device having a plurality of semiconductor memory cells with a control gate interposed therebetween, when one memory cell is accessed, a bias is applied to the control gate before the bias is applied to the drain of the memory cell. A semiconductor memory device comprising: 2 The number of address signals for selecting control gates is smaller than the number of drain selection address signals, so that a bias is applied to the control gate before a bias is applied to the drain. A semiconductor memory device according to claim 1.