JPH0877786A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE: To obtain a nonvolatile semiconductor storage device which can be improved in writing data and the number of times of erasure. CONSTITUTION: A nonvolatile semiconductor memory is provided with a memory cell array 2 in which plural memory cells are arranged in a matrix form. A source region 4 of the memory cell is grounded, a drain region 6 is connected to a bit line 7, and a control gate 8 is connected to a word line 9. The bit line 7 and the word line 9 are connected to a write-in drain voltage generation circuit 16 and a write-in gate voltage generation circuit 20 through a column selecting circuit 14 and a row selecting circuit 18 respectively. A write-in control signal PGM is inputted to the drain voltage generation circuit 16 and the gate voltage generation circuit 20, and a PGM signal inputted to the gate voltage generation circuit 20 is delayed in a falling thereof by a delay circuit 30. By using this constitution, a hot hall becoming the cause of degradation of a tunnel oxide film is suppressed to occur.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly, to electrically write repetitive data,
The present invention also relates to an electrically erasable nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art Conventionally, as a nonvolatile semiconductor memory device capable of electrically writing and electrically erasing data, a flash memory semiconductor device as shown in FIG. 17 is known. This flash memory semiconductor device has a memory array 42 in which a plurality of flash EEPROM memory cells (hereinafter simply referred to as memory cells) are arranged in a matrix.
(Here, only one memory cell is shown for simplification of description). Since each memory cell operates in the same manner, one memory cell will be focused and described below.

A memory cell is formed on a semiconductor substrate, and a source region 44 grounded and a drain region 46 connected to a bit line 47 are formed on the semiconductor substrate, and the source region 44 and the drain region are formed. A control gate 48 connected to a word line 49 is provided on the channel region between the control gate 46 and the channel 46. A floating gate 50 is provided between the control gate 48 and the channel region, the floating gate 50 and the channel region are insulated by a tunnel oxide film, and the floating gate 50 and the control gate 48 are insulated from each other. Insulated in layers. Therefore, the floating gate 5
0 is arranged in an insulated state.

The bit line 47 is a drain region 4 of a plurality of memory cells arranged in the same column in the memory array 42.
6 are commonly connected, and a plurality of them are provided according to the number of columns of memory cells. Similarly, the word line 49 connects the control gates 48 of the plurality of memory cells arranged in the same row in the memory array 42 in common, and a plurality of word lines 49 are provided according to the number of rows of the memory cells.

Each bit line 47 is connected to a write drain voltage generation circuit 56 via a column selection circuit 54, and each word line 49 is connected to a write gate voltage generation circuit 60 via a row selection circuit 58. . Then, at the time of writing data, a data write control signal (hereinafter, referred to as PGM signal) is supplied to each of the voltage generating circuits 56 and 60.

When writing data in the flash memory semiconductor device configured as described above, the PGM signal is supplied to the write gate voltage generating circuit 60 and the write drain voltage generating circuit 56. The write gate voltage generation circuit 60 and the write drain voltage generation circuit 56, to which the PGM signal is input, apply a predetermined gate voltage corresponding to the PGM signal to a predetermined memory cell via the row selection circuit 58 and the column selection circuit 54, respectively. And the drain voltage is selectively generated at the same timing. That is, the write pulse of the gate voltage and the drain voltage applied to the memory cell selected to be written is applied at the same timing as the pulse of the PGM signal, as shown in the timing chart of FIG.

In the memory cell to which the predetermined gate voltage and drain voltage are simultaneously applied, a potential difference is generated between the control gate 48 and the drain region 46, and this potential difference causes hot carriers to be injected into the floating gate 50. . Since the floating gate 50 of each memory cell is insulated, a predetermined charge is accumulated in the floating gate 50 by injecting hot carriers. As a result, data is written in the memory cell.

Next, when the written data is erased, electric charges are discharged from the floating gate 50 by field emission to electrically erase the data collectively.

As described above, in the flash memory semiconductor device, repetitive data writing and erasing can be electrically performed.

[0010]

However, it is known that the conventional flash memory semiconductor device is gradually deteriorated as the number of times of writing and erasing data is accumulated, and the number of times of writing and erasing of the flash memory semiconductor device is limited. Has been.

It is generally considered that such deterioration is caused by the injection of hot holes into the tunnel oxide film of the memory cell when writing data. When hot holes are injected into the tunnel oxide film, the tunnel oxide film itself is deteriorated, and at the same time, an interface state is generated at the interface between the tunnel oxide film and the substrate.
It is presumed that the memory cell is deteriorated.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a non-volatile semiconductor memory device capable of improving the number of times data is written and erased.

[0013]

In order to solve the above problems, the present invention provides a semiconductor substrate, a source region and a drain region formed in the semiconductor substrate, and a channel region between the source region and the drain region. A non-volatile semiconductor memory device including a tunnel oxide film provided on the floating gate, a floating gate provided on the tunnel oxide film, and a control gate provided on the floating gate via an insulating layer, Drain voltage generating means for selectively generating a drain voltage in the drain region based on a write control signal for selectively writing data in the nonvolatile semiconductor memory element, and the write control Gate voltage generating means for selectively generating a gate voltage with respect to the control gate based on a signal, and the drain voltage. Provides the delay means for delaying for a predetermined period of time fall timing of the gate voltage for the fall timing, a nonvolatile semiconductor memory device characterized in that it comprises a.

Further, according to a preferred embodiment of the present invention, the delay means delays a falling timing of the gate voltage with respect to a falling timing of the drain voltage by a predetermined time and a rising timing of the drain voltage. The rising timing of the gate voltage is advanced by a predetermined time.

Further, according to the present invention, a semiconductor substrate, a source region and a drain region formed on the semiconductor substrate,
A tunnel oxide film provided on the channel region between the source region and the drain region, a floating gate provided on the tunnel oxide film, and a control gate provided on the floating gate via an insulating layer. And a plurality of bit lines commonly connecting the drain regions of the nonvolatile semiconductor memory elements arranged in the same column in the memory array, and the memory array in which the nonvolatile semiconductor memory elements are arranged in a matrix. And a plurality of word lines commonly connecting the control gates of the nonvolatile semiconductor memory elements arranged in the same row in the memory array, and data selectively to the nonvolatile semiconductor memory elements. Drain voltage generation that selectively generates drain voltage for the plurality of bit lines based on a write control signal for writing Stage, a gate voltage generating means for selectively generating a gate voltage for the plurality of word lines based on the write control signal, and a predetermined fall timing of the gate voltage with respect to a fall timing of the drain voltage. There is provided a non-volatile semiconductor memory device comprising: a delay unit that delays by a time.

Further, according to a preferred embodiment of the present invention, the delay means delays the falling timing of the gate voltage with respect to the falling timing of the drain voltage by a predetermined time, and the rising timing of the drain voltage. The rising timing of the gate voltage with respect to is advanced by a predetermined time.

[0017]

According to the nonvolatile semiconductor memory device of the present invention,
The delay means delays the falling timing of the gate voltage by a predetermined time with respect to the falling timing of the drain voltage. As described above, since the drain voltage is not applied when the gate voltage falls, it is possible to suppress the generation of hot holes that may deteriorate the tunnel oxide film when the gate voltage is lower than the drain voltage. This can improve the number of times of writing and erasing the nonvolatile semiconductor memory element.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A flash memory semiconductor device as a nonvolatile semiconductor memory device according to embodiments of the present invention will be described below. As shown in FIG. 1, the flash memory semiconductor device is a memory in which a plurality of flash EEPROM memory cells 1 (hereinafter, simply referred to as memory cells 1) as nonvolatile semiconductor memory elements as shown in FIG. 2 are arranged in a matrix. An array 2 is provided (only one memory cell is shown in memory array 2 here for the sake of simplicity). Since each memory cell operates in the same manner, one memory cell will be focused and described below.

The memory cell 1 is, as shown in FIG.
Formed on a semiconductor substrate 3, a source region 4 grounded and a drain region 6 connected to a predetermined bit line 7 of the memory array 2 are formed on the semiconductor substrate 3. A control gate 8 connected to a predetermined word line 9 of the memory array 2 is provided on the channel region 5 between the source region 4 and the drain region 6, and between the control gate 8 and the channel region 5. Is provided with a floating gate 10. A tunnel oxide film 12 is provided between the floating gate 10 and the channel region 5.
The floating gate 10 and the control gate 8 are insulated by an insulating layer.

The bit line 7 connects the drain regions 6 of a plurality of memory cells arranged in the same column in the memory array 2 in common, and the number of bit lines 7 is set according to the number of columns of the arranged memory cells. There is. Similarly, the word line 9 connects the control gates 8 of the plurality of memory cells arranged in the same row in the memory array 2 in common, and the number of the word lines 9 is set according to the number of rows of the arranged memory cells. There is.

Each bit line 7 is connected to a write drain voltage generating circuit 16 as a drain voltage generating means through a column selecting circuit 14, and each word line 9 is connected to a row selecting circuit 18.
Is connected to the write gate voltage generating circuit 20 as a gate voltage generating means. Then, at the time of writing data, a data write control signal (hereinafter, referred to as PGM signal) is supplied to each of the write voltage generation circuits 16 and 20.

When writing data to the flash memory semiconductor device configured as described above, P is written in the write drain voltage generating circuit 16 and the write gate voltage generating circuit 20.
The GM signal is supplied to each. Here, the PGM signal supplied to the write gate voltage generation circuit 20 is supplied via a delay circuit 30 described later. This PGM signal is
This is a signal for writing "0" or "1" data in a predetermined memory cell in the memory array. That is, P
The write gate voltage generation circuit 20 and the write drain voltage generation circuit 16 to which the GM signal is input respond to the predetermined word line 9 and bit line 7 via the row selection circuit 18 and the column selection circuit 14 in response to the PGM signal. And selectively generate a predetermined gate voltage and drain voltage.
Then, in the memory cell 1 in which writing is selected and a predetermined gate voltage and drain voltage are simultaneously applied, a predetermined potential difference is applied between the control gate 8 and the drain region 6, and this potential difference causes hot carriers in the channel region. Are injected into the floating gate 10 through the tunnel oxide film 12. Since the floating gate 10 of each memory cell 1 is insulated, a predetermined charge is accumulated in the floating gate 10 by injecting hot carriers. As a result, data "0" or "1" is written in the memory cell 1 selected for writing.

On the other hand, when erasing the written data, the electric charges accumulated in the floating gate 10 are discharged by field emission to electrically erase the data collectively.
Therefore, the flash memory semiconductor device can electrically write and erase data a plurality of times.

In the above-mentioned flash memory semiconductor device, the number of times of writing and erasing is limited as already described in the prior art, and this limitation is because the tunnel oxide film is deteriorated by hot holes. The inventors focused on the deterioration of the tunnel oxide film due to the hot holes,
As a result of studying the generation mechanism of hot holes which is directly related to this deterioration, it is clarified that the hot holes generated when the gate voltage is low are the main factors.
The mechanism of occurrence of this hot hole and its countermeasure will be described below.

In FIG. 3, for MOS transistors,
A change in gate current is shown when a voltage of 8 V is applied between the drain region and the source region and the voltage applied to the gate is changed from 0 V to 10 V. In this table, the three graphs show that the tunnel oxide film has a thickness of 250 Å (hereinafter, referred to as A), 20
The characteristics in the case of having 0 A and 160 A are shown. As shown in this table, when a relatively low gate voltage is applied, the drain avalanche hot carrier (D
AHC causes a gate current, and when a relatively high gate voltage is applied, channel hot electrons (C
HE) causes a gate current. Tunnel oxide film 1
It is presumed that the hot holes considered to be the cause of the deterioration of No. 2 are the holes of the drain avalanche hot carrier when a relatively low gate voltage is applied. Avalanche hot holes are generated when a gate voltage is applied. That is, it can be understood that avalanche hot holes are likely to occur when a relatively low gate voltage is applied to the memory cell 1 to which a drain voltage sufficient to generate channel hot carriers is applied.

Considering the case where the conditions in which avalanche hot holes are likely to occur are aligned on the actual memory cell 1, the gate voltage is relatively low, for example, when the gate voltage is raised or lowered. It is possible that avalanche hot holes may sometimes occur. That is, in a normal flash memory semiconductor device, the application timings of the write gate voltage and the write drain voltage are set so as to substantially coincide with the timing of the PGM signal, but in the actual memory cell 1, for example, As shown in FIG. 4 (A), the application timing may be slightly shifted due to wiring delay or the like. Furthermore,
On the actual memory cell 1, as shown in FIG. 4B, the slope of the rise and fall of the gate voltage and the drain voltage becomes gentle due to the rounding due to the load, and the rise and fall of the gate voltage can be suppressed. It may take some time. Therefore, even if the gate voltage and the drain voltage are set to be applied at the same timing, the gate voltage may gradually rise or fall in the state where the sufficient drain voltage is applied to the memory cell 1. In case of tunnel oxide 1
It can be sufficiently predicted that avalanche hot holes may occur during the period indicated by d in FIG.

Based on the above prediction of the cause of avalanche hot hole generation, the inventors have reduced the probability of avalanche hot hole generation by applying the gate voltage and the drain voltage at the timings shown in FIG. Predicted what could be done.
In other words, by overlapping the gate voltage application timing with the drain voltage application timing, the drain voltage is not applied when the gate voltage rises and falls, which reduces the probability of avalanche hot hole occurrence. I predicted that I could do it.

In order to verify this prediction, the application timings of the gate voltage and the drain voltage are variously changed,
The following write / erase cycle test was performed.
In each test, the write time was 50 μsec, the erase time was 100 msec, and the tunnel oxide film 1
To evaluate the deterioration of No. 2, transfer conductance G given by
M was used.

GM = ΔI _D / ΔV _G = W / L · μC _OX V _D ; μ: carrier mobility Then, it is judged that this decrease in GM is a decrease in carrier mobility and an increase in interface state concentration. , The reliability of the number of times data was written and erased was evaluated according to the degree of GM deterioration.

First, the gate voltage and the drain voltage were applied at the timings shown in FIG. 6 where it is predicted that avalanche hot holes are unlikely to occur. In this case, a drain voltage of about 7 V was applied, a gate voltage of about 12 V was raised at a timing 200 nsec faster than the rising timing of the drain voltage, and a gate voltage was lowered at a timing 200 nsec later than the falling timing of the drain voltage. . Then, a write / erase cycle test was carried out by overlapping the gate voltage application timing with the drain voltage application timing in this manner, and the decrease in GM with respect to the number of write / erase cycles was examined.

Next, as a comparative example, a condition where avalanche hot holes are easily generated (a relatively low gate voltage is applied to a memory cell to which a drain voltage sufficient to generate channel hot carriers is prepared) is prepared artificially. Then, Fig. 7
The gate voltage and the drain voltage were applied at the timings shown in. That is, a ramp is provided for a certain time when the gate voltage is raised and lowered, and the application timings of the gate voltage and the drain voltage are adjusted so that a sufficient drain voltage is applied when the gate voltage is raised and lowered. . Then, the write / erase cycle test was carried out at such a timing to examine the decrease in GM with respect to the number of write / erase cycles. The injection amount of the avalanche hot holes was adjusted by adjusting the time for providing the inclination, as shown in FIG. For example,
By increasing the time for providing the inclination, it is possible to increase the period d in which the avalanche hot holes may occur, and thus the injection amount of the avalanche hot holes can be increased.

As a result of the above write / erase cycle test, a graph showing the transition of the transfer conductance GM as shown in FIG. 9 was obtained. The inclination time for adjusting the injection amount of the avalanche hot holes is 5 μsec, 2 μsec, 500 nsec, 200 at both rising (R: rise) and falling (F: fall).
nsec was prepared.

As can be seen from this graph, it is clear that the degree of deterioration of the tunnel oxide film 12 is due to the injection amount of avalanche hot holes. In other words, increasing the avalanche hot hole injection amount by increasing the ramp time at the time of raising and lowering the gate voltage and increasing the period d in which avalanche hot holes may occur increases the number of cycles. Accompanied by GM
Drops sharply. On the other hand, when the application timing of the drain voltage is overlapped with the application timing of the drain voltage, it can be seen that the GM is slightly decreased with the increase in the number of cycles. For example, when comparing the overlap at the time of performing the write / erase cycle 3000 times with 5 μsec, when the inclination time of 5 μsec is provided, a GM decrease of about 20% or more is seen, but at the overlap timing. It is only about 10% lower. In addition, it can be seen that the number of rewrites at which the GM is reduced by 10% is also increased by 3 to 30 times.

Therefore, by overlapping the application timing of the gate voltage with the application timing of the drain voltage, it is possible to eliminate the factor that causes the avalanche hot hole, which can suppress the deterioration of the tunnel oxide film 12 and the flash memory semiconductor. The number of write / erase cycles of the device can be improved.

Next, in order to investigate whether the rise or fall of the gate voltage is involved in the generation of avalanche hot holes, FIG. 10 and FIG.
A write / erase cycle test was performed at the timing shown in FIG. The writing or erasing time and the evaluation method of the memory cell deterioration were set to the same conditions as in the above cycle test.

At the timing shown in FIG. 10, a ramp time of 200 nsec is given only when the gate voltage rises, and an avalanche hot hole is generated only when the gate voltage rises.
At the timing shown in FIG. 11, a ramp time of 200 nsec was given only when the gate voltage fell, and an avalanche hot hole was generated only when the gate voltage fell. Then, a write / erase cycle test was carried out at each timing, and the GM lowering characteristic with respect to the number of write / erase cycles was examined. Further, as a comparative example, a write / erase cycle test was performed at a timing with a ramp time of 200 nsec each at the rise and fall of the gate voltage, and the GM lowering characteristic with respect to the number of write / erase cycles was examined.

As a result of the above write / erase cycle test, a graph showing the transition of the transfer conductance GM as shown in FIG. 12 was obtained. According to this graph, the GM at the timing of overlap and the GM at the timing (200nR) at which the slope is provided at the fall show the same characteristics, and the GM at the timing (200nRF) at which the slope is provided at the time of rise and fall are It can be seen that the GM and the GM at the timing (200 nF) at which the slope is provided at the time of rising exhibit the same characteristics.

Further, comparing these two sets of characteristics, it is found that
It can be seen that the combination of 00nRF and 200nF has a larger degree of decrease in GM according to the number of cycles. From this, it is understood that the generation of avalanche hot holes at the time of the rise of the gate voltage rather than at the time of the rise of the gate voltage is dominant in the reduction of the GM. Therefore, it is considered that more avalanche hot holes are generated when the gate voltage falls than when the gate voltage rises, and the memory cell is deteriorated. The reason for this will be described below.

For example, when a gate voltage of 12 V is applied to the drain region 6 of the memory cell 1 while a drain voltage of 7 V is applied, hot electrons are injected into the floating gate 10, and the floating gate is accumulated due to the accumulation of hot electrons. The voltage changes as shown in FIG.

This change will be evaluated with reference to the table of FIG. First, avalanche hot holes occur in a relatively narrow area immediately after the floating gate voltage rises. Then, as the writing progresses, the floating gate 1
When hot electrons are accumulated at 0, the floating gate voltage is gradually reduced due to the negative charge due to the hot electrons. Then, when the gate voltage is lowered at the same time as the writing is completed, the floating gate voltage is further lowered. In this case, since the floating gate voltage changes from a positive low voltage region of around 2 V where avalanche hot holes are likely to occur to a negative potential, more avalanche hot holes are injected than when rising.

Further, when a negative voltage is applied to the gate 8, it is expected that the surface of the P-type substrate will be in an accumulation state and avalanche will easily occur in the vicinity of the drain region 6. Therefore, it is conceivable that the amount of avalanche hot carriers increases due to the floating gate voltage becoming a negative potential, and that the avalanche hot holes are more easily injected into the floating gate 10 due to the attraction by the negative potential. Then, it is expected that more avalanche hot holes will be injected at the time of falling than at the time of rising of the gate voltage.

From the results of the write / erase cycle test as described above, the deterioration of the memory cell 1 which occurs at the time of writing of the flash memory semiconductor device is caused by the injection amount of the avalanche hot holes into the tunnel oxide film 12, and particularly the channel. It was found that many avalanche hot holes are injected when the gate voltage is lowered in the state where the drain voltage sufficient for generating hot carriers is applied.

Therefore, in view of the above points, the inventors have provided a delay circuit as a delay means for delaying the falling timing of the gate voltage applied to the gate 8 by a predetermined time, thereby generating an avalanche hot hole. We have developed a flash memory semiconductor device that can suppress the deterioration of the memory cell 1 by suppressing the above and improve the number of write / erase cycles.

Referring again to FIG. 1, the flash memory semiconductor device of the present invention includes a delay circuit 30 that delays the falling timing of the PGM signal supplied to the write gate voltage generation circuit 20 by a predetermined time.

As shown in FIG. 14, for example, P of 5 volts is used.
When the pulse of the GM signal is supplied, the falling timing of the PGMWL signal that has passed through the delay circuit 30 is delayed by a predetermined time. Due to this delay, the gate voltage selectively applied by the row selection circuit 18 is changed to the column selection circuit 14
Thus, the falling timing of the selectively applied drain voltage is delayed by a predetermined time.

As a result, the possibility that avalanche hot holes will be injected into the tunnel oxide film 12 is reduced, deterioration of the tunnel oxide film 12 can be prevented, deterioration of the memory cell 1 can be suppressed, and writing of the flash memory semiconductor device can be suppressed. /
The number of erase cycles can be improved.

An example of the delay circuit 30 described above will be described below. As shown in FIG. 15, the input end of the PGM signal is connected to the first RC circuit 32 via the first inverter 31.
Of the N-type FET 33 connected to the input terminal of the
connected to a. The output terminal of the first RC circuit 32 and the drain region 33b of the N-type FET 33 are connected to the input terminal of the second RC circuit 35 via the second inverter 34. The output terminal of the second RC circuit 35 has a P-type FE.
Connected to the drain region 36b of T36 and NO
It is connected to one input terminal of the R circuit 37. P type FE
The gate 36a of T36 is connected to the output terminal of the third inverter 38 whose input terminal is connected to the input source of the PGM signal, and the source region 36c of the P-type FET 36 is connected to the power source VDD.
It is connected to the. The other input end of the NOR circuit 37 is
It is connected to the input end of the PGM signal, the output end of the NOR circuit 37 is connected to the input end of the fourth inverter 39, and the PGMWL signal is output from the output end of the fourth inverter 39. The first RC circuit 32 includes a pass gate R1 and an MO.
The second RC is composed of a series circuit with the S capacitor C1.
The circuit 35 is composed of a series circuit of a pass gate R2 and a MOS capacitor C2.

The delay circuit 30 configured as described above is
The trailing edge of the PGM signal is delayed at the timing shown in FIG. That is, the 5 volt PGM pulse signal input to the delay circuit 30 as shown in FIG.
Is inverted via the inverter 31 of the first RC circuit 3
Entered in 2. The pulse signal input to the first RC circuit 32 is integrated here according to the time constants of R1 and C1 and output from the first RC circuit 32. On the other hand, N
The N-type FET 33 is turned off while the PGM pulse signal input to the gate 33a of the type-type FET 33 is high level, and this N-type FET 33 is turned on while the PGM pulse signal is low level, and the output side of the first RC circuit 32 is grounded. ing. Therefore, the pulse signal at the connection point n2 is, as shown in FIG.
It starts to fall at the same time as the rising edge of the pulse signal, and starts to rise at the same time as the falling edge of the PGM pulse signal. Then, this pulse signal is inverted through the second inverter 34, waveform-shaped, and input to the second RC circuit 35.

The pulse signal input to the second RC circuit 35 is further integrated according to the time constants of R2 and C2 and output from the second RC circuit 35. On the other hand, FIG.
The PGM pulse signal inverted by the third inverter 38 as shown in (c) is applied to the gate 36 of the P-type FET 36.
Input to a. The P-type FET 36 is turned on during the high level and connected to the power supply VDD, and turned off during the low level.

Therefore, the pulse signal at the connection point n3 begins to rise at the same time as the rising edge of the pulse signal supplied to the second RC circuit 35, as shown in FIG.
At the same time as the trailing edge of the GM pulse signal, it gradually begins to fall. Then, this pulse signal is P shown in FIG.
It is input to the NOR circuit 37 together with the GM pulse signal.

As shown in FIG. 16F, the NOR circuit 37 synthesizes the pulse signal at the connection point n3 and the pulse signal at the connection point n4 and outputs the inverted signal.

The pulse signal output from the NOR circuit 37 is inverted by the fourth inverter 39 as shown in FIG. 16 (g), and has a predetermined delay at the falling edge.
It is output as a GMWL signal.

The present invention is not limited to the above-mentioned embodiments, but can be variously modified within the scope of the invention. For example, the delay circuit may be any delay circuit that delays the gate voltage falling timing by a predetermined time with respect to the drain voltage falling timing.

[0054]

Since the present invention has the above-described structure and operation, the possibility that hot holes that cause deterioration of the tunnel oxide film will be reduced, and the number of times of writing and erasing data can be improved. A semiconductor memory device can be provided.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a memory cell incorporated in the nonvolatile semiconductor memory device of FIG.

FIG. 3 is a graph of M applied with a drain voltage of 8 volts.
6 is a graph showing changes in gate current when the gate voltage applied to the OS transistor is changed.

FIG. 4 is a diagram showing a timing in which a hot hole may occur and a region in which a hot hole may occur.

FIG. 5 is a diagram showing a timing at which a hot hole is unlikely to occur.

FIG. 6 is a diagram showing a state in which a gate voltage application timing overlaps a drain voltage application timing.

FIG. 7 is a diagram showing a case where a gate voltage is raised or lowered in a predetermined time while a drain voltage is applied.

FIG. 8 is a diagram showing a relationship between a ramp time required for raising or lowering a gate voltage and a hot hole generation region.

9 is a graph showing the degree of decrease in GM with respect to the number of cycles at the timings shown in FIGS. 6 and 7. FIG.

FIG. 10 is a diagram showing a timing at which a slope is provided only when the gate voltage is raised.

FIG. 11 is a diagram showing a timing in which a slope is provided only when the gate voltage falls.

FIG. 12 is a graph showing the degree of decrease in GM with respect to the number of cycles at the timings shown in FIGS. 10 and 11.

FIG. 13 is a diagram showing timings of respective voltages when electric charges are accumulated in a floating gate.

14 is a diagram showing the application timing of the gate voltage with respect to the drain voltage of the nonvolatile semiconductor memory device of FIG.

FIG. 15 is a schematic diagram showing an example of a delay circuit.

16 is a diagram showing an operation timing of the delay circuit of FIG.

FIG. 17 is a schematic diagram showing a conventional nonvolatile semiconductor memory device.

18 is a diagram showing timings of a PGM signal, a drain voltage, and a gate voltage supplied to the nonvolatile semiconductor memory device of FIG.

[Explanation of symbols]

2 ... Memory array, 4 ... Source region, 6 ... Drain region, 7 ... Bit line, 8 ... Control gate, 9 ... Word line, 10 ... Floating gate, 12 ... Tunnel oxide film, 14 ... Column selection circuit, 16 ... Write drain voltage generation circuit, 18 ... Row selection circuit, 20 ... Write gate voltage generation circuit, 30 ... Delay circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/792

Claims (4)

[Claims] 1. A semiconductor substrate, a source region and a drain region formed on the semiconductor substrate, a tunnel oxide film provided on a channel region between the source region and the drain region, and a tunnel oxide film on the tunnel oxide film. A nonvolatile semiconductor memory element including a provided floating gate and a control gate provided on the floating gate via an insulating layer, and data is selectively supplied to the nonvolatile semiconductor memory element. Drain voltage generating means for selectively generating a drain voltage for the drain region based on a write control signal for writing, and gate voltage for the control gate selectively based on the write control signal And a gate voltage generating means for generating the gate voltage falling timing with respect to the drain voltage falling timing. A non-volatile semiconductor memory device comprising: a delay unit that delays a timing by a predetermined time. 2. The delay means delays the falling timing of the gate voltage with respect to the falling timing of the drain voltage by a predetermined time, and advances the rising timing of the gate voltage with respect to the rising timing of the drain voltage by a predetermined time. The nonvolatile semiconductor memory device according to claim 1, wherein 3. A semiconductor substrate, a source region and a drain region formed on the semiconductor substrate, a tunnel oxide film provided on a channel region between the source region and the drain region, and a tunnel oxide film on the tunnel oxide film. A memory array in which non-volatile semiconductor memory elements each having a floating gate provided and a control gate provided on the floating gate via an insulating layer are arranged in a matrix, and in the same column in the memory array. A plurality of bit lines that connect the drain regions of the nonvolatile semiconductor memory elements arranged in common to each other and the control gates of the nonvolatile semiconductor memory elements arranged in the same row in the memory array in common. A plurality of word lines and a write control signal for selectively writing data to the nonvolatile semiconductor memory element. A drain voltage generating means for selectively generating a drain voltage for the plurality of bit lines based on a signal, and a gate voltage for the plurality of word lines selectively based on the write control signal. A non-volatile semiconductor memory device, comprising: a gate voltage generating unit for delaying a falling timing of the gate voltage with respect to a falling timing of the drain voltage; 4. The delay means delays the falling timing of the gate voltage with respect to the falling timing of the drain voltage by a predetermined time, and advances the rising timing of the gate voltage with respect to the rising timing of the drain voltage by a predetermined time. The non-volatile semiconductor memory device according to claim 3, wherein