JP3194277B2 - Read-only memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a read only memory (hereinafter referred to as RO) in a semiconductor memory device.
M), more specifically, a NAND-type ROM in which blocks formed by connecting cell transistors in series are arranged.
About.

[0002]

2. Description of the Related Art Conventionally, as a NAND type ROM, FIG.
There are known those which show the main part. In the figure, 1
₁ , 1 ₂ ... 1 _m are blocks formed by connecting cell transistors in series, and 2 ₁ , 2 ₂ ... 2 _n , 3 ₁ , 3 _2.
· 3 _n, a _{4 1, 4 2 ··· 4 n} , 5 1, 5 2 ··· 5 n is an enhancement type or a depletion type nMOS forming a cell transistor.

_{[0003], 6 1, 6 2 ··· 6} n cell selection word _{line, 7 1, 7 2 ··· 7} m block select word _{line, 8 1, 8 2 ··· 8} m is An enhancement type nMOS as a block selection transistor, 9 is a bit line,
10 is a Vcc power supply line, 11 is a load, and 12 is a data output terminal.

The block selection transistors 8 ₁ ,
8 ₂ · · · 8 _m, the cell transistor of the same structure of the enhancement type, are the same characteristics, and in the same process.

[0005] Here, FIG. 2 shows a state where the cell transistor 3 ₂ is selected, in this case, cell selection word line 6 _1, 6 ₂ · · · 6 _n, the cell selection word line 6 ₂ is L level, the cell selecting word line 6 _1, 6 ₃ ··· 6 _n is H
L level is applied to the gate of the cell transistor 3 ₂ , and the cell transistors 3 ₁ , 3 ₃ ... 3 _n
Is applied with an H level.

Further, word lines 7 ₁ , 7 _2.
· · 7 _m, the block select word line 7 ₂ H level, the block select word line 7 _1, 7 ₃ · · · 7 _m is an L level, the block selection transistor ₈₂ has, at its gate H The level is applied and turned on, and the block selecting transistors 8 ₁ , 8 ₃ ... 8 _m are applied with the L level to their gates and turned off.

[0007] Here, when the cell transistor 3 ₂ is the depletion type nMOS Since the cell transistor 3 ₂ is turned on, is performed discharging of the bit line 9, which is pre-charged, the L-level as data Is output.

[0008] On the contrary, when the cell transistor 3 ₂ is the enhancement type nMOS, the cell transistor 3 ₂ Since kept off, discharge of the bit line 9 precharged is not performed, data And the H level is output. In such a ROM, data reading is performed in this manner.

[0009]

However, in such a conventional ROM, even if the selected cell transistor is an enhancement type nMOS, the bit line 9 is discharged and erroneous reading is performed. was there. And such a malfunction is caused by the ROM
It is rapidly expanding with the miniaturization of devices, and the pursuit of the cause and the measures have been urgently needed.

As a result of experiments and research conducted by the present inventor, such malfunctions are caused by the block selection transistors 8 ₁ , 8 _2.
It was found that the leak was 8 _m . That is, if there is a leak in the block selection transistors 8 ₁ , 8 ₂ ... 8 _m , the selected cell transistor is an enhancement type nMOS, and a block selection transistor for selecting an unselected block. Even when the transistor is turned off, the total amount of leakage current of these block selecting transistors becomes considerably large, and it has been found that this is the cause of discharging the bit line 9. In other words, there is a problem in that the block selection transistors 8 ₁ , 8 ₂ ... 8 _m have the same structure and the same characteristics as the enhancement type transistors.

In view of the above, the present invention eliminates a malfunction caused by a bit line discharge due to a leak of a block selection transistor when an enhancement type cell transistor is selected, and enables correct reading. It is an object of the present invention to provide a ROM that has been optimized.

[0012]

The ROM according to the present invention comprises:
In a ROM in which a block formed by connecting a plurality of cell transistors in series is connected to a bit line via a block selecting transistor connected in series to the block,
That is, the threshold value of the block selection transistor is set higher than the threshold value of the cell transistor.

[0013]

According to the present invention, since the threshold value of the block selection transistor is higher than the threshold value of the cell transistor, the current capability can be reduced to reduce or eliminate leakage.

[0014]

An embodiment of the present invention will be described below with reference to FIG. In FIG. 1, portions corresponding to those in FIG. 2 are denoted by the same reference numerals, and redundant description is omitted.

FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention. In the _{figure, 13 1, 13 2 ··· 13} m is a block selection transistor provided in place of the block selection transistors 8 _1, 8 ₂ ··· 8 _m shown in FIG. 2, for those blocks selected Transistors 13 ₁ , 13 _2.
..13 _m has a higher threshold value than the enhancement-type cell transistor.
It has the same configuration as the ROM shown in FIG.

Here, the block selection transistor 13
The threshold value of ₁ , 13 ₂ ... 13 _m can be increased by increasing the amount of P-type impurities in the channel region, increasing the thickness of the gate oxide film, or increasing the channel length.

According to the present embodiment, since the threshold values of the block selecting transistors 13 ₁ , 13 ₂ ... 13 _m are higher than the threshold value of the enhancement type cell transistor, the current capability is reduced. Thus, leakage can be reduced or eliminated.

Therefore, it is possible to eliminate a malfunction caused by the discharge of the bit line 9 due to the leakage of the block selection transistor when the enhancement type cell transistor is selected, and to perform a correct reading.

According to this embodiment, the leakage of the enhancement type cell transistor is reduced, or
Although it cannot be eliminated, the leakage when the enhancement type cell transistor is selected can be sufficiently compensated for by the current capability of the load 11, so that the discharge of the bit line 9 by the selected enhancement type cell transistor is not a problem. No.

[0020]

According to the present invention, by adopting a configuration in which the threshold value of the block selection transistor is set higher than the threshold value of the cell transistor, the current capability of the block selection transistor is reduced and the leakage is reduced. Since the enhancement-type cell transistor is selected, a malfunction due to discharge of the bit line due to leakage of the block selection transistor when the enhancement-type cell transistor is selected can be eliminated, and correct reading can be performed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a main part of an example of a conventional ROM.

[Explanation of symbols]

1 ₁ , 1 ₂ , 1 ₃ , 1 _m block 2 ₁ , 2 ₂ ... 5 _n cell transistors 6 ₁ , 6 ₂ , 6 ₃ , 6 _n cell selection word lines 7 ₁ , 7 ₂ , 7 ₃ , 7 _m block selection word line 9 bit line 10 Vcc power supply line 11 load 12 data output terminal 13 ₁ , 13 ₂ , 13 ₃ , 13 _m block selection transistor

Claims (1)

(57) [Claims] 1. A bit line and a plurality of cell transistors are connected in series, and one end is grounded.
A plurality of blocks are provided corresponding to each of the plurality of blocks.
Connected in series between the other end of the block and the bit line.
Lead having a plurality of block selecting transistors
In the read-only memory, a threshold value of the plurality of block selection transistors is higher than a threshold value of the cell transistor.