JPS6049655A - Forming method of bump for leadless chip carrier - Google Patents
Forming method of bump for leadless chip carrierInfo
- Publication number
- JPS6049655A JPS6049655A JP15700983A JP15700983A JPS6049655A JP S6049655 A JPS6049655 A JP S6049655A JP 15700983 A JP15700983 A JP 15700983A JP 15700983 A JP15700983 A JP 15700983A JP S6049655 A JPS6049655 A JP S6049655A
- Authority
- JP
- Japan
- Prior art keywords
- chip carrier
- leadless chip
- bump
- solder
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title description 14
- 229910000679 solder Inorganic materials 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 235000015055 Talinum crassifolium Nutrition 0.000 claims description 6
- 244000010375 Talinum crassifolium Species 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 description 17
- 239000002184 metal Substances 0.000 description 17
- 239000000919 ceramic Substances 0.000 description 5
- 238000002844 melting Methods 0.000 description 5
- 230000008018 melting Effects 0.000 description 5
- 239000000969 carrier Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- QDOXWKRWXJOMAK-UHFFFAOYSA-N dichromium trioxide Chemical compound O=[Cr]O[Cr]=O QDOXWKRWXJOMAK-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 235000003599 food sweetener Nutrition 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 239000003765 sweetening agent Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（８１発明の技術分野
本発明はリードレスチップキャリアの基板表面に外部回
路への接続手段としてのバンプの形成方法に係り、特に
芯入バンプを効率よく正確に形成する方法に関する。Detailed Description of the Invention (81) Technical Field of the Invention The present invention relates to a method for forming bumps on the surface of a leadless chip carrier substrate as means for connecting to an external circuit, and in particular to a method for efficiently and accurately forming cored bumps. Regarding the method.
（ｂｌ 従来技術と問題点 電子計算機等の電子機器の急速な発展に伴い。(bl Conventional technology and problems With the rapid development of electronic devices such as computers.
該電子機器の電子部品の実装の高密度化や小型化が益々
要求されてきた。殊に半導体集積回路は一層その集積度
を増すと共に、セラミック基板を用いたチップキャリア
が実用化され、殊にリード端子のない所謂リードレスチ
ップキャリアが広く使用されるようになってきた。There has been an increasing demand for higher density and smaller packaging of electronic components in electronic devices. In particular, as the degree of integration of semiconductor integrated circuits continues to increase, chip carriers using ceramic substrates have been put into practical use, and in particular, so-called leadless chip carriers without lead terminals have come into widespread use.
リードレスチ・ノブキャリアの中で特に高密度実装に適
したバンプを備えたチップキャリアの構造について第１
図の断面図と第２図の下方からみた平面図を参照して述
べよう。Part 1 about the structure of a chip carrier with bumps that is particularly suitable for high-density mounting among lead rest/knob carriers.
This will be described with reference to the sectional view in the figure and the plan view seen from below in Figure 2.
通常セラミックの基板１内にキャビティ２と称する凹所
があり、ここに半導体集積回路装置のチップ３が配設さ
れている。キャビティ２はセラミック製の蓋部５で密閉
されて環境から保護されている。There is usually a recess called a cavity 2 in a ceramic substrate 1, in which a chip 3 of a semiconductor integrated circuit device is placed. The cavity 2 is sealed with a ceramic lid 5 to protect it from the environment.
前記チップ３は細い金線のボンディングワイヤ４で、キ
ャビティ２の周辺部に形成されたポンディングパッド６
に溶接等の方法で接続される。The chip 3 is a thin gold wire bonding wire 4 and a bonding pad 6 formed around the cavity 2.
connected by welding or other methods.
ポンディングパッド６はビア７と称するタングステン等
の高融点金属粉末とセラミック粉末とを混合して焼結し
て形成した導電性の端子に接続し。The bonding pad 6 is connected to a conductive terminal called a via 7 formed by mixing and sintering a high melting point metal powder such as tungsten and a ceramic powder.
チップ基板１のセラミックの中を貫通して、チップ基板
１の表面１ａに形成された外部回路接続用のパッド８に
接続する。It penetrates through the ceramic of the chip substrate 1 and connects to an external circuit connection pad 8 formed on the surface 1a of the chip substrate 1.
」−記パソド８に通常Ｐｂ−５ｎ系の鑞材で形成された
突起状のバンプ９が機械的に接続されてチップキャリア
に搭載した半導体集積回路装置のチップ３の外部回路接
続手段を形成している。- A protruding bump 9 usually formed of a Pb-5n based brazing material is mechanically connected to the pad 8 to form external circuit connection means for the chip 3 of the semiconductor integrated circuit device mounted on the chip carrier. ing.
さて、第３図の断面図に示すように１以上に説明したチ
ップキャリアをプリント基板１０に搭載するには、該プ
リント基板１０の表面上に形成された印刷回路のバンド
１１等の接続手段上に他の電子部品とともに載置して、
全体を電気炉にいれｌ ？！Ａ度を半田の融点以上に保
ってバンプ９およびパッド１１の半田を溶かして融合さ
せて半田層１２を形成することで実装を完了する。これ
が所謂リフロー法である。 上記のようなリードレスチ
ップキャリアのハンプ９とプリント基板１０のパッド１
１との半田付けによる接続点は一枚のプリント基板１１
上でも極めて多数あり、これらの接続点が全部確実に所
定の強度を以て接続するためには、リードレスチップキ
ャリアの基板１の表面］、ａｌのバンプ９の高さのバラ
ツキを少なくする必要がある。Now, as shown in the cross-sectional view of FIG. Place it with other electronic parts on the
Put the whole thing in an electric furnace? ! Mounting is completed by keeping the degree A higher than the melting point of the solder and melting and fusing the solder on the bumps 9 and pads 11 to form a solder layer 12. This is the so-called reflow method. The hump 9 of the leadless chip carrier and the pad 1 of the printed circuit board 10 as described above
The connection point by soldering with 1 is a single printed circuit board 11
In order to reliably connect all of these connection points with a predetermined strength, it is necessary to reduce the variation in the height of the Al bumps 9 on the surface of the substrate 1 of the leadless chip carrier. .
バンプ９をバッド１１上に形成するには２例えば金属マ
スクを用いて、厚膜印刷の方法で半田ペーストを所定量
バッドＩＩ−ヒに載置し、電気炉中で溶解して半田の表
面張力で球状の突起のバンプ９とするか、同じく金属マ
スクを用いて一定量の半田よりなるソルダボールをパッ
ド１１に載置して溶融させる方法等がある。To form the bumps 9 on the pads 11 2. For example, using a metal mask, a predetermined amount of solder paste is placed on the pads II-H by thick film printing, and melted in an electric furnace to increase the surface tension of the solder. Alternatively, a solder ball made of a certain amount of solder may be placed on the pad 11 using a metal mask and melted.
容易に理解されるように、バンブ９形成の際に溶融した
半田はパッド１１の表面を濡れて這っていく傾向があり
、パッド１１の面積と形・やその表面状態（濡れ状態）
および半田の温度による表面張力の大きさ等、複雑な要
素が絡んで何れの場合にも。As can be easily understood, the solder melted during the formation of the bumps 9 tends to wet and creep over the surface of the pad 11, and the area and shape of the pad 11 as well as its surface condition (wet state)
In any case, complicated factors are involved, such as the magnitude of surface tension due to the temperature of the solder.
バンプ９の高さを揃えることは容易ではない。It is not easy to make the heights of the bumps 9 the same.
さらに上記のリードレスチップキャリアをプリント基板
に搭載する時は既に述べたように、バンプ９は再度溶融
されるので、バンプ９形成の時と同様の半田の流れの問
題が起こる。Further, when the leadless chip carrier is mounted on a printed circuit board, the bumps 9 are melted again as described above, so the same problem of solder flow as in the case of forming the bumps 9 occurs.
その対策としてはバンプ９の中に銅のような融点の高い
金属の芯部１３（通常球形）を入れて置き。As a countermeasure, a core 13 (usually spherical) of a metal with a high melting point, such as copper, is placed inside the bump 9.
リードレスチップキャリアをプリント基板１０に搭載す
る時のりフロ一温度を高い目にして半田の流動をよくす
ると第３図の断面図に示すように、リードレスチップキ
ャリアは芯部１３によって支えられ、半田層１２は接着
剤の役目だけを司るので、半田量の影響は殆ど無くなる
。When the leadless chip carrier is mounted on the printed circuit board 10, the flow temperature is set high to improve solder flow, and as shown in the cross-sectional view of FIG. 3, the leadless chip carrier is supported by the core 13. Since the solder layer 12 serves only as an adhesive, the influence of the amount of solder is almost eliminated.
上述のように芯部１３を使用するとバンプ９の半田量の
問題が解消するが、その反面芯部１３を予め基板１のパ
ッド８に接着して置かねばならない。Using the core portion 13 as described above solves the problem of the amount of solder on the bump 9, but on the other hand, the core portion 13 must be bonded to the pad 8 of the substrate 1 in advance.
その一般的な方法としては、基板１のパッド８に予め銅
ペースト等を介して芯部１３を高温で焼付で接着する。A common method is to bond the core 13 to the pad 8 of the substrate 1 in advance by baking at a high temperature via copper paste or the like.
この接着温度が高いこと（約９００“Ｃ）や微小な芯部
１３の取り扱い等で、恋人バンプは高価なものとされ、
原価上大きな問題となっており。Lover bumps are considered expensive due to the high bonding temperature (approximately 900"C) and the handling of the minute core 13.
This is a big problem in terms of cost.
その解決策が久しく待望されていた。A solution has been awaited for a long time.
［Ｃ１発明の目的
本発明は前述の点に鑑みなされたもので、リードレスチ
ップキャリアの恋人バンプを効率的に形成する方法を提
供しようとするものである。[C1 Object of the Invention The present invention has been made in view of the above-mentioned points, and it is an object of the present invention to provide a method for efficiently forming sweetheart bumps on a leadless chip carrier.
（（１１発明の構成
上記の発明の目的は、リードレスチップキャリアの基板
表面に恋人バンブを形成するに際し、前記基板の表面上
に形成されたバッド上にそれぞれ一組のソルダボールと
芯部を相隣接して金属マスクを介して載置した後、加熱
手段により所定の温度に加熱して前記ソルダボールを溶
融流動させて前記芯部を前記パッド上の所定位置に接着
させることで容易に達成される。((11) Structure of the Invention The object of the above invention is to form a sweetener bump on the surface of the substrate of a leadless chip carrier by placing a pair of solder balls and a core on each pad formed on the surface of the substrate. This can be easily achieved by placing the solder balls adjacent to each other through a metal mask, and then heating the solder balls to a predetermined temperature using a heating means to melt and flow the solder balls, thereby adhering the core portion to a predetermined position on the pad. be done.
ｔｅｌ 発明の実施例 以下本発明の一実施例につき図面を参照して説明する。tel Embodiments of the invention An embodiment of the present invention will be described below with reference to the drawings.
第４図は本発明に基づくり一ドレスチップキャリアのバ
ンプの形成方法の概要を示す斜視図である。FIG. 4 is a perspective view showing an outline of a method for forming bumps on a single-dress chip carrier according to the present invention.
金属トレー２１にリードレスチップキャリアの基板１を
、パッド１１を配設した面を上にして規則正しく並べる
。その上に金属マスク２２を位置合わせをして、基板１
」二のパッド１１に対応して設けられた窓２７（図示せ
ず）が当該パッド１１上にくるように配置する。The substrates 1 of leadless chip carriers are regularly arranged on a metal tray 21 with the surface on which the pads 11 are arranged facing upward. The metal mask 22 is aligned on top of the substrate 1.
The window 27 (not shown) provided corresponding to the second pad 11 is placed above the pad 11.
第５図は金属マスク２２の窓２７の形状の一例を示す平
面図で、ソルダボールを収容する内部２４と芯部１３を
収容する内部２５より構成されており９両内部は図示の
ように部分的に重なっている。鎖線で示した２６はリー
ドレスチップキャリアの基板１の表面のパッド８の形を
示したものである。FIG. 5 is a plan view showing an example of the shape of the window 27 of the metal mask 22, which is composed of an interior 24 that accommodates the solder ball and an interior 25 that accommodates the core 13. overlap. The chain line 26 indicates the shape of the pad 8 on the surface of the substrate 1 of the leadless chip carrier.
第６図の平面図は別の形の窓２７を示すもので。The plan view of FIG. 6 shows another type of window 27.
本実施例では１個のバンド８に対し、ソルダボールを２
個と芯部１３を１（ｆｌｉｔ供給することが出来る。In this embodiment, two solder balls are used for one band 8.
It is possible to supply 1 (flit) of the core portion 13.
芯部１３は通常銅等の球が適当であるが、タブレット状
のものでもよい。The core 13 is normally a ball made of copper or the like, but it may also be in the form of a tablet.
金属マスク２２の材料は、半田の溶融温度（２５０℃程
度）に耐え、かつ半田に濡れないことが条件である。例
えばステンレス鋼板を水蒸気を含んだ水素雰囲気炉で加
熱してその表面を軽く酸化させ。The material of the metal mask 22 must be able to withstand the melting temperature of the solder (approximately 250° C.) and not be wetted by the solder. For example, a stainless steel plate is heated in a hydrogen atmosphere furnace containing water vapor to lightly oxidize its surface.
酸化クローム股で覆ったもの等は好適である。第５図や
第６図に示すような窓２５．２７はエツチング法で容易
に形成出来る。Those covered with a chrome oxide crotch are suitable. Windows 25 and 27 as shown in FIGS. 5 and 6 can be easily formed by etching.
次段の作業としては続いて、直径の大きいソルダボール
を金属トレー２１の中の金属マスク２２上に多数載せて
揺すぶれば、自然にソルダボールは内部２４に落ち込む
。次ぎに直径の小さい芯部１３を多数人れて揺動すれば
、これらを窓の内部２５にいれることが出来る。以上の
方法によれば、多数の小さい球状のソルダボールや芯部
１３を一々所定位置に置く必要がなく極めて効率的に配
置することが出来る。 このようにして、リードレスチ
ップキャリアの基板１のバンド８上に金属マスク２２を
介して、ソルダボールおよび芯部１３を配置したものを
、金属トレー２１のまま、電気炉に静かに送りこんで、
所定のタイムスケジュールで加熱、冷却すれば、第７図
の一部拡大断面図に示すように、芯部１３をパッド８の
」二に半田層１２で確実に接着することが出来る。In the next step, a large number of solder balls with large diameters are placed on the metal mask 22 in the metal tray 21 and shaken, so that the solder balls naturally fall into the interior 24. Next, by swinging a large number of small-diameter cores 13, they can be placed inside the window 25. According to the above method, it is not necessary to place a large number of small spherical solder balls and core portions 13 at predetermined positions one by one, and it is possible to arrange them extremely efficiently. In this way, the solder balls and the core 13 are arranged on the band 8 of the substrate 1 of the leadless chip carrier through the metal mask 22, and the metal tray 21 is gently fed into an electric furnace.
By heating and cooling according to a predetermined time schedule, the core 13 can be reliably bonded to the second part of the pad 8 with the solder layer 12, as shown in the partially enlarged sectional view of FIG.
（ｆｌ 発明の効果
以上の説明から明らかなように、リードレスチップキャ
リアをプリント基板に接続する手段の一つとして、恋人
バンプをリードレスチップキャリアの基板表面に形成す
る際、金属マスクを使用する本発明に基づいた形成方法
を採用すれば、僅かの工数で均一な品質の恋人ハンプを
形成することが出来、多大の原価削減が可能となる。さ
らに本発明による形成方法は容易に自動化出来るという
利点もある。(fl Effects of the Invention As is clear from the above explanation, a metal mask is used when forming sweetheart bumps on the substrate surface of a leadless chip carrier as one of the means for connecting the leadless chip carrier to a printed circuit board. By adopting the forming method based on the present invention, it is possible to form sweetheart humps of uniform quality with a small number of man-hours, and it is possible to greatly reduce costs.Furthermore, the forming method according to the present invention can be easily automated. There are also advantages.
第１図と第２図はバンプを有するチップキャリアの従来
の構造を示す断面図と平面図、第３図は恋人バンプを有
するリードレスチップキャリアをプリント基板に搭載し
た模様を示す断面図、第４図は本発明に基づいたリード
レスチップキャリアの恋人バンプの形成方法の一実施例
の概要を示す斜視図、第５図と第６図は本発明に使用す
る金属マスクの窓の形の実施例を示す平面図、第７図は
本実施例による方法でリードレスチップキャリアの基板
上に形成された恋人バンプの構造を示す断面図である。
図において、１はチップ基板、３はＩＣチップ。
６はボンディングバンド、７はビア、８ばバンプ接続用
パッド、９はバンプ、１０はプリント基板。
１１はプリント基板印刷回路のバンド、１２は半田層。
１３は芯部、２１は金属ｌ・レー、２２は金属マスク、
２３．２７は窓、 ２４ 、２５は窓の内部をそれぞれ
示す。
０
第４図
第６図
第７図
３1 and 2 are a cross-sectional view and a plan view showing the conventional structure of a chip carrier having bumps, FIG. 3 is a cross-sectional view showing a pattern in which a leadless chip carrier having lover bumps is mounted on a printed circuit board, and FIG. FIG. 4 is a perspective view showing an overview of an embodiment of the method for forming sweetheart bumps of a leadless chip carrier according to the present invention, and FIGS. 5 and 6 show the implementation of the window shape of the metal mask used in the present invention. FIG. 7 is a plan view showing an example, and a cross-sectional view showing the structure of sweetheart bumps formed on a substrate of a leadless chip carrier by the method according to the present embodiment. In the figure, 1 is a chip substrate and 3 is an IC chip. 6 is a bonding band, 7 is a via, 8 is a bump connection pad, 9 is a bump, and 10 is a printed circuit board. 11 is a band of a printed circuit board printed circuit, and 12 is a solder layer. 13 is a core, 21 is a metal l/ray, 22 is a metal mask,
23 and 27 are windows, and 24 and 25 are the insides of the windows, respectively. 0 Figure 4 Figure 6 Figure 7 Figure 3
Claims (1)
リアの基板表面に恋人バンプを形成するに際し、前記基
板の表面上に形成されたパッド上にそれぞれ一組のソル
ダボールと芯部を相隣接して金属マスクを介して載置し
た後、加熱手段により所定の温度に加熱して前記ソルダ
ボールを溶融流動させて前記芯部を前記バンド上の所定
位置に接着させることを特徴とするり一ドレスチップキ
ャリアのバンプの形成方法。When forming sweetheart bumps on the surface of a substrate of a leadless chip carrier on which a semiconductor integrated circuit device or the like is mounted, a pair of solder balls and a core are placed adjacent to each other on pads formed on the surface of the substrate. After being placed through a mask, the solder ball is heated to a predetermined temperature by a heating means to melt and flow, thereby adhering the core portion to a predetermined position on the band. How to form bumps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15700983A JPS6049655A (en) | 1983-08-26 | 1983-08-26 | Forming method of bump for leadless chip carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15700983A JPS6049655A (en) | 1983-08-26 | 1983-08-26 | Forming method of bump for leadless chip carrier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6049655A true JPS6049655A (en) | 1985-03-18 |
Family
ID=15640181
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15700983A Pending JPS6049655A (en) | 1983-08-26 | 1983-08-26 | Forming method of bump for leadless chip carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6049655A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62112355A (en) * | 1985-11-12 | 1987-05-23 | Ngk Spark Plug Co Ltd | Chip carrier |
| JPH02144945A (en) * | 1988-11-28 | 1990-06-04 | Sumitomo Bakelite Co Ltd | Board for semiconductor mounting and its manufacture |
| JPH0462865A (en) * | 1990-06-25 | 1992-02-27 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| JPH05183067A (en) * | 1991-06-20 | 1993-07-23 | Iwaki Electron Corp Ltd | External electrode structure of leadless package and manufacturing method thereof |
| CN106216791A (en) * | 2016-08-08 | 2016-12-14 | 北方电子研究院安徽有限公司 | Space welding and assembling method bottom the one of LCCC device |
-
1983
- 1983-08-26 JP JP15700983A patent/JPS6049655A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62112355A (en) * | 1985-11-12 | 1987-05-23 | Ngk Spark Plug Co Ltd | Chip carrier |
| JPH02144945A (en) * | 1988-11-28 | 1990-06-04 | Sumitomo Bakelite Co Ltd | Board for semiconductor mounting and its manufacture |
| JPH0462865A (en) * | 1990-06-25 | 1992-02-27 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| JPH05183067A (en) * | 1991-06-20 | 1993-07-23 | Iwaki Electron Corp Ltd | External electrode structure of leadless package and manufacturing method thereof |
| CN106216791A (en) * | 2016-08-08 | 2016-12-14 | 北方电子研究院安徽有限公司 | Space welding and assembling method bottom the one of LCCC device |
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