JP2000031189A - Spherical semiconductor device - Google Patents
Spherical semiconductor deviceInfo
- Publication number
- JP2000031189A JP2000031189A JP10210442A JP21044298A JP2000031189A JP 2000031189 A JP2000031189 A JP 2000031189A JP 10210442 A JP10210442 A JP 10210442A JP 21044298 A JP21044298 A JP 21044298A JP 2000031189 A JP2000031189 A JP 2000031189A
- Authority
- JP
- Japan
- Prior art keywords
- spherical
- semiconductor device
- electrode
- melting point
- bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 147
- 238000002844 melting Methods 0.000 claims description 30
- 230000008018 melting Effects 0.000 claims description 30
- 229910052751 metal Inorganic materials 0.000 claims description 29
- 239000002184 metal Substances 0.000 claims description 29
- 229910045601 alloy Inorganic materials 0.000 claims description 16
- 239000000956 alloy Substances 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 12
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 12
- 229910052802 copper Inorganic materials 0.000 claims description 12
- 239000010949 copper Substances 0.000 claims description 12
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 8
- 229910001128 Sn alloy Inorganic materials 0.000 claims description 6
- 239000000919 ceramic Substances 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 229910052763 palladium Inorganic materials 0.000 claims description 6
- 229910052697 platinum Inorganic materials 0.000 claims description 6
- 239000003566 sealing material Substances 0.000 claims description 6
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 3
- 229910000676 Si alloy Inorganic materials 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 3
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 claims description 3
- OFLYIWITHZJFLS-UHFFFAOYSA-N [Si].[Au] Chemical compound [Si].[Au] OFLYIWITHZJFLS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052797 bismuth Inorganic materials 0.000 claims description 3
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 239000011651 chromium Substances 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 229910052718 tin Inorganic materials 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 229910052725 zinc Inorganic materials 0.000 claims description 3
- 239000011701 zinc Substances 0.000 claims description 3
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 claims description 2
- 150000002739 metals Chemical class 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 8
- 238000005304 joining Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 229910000831 Steel Inorganic materials 0.000 description 2
- LFYJSSARVMHQJB-QIXNEVBVSA-N bakuchiol Chemical compound CC(C)=CCC[C@@](C)(C=C)\C=C\C1=CC=C(O)C=C1 LFYJSSARVMHQJB-QIXNEVBVSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000010959 steel Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006355 external stress Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1017—Shape being a sphere
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置、特に表
面に１つ以上の電極を有する球状半導体素子からなる球
状半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a spherical semiconductor device comprising a spherical semiconductor element having at least one electrode on a surface.
【０００２】[0002]
【従来の技術】近年、シリコンウェハ上に集積回路を形
成する、これまでの半導体デバイスの代わりに球状シリ
コンの表面に回路が形成されてなる球状半導体素子が開
発されている。この球状半導体素子はその表面に１つ以
上の電極を有し、種々の機能を持つ球状半導体素子を組
み合わせることにより、多様な機能を持つ半導体装置を
実現することができる。2. Description of the Related Art In recent years, a spherical semiconductor element in which an integrated circuit is formed on a silicon wafer and a circuit is formed on the surface of spherical silicon instead of the conventional semiconductor device has been developed. This spherical semiconductor element has one or more electrodes on its surface, and a semiconductor device having various functions can be realized by combining spherical semiconductor elements having various functions.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、かかる
球状半導体素子はそれ自体では機能することができず、
つまり外部回路等と電気信号をやり取りするめに外部と
電気的に接続する入出力手段が必要である。このように
球状半導体素子自体は優れた機能を持ちながらも、従来
では特にその実装レベルで有効な手段がないのが実情で
あった。However, such a spherical semiconductor device cannot function by itself,
In other words, input / output means for electrically connecting to the outside is required to exchange electric signals with an external circuit or the like. As described above, although the spherical semiconductor element itself has excellent functions, there has been no means effective at the mounting level in the related art.
【０００４】本発明はかかる実情に鑑み、外部との接続
性に優れた球状半導体装置を提供することを目的とす
る。[0004] In view of such circumstances, an object of the present invention is to provide a spherical semiconductor device having excellent connectivity with the outside.
【０００５】[0005]
【課題を解決するための手段】本発明の半導体装置は、
表面に１つ以上の電極を有する球状半導体素子からなる
半導体装置であって、前記球状半導体素子の電極の位置
に導電性の球状バンプを形成したことを特徴とする。According to the present invention, there is provided a semiconductor device comprising:
A semiconductor device comprising a spherical semiconductor element having one or more electrodes on a surface, wherein a conductive spherical bump is formed at a position of the electrode of the spherical semiconductor element.
【０００６】また、本発明の半導体装置において、前記
電極は、共通平面に接触するように配列されていること
を特徴とする。また、本発明の半導体装置において、外
部との接続対象となる球状バンプの１組に接触し得る平
面もしくは球面と球状半導体素子の表面との間隙が、０
または所定の間隙となるように前記１組の球状バンプを
球状半導体素子から突出配置したことを特徴とする。Further, in the semiconductor device according to the present invention, the electrodes are arranged so as to be in contact with a common plane. In the semiconductor device of the present invention, a gap between a flat surface or a spherical surface capable of contacting a set of spherical bumps to be connected to the outside and the surface of the spherical semiconductor element is zero.
Alternatively, the set of spherical bumps is arranged so as to protrude from the spherical semiconductor element so as to have a predetermined gap.
【０００７】また、本発明の半導体装置において、素子
表面の電極に融点が５５０℃以上の高融点金属からなる
球状バンプが形成されたことを特徴とする。また、本発
明の半導体装置において、前記電極はアルミニウムまた
は銅、あるいはそれらのうちの１つ以上の成分を含む合
金からなり、前記球状バンプは金、白金、パラジウム、
銀、銅、アルミニウムまたはニッケル、あるいはそれら
のうちの１つ以上の成分を含む合金からなることを特徴
とする。Further, in the semiconductor device of the present invention, a spherical bump made of a high melting point metal having a melting point of 550 ° C. or more is formed on the electrode on the element surface. Further, in the semiconductor device of the present invention, the electrode is made of aluminum or copper, or an alloy containing one or more components thereof, and the spherical bump is made of gold, platinum, palladium,
It is characterized by being made of silver, copper, aluminum or nickel, or an alloy containing one or more components thereof.
【０００８】また、本発明の半導体装置において、素子
表面の電極に融点が４５０℃以下の低融点金属からなる
球状バンプが形成されたことを特徴とする。また、本発
明の半導体装置において、前記電極はアルミニウムまた
は銅、あるいはそれらのうちの１つ以上の成分を含む合
金からなり、前記球状バンプは鉛、錫、インジウム、ビ
スマスまたは亜鉛、あるいはそれらのうちの１つ以上の
成分を含む合金、もしくは金−シリコン合金または金−
錫合金または銀−錫合金を主成分とする合金からなるこ
とを特徴とする。Further, in the semiconductor device of the present invention, a spherical bump made of a low melting point metal having a melting point of 450 ° C. or less is formed on an electrode on the element surface. Further, in the semiconductor device of the present invention, the electrode is made of aluminum or copper, or an alloy containing at least one component thereof, and the spherical bump is made of lead, tin, indium, bismuth or zinc, or any of them. Or an alloy containing one or more of the following components, or a gold-silicon alloy or gold-
It is characterized by being made of an alloy containing a tin alloy or a silver-tin alloy as a main component.
【０００９】また、本発明の半導体装置において、前記
電極上にチタン、タングステン、チタンタングステン、
ニッケル、クロム、金、パラジウム、銅および白金のな
かから選ばれた１または２種以上の金属が順次積層して
形成されたことを特徴とする。Further, in the semiconductor device of the present invention, titanium, tungsten, titanium tungsten,
One or two or more metals selected from nickel, chromium, gold, palladium, copper and platinum are sequentially laminated.
【００１０】また、本発明の半導体装置において、素子
表面の電極がその球状バンプを介して、セラミックス基
板、フィルムキャリア、シリコン基板、プリント回路基
板、リードフレーム、半導体チップまたは球状半導体素
子それぞれの電極と接続されることを特徴とする。In the semiconductor device of the present invention, the electrodes on the element surface are connected to the electrodes of the ceramic substrate, film carrier, silicon substrate, printed circuit board, lead frame, semiconductor chip or spherical semiconductor element via the spherical bumps. It is characterized by being connected.
【００１１】また、本発明の半導体装置において、素子
表面の電極に高融点バンプが形成され、そのバンプがセ
ラミックス基板、フィルムキャリア、シリコン基板、プ
リント回路基板、リードフレーム、半導体チップまたは
球状半導体素子それぞれの電極と、低融点金属を介して
接続されており、高融点金属と低融点金属の融点の差が
５０℃以上であることを特徴とする。In the semiconductor device of the present invention, a high melting point bump is formed on an electrode on the element surface, and the bump is formed of a ceramic substrate, a film carrier, a silicon substrate, a printed circuit board, a lead frame, a semiconductor chip or a spherical semiconductor element. And a low melting point metal, and a difference in melting point between the high melting point metal and the low melting point metal is 50 ° C. or more.
【００１２】また、本発明の半導体装置において、封止
材料で封止されたことを特徴とする。また、本発明の半
導体装置において、素子表面の電極が台形または五角形
以上の多角形または円形の形状を有することを特徴とす
る。また、本発明の半導体装置において、素子表面の電
極が、球状半導体素子の直径の３％以上の長さを直径と
する円と同等の面積を有することを特徴とする。Further, the semiconductor device of the present invention is characterized in that the semiconductor device is sealed with a sealing material. Further, in the semiconductor device of the present invention, the electrode on the element surface has a trapezoidal shape, a pentagonal or more polygonal or circular shape. Further, in the semiconductor device of the present invention, the electrode on the element surface has an area equivalent to a circle having a diameter of 3% or more of the diameter of the spherical semiconductor element.
【００１３】また、本発明の半導体装置において、高融
点金属の球状バンプの表面が低融点金属で被覆されてい
ることを特徴とする。Further, in the semiconductor device according to the present invention, the surface of the high-melting-point metal spherical bump is coated with a low-melting-point metal.
【００１４】本発明によれば、球状半導体素子の電極の
位置に導電性の球状バンプを形成したことで、この球状
バンプを介して外部の電気的接続を容易かつ的確に行う
ことができる。According to the present invention, since the conductive spherical bump is formed at the position of the electrode of the spherical semiconductor element, an external electrical connection can be easily and accurately made via the spherical bump.
【００１５】この場合、特に外部との接続対象となる球
状バンプの１組に接触し得る平面もしくは球面と球状半
導体素子の表面との間に所定の間隙が形成されるよう
に、前記１組の球状バンプが球状半導体素子から突出配
置される。このように球状バンプを球状半導体素子から
突設することにより、極めて優れたバンプの接合性を確
保することができる。溶融接合される場合は、所定の間
隙は０もしくはそれ以上あれば、溶融時のバンプの濡れ
効果により接合することができる。In this case, in particular, the one set of spherical bumps to be connected to the outside is formed so that a predetermined gap is formed between a flat surface or a spherical surface capable of contacting the set of spherical bumps and the surface of the spherical semiconductor element. The spherical bump is arranged to protrude from the spherical semiconductor element. By protruding the spherical bumps from the spherical semiconductor element in this way, it is possible to ensure extremely excellent bump bondability. In the case of fusion joining, if the predetermined gap is 0 or more, joining can be performed by the wetting effect of the bump at the time of melting.
【００１６】また、高融点金属の球状バンプの表面が低
融点金属で被覆されている。そして高融点金属と低融点
金属の融点の差が５０℃以上、好ましくは１００℃以上
とすることで、接合時にコアを固体のままの状態で表面
部を溶融させる接合が可能になる。したがって、接合箇
所をつねに一定の間隔以上、すなわちコア金属の径以上
に間隔を保つことができる。The surface of the high-melting-point metal spherical bump is coated with a low-melting-point metal. By setting the difference between the melting points of the high melting point metal and the low melting point metal to 50 ° C. or more, preferably 100 ° C. or more, it becomes possible to perform joining in which the surface is melted while the core remains solid during joining. Therefore, it is possible to always keep the joints at a certain distance or more, that is, at least a diameter of the core metal.
【００１７】なお、球状バンプはラグビーボール状、一
部接合部等が不均一に変形していてもよい。また球状バ
ンプが突出するためには、２個以上のバンプが積層され
て接合されるものであってもよい。The spherical bump may have a rugby ball shape, and a partially joined portion may be unevenly deformed. In order for the spherical bumps to protrude, two or more bumps may be stacked and joined.
【００１８】[0018]
【発明の実施の形態】以下、図面に基づき本発明による
半導体装置の好適な実施形態を説明する。図１は、本発
明による半導体装置の一実施形態を示している。この例
ではたとえば図示のように、球状半導体素子１の電極の
位置に導電性の球状バンプ１０が形成されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a semiconductor device according to the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of a semiconductor device according to the present invention. In this example, as shown, for example, conductive spherical bumps 10 are formed at the positions of the electrodes of the spherical semiconductor element 1.
【００１９】ここで、球状半導体素子１は球状のシリコ
ン結晶材料を用い、複数の製造工程を経て球状結晶材料
の表面に所望の回路を形成することでつくられる。この
製造工程としては主に、結晶材料の清浄工程、酸化膜形
成工程、フォトレジスト膜形成工程、球面露光によるフ
ォトリソグラフィ工程、パターン現像工程、エッチング
工程等を含んでいる。これらの工程により形成された回
路には、外部との電気的接続を行うための電極が設けら
れる。すなわち複数の電極が球状半導体素子１の球面に
沿って列設される。Here, the spherical semiconductor element 1 is manufactured by forming a desired circuit on the surface of the spherical crystal material through a plurality of manufacturing steps using a spherical silicon crystal material. The manufacturing process mainly includes a crystal material cleaning process, an oxide film forming process, a photoresist film forming process, a photolithography process using spherical exposure, a pattern developing process, an etching process, and the like. The circuits formed by these steps are provided with electrodes for making electrical connection to the outside. That is, a plurality of electrodes are arranged in line along the spherical surface of the spherical semiconductor element 1.
【００２０】たとえば、図１の例のように球状半導体素
子１の表面の円周に沿って、外部との接続対象となる１
組の球状バンプ１０が形成されている。球状バンプ１０
は、導電性の金属ボールを球状半導体素子１の電極部に
転写したものである。これら１組の球状バンプ１０は、
共通の接触平面（球面であってもよい）Ｓを有する。こ
の接触平面Ｓと球状半導体素子１の表面との間に所定の
間隙が形成されるように、１組の球状バンプ１０を球状
半導体素子１から突出配置してある。For example, along the circumference of the surface of the spherical semiconductor element 1 as shown in FIG.
A set of spherical bumps 10 is formed. Spherical bump 10
Is obtained by transferring a conductive metal ball to the electrode portion of the spherical semiconductor element 1. These one set of spherical bumps 10
It has a common contact plane (which may be spherical) S. A set of spherical bumps 10 is arranged so as to protrude from the spherical semiconductor element 1 so that a predetermined gap is formed between the contact plane S and the surface of the spherical semiconductor element 1.
【００２１】図２は、球状バンプ１０の配列例を模式的
に示している。接触平面Ｓに接する１組の球状バンプ１
０の各々は、球状半導体素子１の表面に形成されている
電極２に接合する。図から明らかなように接触平面Ｓと
球状半導体素子１の表面（頂点Ｐとする）間には間隙Ｇ
が形成される。この間隙Ｇを形成するように球状バンプ
１０を球状半導体素子１から突出させて配置すること
で、球状バンプ１０をたとえば接続対象に加圧して接合
する際、球状バンプ１０の有効な加圧変形しろを確保
し、適正なバンプ接合を保証する。なお、接触平面Ｓと
球状半導体素子１の表面との間隙がない、すなわちＧ＝
０の場合にもバンプ接合は可能である。FIG. 2 schematically shows an example of the arrangement of the spherical bumps 10. A set of spherical bumps 1 in contact with the contact plane S
Each of 0 is bonded to the electrode 2 formed on the surface of the spherical semiconductor element 1. As is clear from the figure, a gap G exists between the contact plane S and the surface (vertex P) of the spherical semiconductor element 1.
Is formed. By arranging the spherical bumps 10 so as to protrude from the spherical semiconductor element 1 so as to form the gaps G, when the spherical bumps 10 are pressurized and joined to a connection object, for example, the effective deformation of the spherical bumps 10 can be achieved. To ensure proper bump bonding. Note that there is no gap between the contact plane S and the surface of the spherical semiconductor element 1, that is, G =
Even in the case of 0, bump bonding is possible.
【００２２】図２の図示例において、頂点Ｐを通る接触
平面Ｓ′とした場合には球状半導体素子１の表面との間
に間隙がなくなり、このような状態では適正なバンプ接
合が難しくなる。したがって、球状バンプ１０の配列位
置は、下記式を満足することが好ましい。 Ｒ−ｒ≦（ｒ＋Ｒ）ｃｏｓθ （０≦θ≦２π） 上式において、Ｒは球状半導体素子の半径、ｒは球状バ
ンプの半径、またθは球状半導体素子と球状バンプの中
心を結ぶ線と頂点Ｐを通る直径とのなす角度である。球
状バンプの大きさｒと球状バンプの位置θとの関係は、
素子表面の電極の大きさとその間隙、ならびに必要な電
極数とにより設計される。In the example shown in FIG. 2, when the contact plane S 'passes through the vertex P, there is no gap between the contact surface and the surface of the spherical semiconductor element 1. In such a state, it is difficult to perform proper bump bonding. Therefore, it is preferable that the arrangement position of the spherical bumps 10 satisfies the following expression. R−r ≦ (r + R) cos θ (0 ≦ θ ≦ 2π) In the above equation, R is the radius of the spherical semiconductor element, r is the radius of the spherical bump, and θ is the line and vertex connecting the spherical semiconductor element and the center of the spherical bump. It is the angle made with the diameter passing through P. The relationship between the size r of the spherical bump and the position θ of the spherical bump is
It is designed according to the size of the electrodes on the element surface, the gap therebetween, and the required number of electrodes.
【００２３】球状バンプ１０は、熱圧着により球状半導
体素子１の電極２に形成することができる。この場合、
球状バンプ１０は融点が好ましくは５５０℃以上、最も
好ましくは６００℃以上の高融点金属材料により形成さ
れる。特に、電極２はアルミニウムまたは銅、あるいは
それらのうちの１つ以上の成分を含む合金からなり、そ
の場合球状バンプ１０は金、白金、パラジウム、銀、
銅、アルミニウムまたはニッケル、あるいはそれらのう
ちの１つ以上の成分を含む合金からなる。The spherical bump 10 can be formed on the electrode 2 of the spherical semiconductor element 1 by thermocompression. in this case,
The spherical bump 10 is formed of a high melting point metal material having a melting point of preferably 550 ° C. or more, most preferably 600 ° C. or more. In particular, the electrode 2 is made of aluminum or copper, or an alloy containing one or more components thereof, in which case the spherical bump 10 is made of gold, platinum, palladium, silver,
It consists of copper, aluminum or nickel, or an alloy containing one or more components thereof.
【００２４】なお、球状バンプ１０はラグビーボール
状、一部接合部等が不均一に変形していてもよい。また
球状バンプ１０が接触平面Ｓから突出するためには、２
個以上のバンプが所謂、「団子状」または「数珠つなぎ
状」に積層されて接合されるものであってもよい。The spherical bump 10 may have a rugby ball shape, and a part of the joint may be unevenly deformed. In order for the spherical bump 10 to protrude from the contact plane S, 2
A plurality of bumps may be stacked and joined in a so-called “dango-like” or “bead-like” shape.
【００２５】あるいはまた、球状バンプ１０は、溶着に
より球状半導体素子１の電極２に形成することができ
る。この場合、球状バンプ１０は融点が好ましくは４５
０℃以下、最も好ましくは４００℃以下の低融点金属材
料により形成される。特に、電極２はアルミニウムまた
は銅、あるいはそれらのうちの１つ以上の成分を含む合
金からなり、その場合球状バンプ１０は鉛、錫、インジ
ウム、ビスマスまたは亜鉛、あるいはそれらのうちの１
つ以上の成分を含む合金、もしくは金−シリコン合金ま
たは金−錫合金または銀−錫合金を主成分とする合金か
らなる。Alternatively, the spherical bump 10 can be formed on the electrode 2 of the spherical semiconductor element 1 by welding. In this case, the melting point of the spherical bump 10 is preferably 45.
It is formed of a low melting point metal material having a temperature of 0 ° C. or less, most preferably 400 ° C. or less. In particular, the electrode 2 is made of aluminum or copper, or an alloy containing one or more components thereof, wherein the spherical bump 10 is made of lead, tin, indium, bismuth or zinc, or one of them.
It is composed of an alloy containing one or more components, or an alloy containing a gold-silicon alloy, a gold-tin alloy, or a silver-tin alloy as a main component.
【００２６】上記の場合、電極２上にチタン、タングス
テン、チタンタングステン、ニッケル、クロム、金、パ
ラジウム、銅および白金のなかから選ばれた１または２
種以上の金属が順次積層して形成されることが好まし
い。アルミニウムまたはその合金からなる電極２は、半
田等の低融点金属とは濡れ性が悪く、したがって濡れ性
確保、拡散防止あるいは酸化防止等を図るために下地と
なる金属を積層しておくというものである。In the above case, one or two selected from titanium, tungsten, titanium tungsten, nickel, chromium, gold, palladium, copper and platinum are formed on the electrode 2.
It is preferable that at least one kind of metal is sequentially laminated. The electrode 2 made of aluminum or an alloy thereof has poor wettability with low-melting-point metal such as solder. Therefore, a metal serving as a base is laminated in order to secure wettability, prevent diffusion, prevent oxidation, and the like. is there.
【００２７】本発明の半導体装置を実装する際、上記の
ように形成される球状バンプ１０を介して外部回路等に
接続される。電極２はたとえば、セラミックス基板、フ
ィルムキャリア、シリコン基板、プリント回路基板、リ
ードフレーム、半導体チップまたは球状半導体素子それ
ぞれの電極と接続される。なお、複数の球状半導体素子
が接続されてから、それらを基板等に接続するようにし
てもよい。When mounting the semiconductor device of the present invention, it is connected to an external circuit or the like via the spherical bump 10 formed as described above. The electrode 2 is connected to, for example, an electrode of a ceramic substrate, a film carrier, a silicon substrate, a printed circuit board, a lead frame, a semiconductor chip, or a spherical semiconductor element. After a plurality of spherical semiconductor elements are connected, they may be connected to a substrate or the like.
【００２８】図３は、球状半導体素子１を用いたＢＧＡ
（ボールグリッドアレイ）パッケージの例を示してい
る。図において、球状半導体素子１の各電極２はそれに
形成された球状バンプ１０を介して、プリント回路基板
２０と接続される。球状半導体素子１が接続されたプリ
ント回路基板２０はさらに、各種の電子機器等と接続さ
れ、これらの電子機器との間で電気信号のやり取りを行
うことができる。なお、１つのＢＧＡパッケージ内に複
数の球状半導体素子１が搭載されるものであってもよ
い。FIG. 3 shows a BGA using the spherical semiconductor element 1.
(Ball grid array) shows an example of a package. In the figure, each electrode 2 of a spherical semiconductor element 1 is connected to a printed circuit board 20 via a spherical bump 10 formed on the electrode. The printed circuit board 20 to which the spherical semiconductor element 1 is connected is further connected to various electronic devices and the like, and can exchange electric signals with these electronic devices. Note that a plurality of spherical semiconductor elements 1 may be mounted in one BGA package.
【００２９】ここで、この例の場合をはじめ本発明の半
導体装置を実装するにあたって、図３に示すように球状
半導体素子１を封止材料３で封止するとよい。なお、こ
の封止材料３としては、樹脂あるいは樹脂とフィラーを
含むモールドコンパウンド等の絶縁材料で封止するのが
好ましい。このように封止することで、球状半導体素子
１の回路面の保護を図り、あるいは球状半導体素子１と
プリント回路基板２０等の熱膨張係数の差に起因する熱
歪みを有効に抑制することができる。Here, when mounting the semiconductor device of the present invention including this case, the spherical semiconductor element 1 may be sealed with a sealing material 3 as shown in FIG. The sealing material 3 is preferably sealed with an insulating material such as a resin or a mold compound containing a resin and a filler. By sealing in this way, the circuit surface of the spherical semiconductor element 1 is protected, or thermal distortion caused by the difference in the coefficient of thermal expansion between the spherical semiconductor element 1 and the printed circuit board 20 is effectively suppressed. it can.
【００３０】図４（Ａ）に示すように複数の球状半導体
素子１が、各電極２に形成された複数の球状バンプ１０
を介して相互に接続され、このように接続したものがプ
リント回路基板２０に実装されるものであってもよい。
さらに、このような場合、図４（Ｂ）に示すように複数
の球状半導体素子１全体を封止材料３で封止するとよ
い。As shown in FIG. 4A, a plurality of spherical semiconductor elements 1 are formed on a plurality of spherical bumps 10 formed on each electrode 2.
May be connected to each other via the above, and the connection may be mounted on the printed circuit board 20.
Further, in such a case, the whole of the plurality of spherical semiconductor elements 1 may be sealed with the sealing material 3 as shown in FIG.
【００３１】また、図５は、球状半導体素子１を用いた
ＱＦＰ（クワッドフラットパッケージ）の例を示してい
る。図において、球状半導体素子１の各電極２はそれに
形成された球状バンプ１０を介して、リードフレーム２
１と接続される。この場合にも球状半導体素子１を封止
材料３で封止するとよい。なお、半導体装置は、複数の
球状半導体素子１がリードフレーム基板に接続されるも
のであってもよい。FIG. 5 shows an example of a QFP (quad flat package) using the spherical semiconductor element 1. In the figure, each electrode 2 of a spherical semiconductor element 1 is connected to a lead frame 2 via a spherical bump 10 formed on the electrode.
1 is connected. Also in this case, the spherical semiconductor element 1 may be sealed with the sealing material 3. Note that the semiconductor device may be one in which a plurality of spherical semiconductor elements 1 are connected to a lead frame substrate.
【００３２】本発明の半導体装置の実装例として、さら
に図６に示すように特にこの例ではメモリ用の球状半導
体素子１の各電極２は球状バンプ１０を介して、半導体
チップム２２と接続される。As a mounting example of the semiconductor device of the present invention, as shown in FIG. 6, in this example, in particular, each electrode 2 of the spherical semiconductor element 1 for memory is connected to the semiconductor chip 22 via the spherical bump 10. .
【００３３】あるいは、図７（Ａ）に示したように球状
半導体素子１相互を球状バンプ１０を介して接続するこ
とができる。また、図７（Ｂ）のように、それぞれ予め
球状バンプ１０が接合された球状半導体素子１相互が接
続される。この場合、図７（Ｃ）に示されるように球状
バンプ１０は加圧後、変形していてもよい。Alternatively, as shown in FIG. 7A, the spherical semiconductor elements 1 can be connected to each other via the spherical bumps 10. Further, as shown in FIG. 7B, the spherical semiconductor elements 1 to which the spherical bumps 10 are previously bonded are connected to each other. In this case, as shown in FIG. 7C, the spherical bump 10 may be deformed after pressing.
【００３４】また、図８（Ａ）に示したように、たとえ
ばプリント回路基板２０等の接合面に対して、大小大き
さの異なる複数種類の球状バンプ１０ａ，１０ｂを介し
て、球状半導体素子１を接続することができる。この場
合、図８（Ｂ）に示すように２種類の球状バンプ１０
ａ，１０ｂを球状半導体素子１の表面に同心円状に配置
する。なお、この例では図８（Ｃ）に示されるように外
側の球状バンプ１０ａとして２個以上を重ねて積層した
ものを用いることができる。As shown in FIG. 8A, the spherical semiconductor element 1 is connected to a bonding surface of the printed circuit board 20 or the like via a plurality of types of spherical bumps 10a and 10b having different sizes. Can be connected. In this case, as shown in FIG.
a and 10b are concentrically arranged on the surface of the spherical semiconductor element 1. In this example, as shown in FIG. 8 (C), two or more outer spherical bumps 10a can be used as the outer spherical bumps 10a.
【００３５】幾つかの典型的な実装例とともに本発明の
半導体装置の構成例を説明したが、上記のように球状半
導体素子１の電極２の位置に導電性の球状バンプ１０を
形成したことで、この球状バンプ１０を介して外部の電
気的接続を容易かつ的確に行うことができる。The configuration example of the semiconductor device of the present invention has been described together with some typical mounting examples. However, the conductive spherical bumps 10 are formed at the positions of the electrodes 2 of the spherical semiconductor element 1 as described above. External electrical connection can be easily and accurately performed through the spherical bumps 10.
【００３６】ところで、上述した本発明の半導体装置に
おいて、球状半導体素子１の電極２はたとえば、図９の
ように電気的接続の組となる電極２の中心から外側に長
辺が設定されるように台形もしくは扇形の形状が好まし
い。このように長辺を外側に位置させることで、接合後
に外部応力に対して耐剥離性を増すことができる。ま
た、五角形以上の多角形または円形の形状（平面形状）
にするとよい。つまりこのような形状にすることで、球
状バンプ１０を接続対象に加圧して接合する際等、電極
２と球状バンプ１０の間に生じる負荷荷重を均等に分散
さて応力集中を避けることができる。したがって、バン
プ接合時の歪み等の発生をなくして、適正なバンプ接合
を保証することができる。By the way, in the semiconductor device of the present invention described above, the long side of the electrode 2 of the spherical semiconductor element 1 is set outward from the center of the electrode 2 forming a pair of electrical connections, for example, as shown in FIG. A trapezoidal or sector shape is preferred. By locating the long sides on the outside in this manner, the peeling resistance against external stress after joining can be increased. In addition, polygonal or circular shape (planar shape) of pentagon or more
It is good to That is, by adopting such a shape, when the spherical bumps 10 are pressurized and joined to the connection object, the load generated between the electrode 2 and the spherical bumps 10 can be evenly dispersed to avoid stress concentration. Therefore, it is possible to eliminate the occurrence of distortion or the like at the time of bump bonding and to assure proper bump bonding.
【００３７】また、球状半導体素子１の電極２の大きさ
等について、球状半導体素子１の直径の３％以上の長さ
を直径とする円と同等の面積を有することが好ましい。
電極２の面積をこのように設定することにより、半導体
装置の実装等で実用に供する場合、バンプ接合時の加圧
荷重に耐え得るだけの接合強度を確保することができ
る。したがって、この点でも適正かつ良好なバンプ接合
を保証する。The size of the electrode 2 of the spherical semiconductor element 1 and the like are preferably equal to a circle having a diameter of 3% or more of the diameter of the spherical semiconductor element 1.
By setting the area of the electrode 2 in this way, when the semiconductor device is practically used for mounting a semiconductor device or the like, it is possible to secure a bonding strength that can withstand a pressing load at the time of bump bonding. Therefore, also in this respect, proper and good bump bonding is guaranteed.
【００３８】なお、上記実施形態において球状半導体素
子１の電極２に６００℃以上の高融点バンプが形成さ
れ、そのバンプがセラミックス基板、フィルムキャリ
ア、シリコン基板、プリント回路基板、リードフレー
ム、半導体チップまたは球状半導体素子それぞれの電極
と、４００℃以下の低融点金属を介して接続されるよう
にしてもよい。あるいはまた、接続される側の電極に予
め高融点金属のバンプを形成しておき、高融点金属間を
低融点金属を介して接続するようにしてもよい。In the above embodiment, a bump having a high melting point of 600 ° C. or more is formed on the electrode 2 of the spherical semiconductor element 1, and the bump is formed of a ceramic substrate, a film carrier, a silicon substrate, a printed circuit board, a lead frame, a semiconductor chip or The electrodes of each of the spherical semiconductor elements may be connected to each other via a low melting point metal of 400 ° C. or lower. Alternatively, a high-melting-point metal bump may be formed in advance on an electrode to be connected, and the high-melting-point metal may be connected via a low-melting-point metal.
【００３９】[0039]
【発明の効果】以上説明したように本発明によれば、球
状半導体素子の電極の位置に導電性の球状バンプを形成
したことで、この球状バンプを介して外部の電気的接続
を容易かつ的確に行うことができる。この場合、球状バ
ンプを球状半導体素子から突設することにより、極めて
優れたバンプの接合性を確保することができ、この種の
球状半導体素子からなる半導体装置を実装等において高
い信頼を確保することができる。As described above, according to the present invention, since the conductive spherical bumps are formed at the positions of the electrodes of the spherical semiconductor element, an external electrical connection can be easily and accurately made via the spherical bumps. Can be done. In this case, by projecting the spherical bumps from the spherical semiconductor elements, it is possible to ensure extremely excellent bonding properties of the bumps, and to secure high reliability in mounting a semiconductor device including such spherical semiconductor elements. Can be.
【図１】本発明の半導体装置の一実施形態を示す斜視図
である。FIG. 1 is a perspective view showing one embodiment of a semiconductor device of the present invention.
【図２】本発明の半導体装置における球状バンプの配列
例を模式的に示す図である。FIG. 2 is a diagram schematically showing an example of the arrangement of spherical bumps in the semiconductor device of the present invention.
【図３】本発明の半導体装置の実装例を示す図である。FIG. 3 is a diagram showing a mounting example of a semiconductor device of the present invention.
【図４】本発明の半導体装置の別の実装例を示す図であ
る。FIG. 4 is a diagram showing another example of mounting the semiconductor device of the present invention.
【図５】本発明の半導体装置のさらに別の実装例を示す
図である。FIG. 5 is a diagram showing still another mounting example of the semiconductor device of the present invention.
【図６】本発明の半導体装置のさらに別の実装例を示す
図である。FIG. 6 is a diagram showing still another mounting example of the semiconductor device of the present invention.
【図７】本発明の半導体装置のさらに別の実装例を示す
図である。FIG. 7 is a diagram showing still another mounting example of the semiconductor device of the present invention.
【図８】本発明の半導体装置のさらに別の実装例を示す
図である。FIG. 8 is a diagram showing still another mounting example of the semiconductor device of the present invention.
【図９】本発明の半導体装置における電極の例を示す図
である。FIG. 9 is a diagram showing an example of an electrode in the semiconductor device of the present invention.
１ 球状半導体素子 ２ 電極 ３ 封止材料 １０ 球状バンプ ２０ プリント回路基板 ２１ リードフレーム ２２ 半導体チップ DESCRIPTION OF SYMBOLS 1 Spherical semiconductor element 2 Electrode 3 Encapsulation material 10 Spherical bump 20 Printed circuit board 21 Lead frame 22 Semiconductor chip
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 23/12 Ｌ (72)発明者 下川 健二 川崎市中原区井田３−35−１ 新日本製鐵 株式会社技術開発本部内 (72)発明者 橋野 英児 川崎市中原区井田３−35−１ 新日本製鐵 株式会社技術開発本部内 (72)発明者 竹田 宣生 千葉県流山市南流山４−１−７ ボールセ ミコンダクター株式会社内 (72)発明者 深野 敦之 千葉県流山市南流山４−１−７ ボールセ ミコンダクター株式会社内──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat II (Reference) H01L 23/12 L (72) Inventor Kenji Shimokawa 3-35-1 Ida, Nakahara-ku, Kawasaki-shi Nippon Steel Corporation (72) Inventor Hideji Hashino 3-35-1 Ida, Nakahara-ku, Kawasaki City Nippon Steel Corporation Technology Development Headquarters (72) Inventor Norio Takeda 4-1-7 Minamiruyama, Nagareyama City, Chiba Prefecture (72) Inventor Atsuyuki Fukano 4-1-7 Minamiruyama, Nagareyama City, Chiba Prefecture Inside Ball Semiconductor Co., Ltd.
Claims (14)
体素子からなる半導体装置であって、 前記球状半導体素子の電極の位置に導電性の球状バンプ
を形成したことを特徴とする半導体装置。1. A semiconductor device comprising a spherical semiconductor element having one or more electrodes on a surface, wherein a conductive spherical bump is formed at a position of the electrode of the spherical semiconductor element.
配列されていることを特徴とする請求項１に記載の半導
体装置。2. The semiconductor device according to claim 1, wherein said electrodes are arranged so as to contact a common plane.
組に接触し得る平面もしくは球面と球状半導体素子の表
面との間隙が、０または所定の間隙となるように前記１
組の球状バンプを球状半導体素子から突出配置したこと
を特徴とする請求項２に記載の半導体装置。3. A spherical bump 1 to be connected to the outside.
The above-mentioned 1 is set so that the gap between the flat or spherical surface that can come into contact with the set and the surface of the spherical semiconductor element is 0 or a predetermined gap.
3. The semiconductor device according to claim 2, wherein the set of spherical bumps is arranged to protrude from the spherical semiconductor element.
高融点金属からなる球状バンプが形成されたことを特徴
とする請求項１〜３のいずれか１項に記載の半導体装
置。4. The semiconductor device according to claim 1, wherein a spherical bump made of a high melting point metal having a melting point of 550 ° C. or more is formed on an electrode on the element surface.
いはそれらのうちの１つ以上の成分を含む合金からな
り、前記球状バンプは金、白金、パラジウム、銀、銅、
アルミニウムまたはニッケル、あるいはそれらのうちの
１つ以上の成分を含む合金からなることを特徴とする請
求項４に記載の半導体装置。5. The electrode according to claim 1, wherein the electrode is made of aluminum or copper, or an alloy containing one or more components thereof, and the spherical bump is made of gold, platinum, palladium, silver, copper, or the like.
The semiconductor device according to claim 4, wherein the semiconductor device is made of aluminum, nickel, or an alloy containing one or more components thereof.
低融点金属からなる球状バンプが形成されたことを特徴
とする請求項１〜３のいずれか１項に記載の半導体装
置。6. The semiconductor device according to claim 1, wherein a spherical bump made of a low melting point metal having a melting point of 450 ° C. or less is formed on an electrode on the element surface.
いはそれらのうちの１つ以上の成分を含む合金からな
り、前記球状バンプは鉛、錫、インジウム、ビスマスま
たは亜鉛、あるいはそれらのうちの１つ以上の成分を含
む合金、もしくは金−シリコン合金または金−錫合金ま
たは銀−錫合金を主成分とする合金からなることを特徴
とする請求項６に記載の半導体装置。7. The electrode is made of aluminum or copper, or an alloy containing one or more components thereof, and the spherical bump is made of lead, tin, indium, bismuth or zinc, or one or more of them. 7. The semiconductor device according to claim 6, wherein the semiconductor device is made of an alloy containing the following components, or an alloy mainly containing a gold-silicon alloy, a gold-tin alloy, or a silver-tin alloy. 8.
タンタングステン、ニッケル、クロム、金、パラジウ
ム、銅および白金のなかから選ばれた１または２種以上
の金属が順次積層して形成されたことを特徴とする請求
項６または７に記載の半導体装置。8. The method according to claim 1, wherein one or more metals selected from titanium, tungsten, titanium tungsten, nickel, chromium, gold, palladium, copper and platinum are sequentially laminated on the electrode. The semiconductor device according to claim 6 or 7, wherein
体装置において、 素子表面の電極がその球状バンプを介して、セラミック
ス基板、フィルムキャリア、シリコン基板、プリント回
路基板、リードフレーム、半導体チップまたは球状半導
体素子それぞれの電極と接続されることを特徴とする半
導体装置。9. The semiconductor device according to claim 1, wherein an electrode on an element surface is provided with a ceramic substrate, a film carrier, a silicon substrate, a printed circuit board, a lead frame, and a semiconductor via the spherical bumps. A semiconductor device which is connected to electrodes of a chip or a spherical semiconductor element.
て、 素子表面の電極に高融点バンプが形成され、そのバンプ
がセラミックス基板、フィルムキャリア、シリコン基
板、プリント回路基板、リードフレーム、半導体チップ
または球状半導体素子それぞれの電極と、低融点金属を
介して接続されており、高融点金属と低融点金属の融点
の差が５０℃以上であることを特徴とする半導体装置。10. The semiconductor device according to claim 9, wherein a high melting point bump is formed on an electrode on an element surface, and the bump is formed of a ceramic substrate, a film carrier, a silicon substrate, a printed circuit board, a lead frame, a semiconductor chip, or a spherical shape. A semiconductor device which is connected to each electrode of a semiconductor element via a low melting point metal, and a difference in melting point between the high melting point metal and the low melting point metal is 50 ° C. or more.
る請求項１〜１０のいずれか１項に記載の半導体装置。11. The semiconductor device according to claim 1, wherein the semiconductor device is sealed with a sealing material.
上の多角形または円形の形状を有することを特徴とする
請求項１〜１１のいずれか１項に記載の半導体装置。12. The semiconductor device according to claim 1, wherein the electrodes on the element surface have a trapezoidal shape, a polygonal shape of pentagon or more, or a circular shape.
直径の３％以上の長さを直径とする円と同等の面積を有
することを特徴とする請求項１〜１２のいずれか１項に
記載の半導体装置。13. The device according to claim 1, wherein the electrode on the element surface has an area equivalent to a circle having a diameter equal to or more than 3% of the diameter of the spherical semiconductor element. 13. The semiconductor device according to claim 1.
点金属で被覆されていることを特徴とする請求項１〜１
３のいずれか１項に記載の半導体装置。14. The method according to claim 1, wherein the surface of the spherical bump made of a high melting point metal is coated with a low melting point metal.
4. The semiconductor device according to any one of 3.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10210442A JP2000031189A (en) | 1998-07-09 | 1998-07-09 | Spherical semiconductor device |
| US09/350,125 US6509645B2 (en) | 1998-07-09 | 1999-07-09 | Spherical semiconductor device and method for fabricating the same |
| US09/851,324 US20020132462A1 (en) | 1998-07-09 | 2001-05-09 | Spherical semiconductor device and method for fabricating the same |
| US10/255,759 US6909182B2 (en) | 1998-07-09 | 2002-09-27 | Spherical semiconductor device and method for fabricating the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10210442A JP2000031189A (en) | 1998-07-09 | 1998-07-09 | Spherical semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000031189A true JP2000031189A (en) | 2000-01-28 |
Family
ID=16589406
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10210442A Pending JP2000031189A (en) | 1998-07-09 | 1998-07-09 | Spherical semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000031189A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002019428A1 (en) * | 2000-08-28 | 2002-03-07 | Dai Nippon Printing Co., Ltd. | Cluster globular semiconductor device |
| US6597070B2 (en) | 2000-02-01 | 2003-07-22 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
| EP1496381A2 (en) * | 2003-07-01 | 2005-01-12 | Matsushita Electric Industrial Co., Ltd. | Mount assembly, optical transmission line and photoelectric circuit board |
| US6897430B2 (en) | 2000-12-28 | 2005-05-24 | Canon Kabushiki Kaisha | Semiconductor device, optoelectronic board, and production methods therefor |
| US6928205B2 (en) | 2002-08-02 | 2005-08-09 | Canon Kabushiki Kaisha | Optical waveguide device, layered substrate and electronics using the same |
| US7002237B2 (en) | 2000-02-18 | 2006-02-21 | Sharp Kabushiki Kaisha | Spherical shaped semiconductor device, a flexible printed wiring substrate, and mounting method thereof |
| JP2006291724A (en) * | 2005-04-05 | 2006-10-26 | Hitachi Industries Co Ltd | Pump and method for preventing corrosion thereof |
-
1998
- 1998-07-09 JP JP10210442A patent/JP2000031189A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6597070B2 (en) | 2000-02-01 | 2003-07-22 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
| US7002237B2 (en) | 2000-02-18 | 2006-02-21 | Sharp Kabushiki Kaisha | Spherical shaped semiconductor device, a flexible printed wiring substrate, and mounting method thereof |
| WO2002019428A1 (en) * | 2000-08-28 | 2002-03-07 | Dai Nippon Printing Co., Ltd. | Cluster globular semiconductor device |
| US6897430B2 (en) | 2000-12-28 | 2005-05-24 | Canon Kabushiki Kaisha | Semiconductor device, optoelectronic board, and production methods therefor |
| US6936808B2 (en) | 2000-12-28 | 2005-08-30 | Canon Kabushiki Kaisha | Semiconductor device, optoelectronic board, and production methods therefor |
| US7141778B2 (en) | 2000-12-28 | 2006-11-28 | Canon Kabushiki Kaisha | Semiconductor device, optoelectronic board, and production methods therefor |
| US6928205B2 (en) | 2002-08-02 | 2005-08-09 | Canon Kabushiki Kaisha | Optical waveguide device, layered substrate and electronics using the same |
| EP1496381A2 (en) * | 2003-07-01 | 2005-01-12 | Matsushita Electric Industrial Co., Ltd. | Mount assembly, optical transmission line and photoelectric circuit board |
| EP1496381A3 (en) * | 2003-07-01 | 2008-02-06 | Matsushita Electric Industrial Co., Ltd. | Mount assembly, optical transmission line and photoelectric circuit board |
| JP2006291724A (en) * | 2005-04-05 | 2006-10-26 | Hitachi Industries Co Ltd | Pump and method for preventing corrosion thereof |
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