JPS6048613A - Signal generating circuit - Google Patents

Abstract

PURPOSE:To obtain an optional timing signal by combining a differentiation circuit, a binary counter and a latch circuit with a P-ROM so as to impress a power voltage to the P-ROM for a very short time thereby storing an output in a transmission time to a latch circuit. CONSTITUTION:A power supply terminal V is connected to an input terminal VD of the P-ROM through the differentiation circuit comprising a transistor (TR), a resistor R and a capacitor C. Further, an output terminal theta1 is connected to an input terminal D of the latch circuit 3 comprising a D-FF or the like, and an output terminal theta2 is connected to a reset terminal R of the binary counter 2 respectively. The binary counter 2 frequency-divides a clock pulse CP and outputs an address designation signal to input terminals A1-A4 corresponding to the P-ROM1 from output terminals A1-A4. The latch circuit 3 fetches an output of the P-ROM1 in synchronizing with the impression of power of the P-ROM1, keeps the output until the next latch voltage and obtains an optional timing signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal generating circuit for use in, for example, light buoys and marker lights.

Lights such as light buoys and beacon lights used as night markers require an extremely wide variety of light qualities in order to clearly indicate the installation location, purpose of installation, type of navigation route, etc.

In order to obtain such lighting quality, conventionally, diode matrices and the like have been frequently used, but these are very complicated, and once the timing is set, it is not easy to change it.

Further, as the power source for the light used in the light buoy, an independent power source such as an air cell, a dry cell battery, a solar battery, etc., which can fit inside the light buoy, is used.

These independent power supplies are more expensive than commercial AC power supplies;
From the standpoint of economy and maintenance, it is desired that the power consumed by the lighting control circuit be as small as possible, and that the parts that make up the circuit be easily available and inexpensive.

Although the present invention consumes a lot of power, it is very inexpensive and is available in large numbers on the market.
By using a program read-only memory and combining it with a differentiating circuit, a binary counter, and a latch circuit, the power supply voltage is applied to the P-ROM for an extremely short period of time compared to the clock pulse period, and the output during this energization time is - Temporarily memorized by a latch circuit so that an arbitrary timing signal can be obtained, and the operation speed is fast.
Power consumption is extremely low. Moreover, the present invention provides a signal generating circuit whose circuit components are easily available.

The details will be explained in detail below according to the attached drawings.

FIG. 1 shows a block diagram of a signal generating circuit for a marker light, which is an embodiment of the present invention.

In the figure, (1) is a P-ROM in which data can be freely written, and the input terminals vD, vss 1 output terminals θ1, θ2, and the addressing output terminals A1, A2, A3, A4 of the binary counter (2) are It comprises corresponding addressing input terminals A1, A2, A3, and A4.

The input terminal VD of the P-ROM (1) is connected to the power supply terminal V through a differential circuit consisting of a transistor Tr1, a resistor R, and a capacitor C, and the output terminal θ1 is connected to a D flip-flop (D-F'F), etc. Latch circuit (3)
and the output terminal θ2 are connected to the reset terminal H of the binary counter (2).

The binary counter <2) divides the clock pulse C2 and outputs the signals from the output terminal Al-A4 to the corresponding input terminals A1 to A4 of the P-ROM (1)! This outputs an addressing signal.

The latch circuit (3) takes in the output of the P-ROM (1) in synchronization with the application of power to the P-ROM (1), holds the output until the next latch voltage is applied, and operates the lamp. It controls a power switch (5) connected to a light bulb (4).

The truth table in FIG. 2 and the time chart in FIG. 3 are specific examples of these relationships.

In this example, the power supply voltage is differentiated at the falling edge of clock pulse C2 (the rising edge may also be used), and P
-Supplies power for only the differential pulse "1" to the input terminal VD of the ROM (1) and the input terminal C1 of the latch circuit (3).

On the other hand, the binary counter (2) divides the clock pulse and outputs a signal specifying the address of the P-ROM (1).

In this example, at the time of transmission of the first clock pulse, that is, at address 0, which is the branching point of the binary counter (2),
Addressing terminals 1 to A4 are all '0', and in this case, output terminal θ1 of P-ROM (1) (therefore input terminal D of latch circuit (3)) is 11M1 output terminal θ2 (
Therefore, the reset terminal R) of the binary counter (2) is M
ol, as a result P,, a latch circuit (which receives a pulse at input terminal C1 in synchronization with the application of power to ROI
The output terminal Q of 3) becomes 11w& at the first rising edge of the clock pulse Cp.

At the next clock pulse, that is, the frequency division 1 address of the binary counter (2), the address designation terminal A1 is "1", A
2-A4 is 'O', output terminal θ1 of P-ROM (1)
is 11'', and θ2 is Mol1. Therefore, the output terminal Q of the latch circuit (3) is 11w1. Also, the reset terminal R of the binary counter (2) is 101.

Second clock pulse, i.e. binary counter (2)
When the frequency division address is 2, the address designation terminal AI is '0',
A2 is 111, A3A4 are both MOM and F ROM
The output terminal θ1 of (1) is 111, and θ2 is '01,
Therefore, the output terminal Q of the latch circuit (3) maintains 111.

In this example, when the branch address of the binary counter (2) is 3, the output terminal θI of the P-ROM (1) is set to be lOl, so the output terminal Q of the latch circuit (3) is set at this point. becomes "0".

Also, in the case of branch address 4.5 of binary counter (2), output terminals θI and θ2 of P-ROM (1) are both V
Therefore, the output of the output terminal Q of the latch circuit (3) continues to maintain Wol.

When the branch address of binary counter (2) is 6.7, P-
The output θ1+i"l' of ROM (1), θ2 is 101, so the output of the output terminal Q of the latch circuit (3) becomes !, and the output of P-ROM (1) is at branch address 8 of the binary counter (2).
) becomes 105, and the output of the output terminal Q of the latch circuit (3) becomes V again.

In this way, the frequency division address of the binary counter (2) becomes O, and the output terminals θ1 and θ2 of the P-ROM (1)
When both become 11g (see FIG. 2) and a signal is sent to the reset terminal R of the binary counter (2), the address returns to 101, and the above sequence is repeated.

In the above, the output terminal Q of the latch circuit (3) is “1”
During this period, power is sent to the power switch (5) to light the light bulb (4) of the lamp.

Data writing in P-ROM (1) can be freely selected, so by appropriately designing the combination of output θ1, the required light quality can be determined by binary counter (
This can be easily obtained in conjunction with setting 2).

In the present invention, since a differentiating circuit is used in the power supply circuit, the time T is extremely short compared to the period Tc of the clock pulse Cp.
Since M is applied to the P-ROM (1) and the output during this energization time is temporarily stored in the latch circuit (3) to obtain an arbitrary timing signal, the average power consumption required by the circuit is T. Furthermore, by taking advantage of the fast operating characteristics, the TM dark time can be extremely shortened, and the power consumption can therefore be extremely reduced.

According to the present invention, inexpensive and easily available pregnancy≠4−=Fg!
By using P-ROM, it is possible to freely design the light quality, and it is possible to easily provide a signal generator for a marker light that has fast operating characteristics and low power consumption.

Incidentally, in the above description, the differentiating circuit may be replaced with a monomultiple circuit, and the latch circuit may be a D-FF.

Alternatively, similar effects can be achieved using other types of flip-flops.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a signal generator for a marker light which is an embodiment of the present invention, FIG. 2 is a truth table thereof, and FIG.
The figure is a time chart. (1)...Program read only memory, (2)
Para...Binary counter, (3)...Latch circuit,
(4)...Light bulb, (5)...Power switch. Patent applicant: Zeni Light Buoy Co., Ltd. Figure 1 B-Pr? OM completed toss specification input Ar A2/43 Ar θ, θ2 0 0 0 θ θ l θ rtoooo r θ 20 l θ θ l θ 31/ θ θ θ 0 4 00 10 θ θ P 5toro o θ ' 601 l OI θ 7/110 10 S Oθ 01 QO Fig. 3s, -111''-

Claims (1)

[Claims] A program read only memory (hereinafter abbreviated as P-ROM), a power supply circuit that supplies power for a very short time every falling or rising edge of a tarok pulse, and a P-ROM.
A medium-inary counter that specifies the OM address and uses one output of the P-ROM as the reset terminal, and a P-ROM.
Take in the output of the other side and send that output to the power supply section of JD.
1. A signal generating circuit comprising a latch circuit that holds the signal until the specified time, and generating a desired signal by the output of the latch circuit.