JPS6047748B2 - integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pattern layout structure for forming a pair of transistors having the same characteristics in a differential amplifier or the like.

In order to improve the degree of integration, MIS (Metal Insu
Integrated circuits using transistors have been developed.

Generally, a MIS transistor has an insulating film 4 on a P-type (N-type) source 2, a drain 3, and a drain region therebetween, which are provided on an N-type (P-type) semiconductor substrate 1, as shown in the cross-sectional view of FIG. It consists of a gate 5 provided through the gate. 6 and 7 are electrodes 6 connected to the source 2 and drain 3, respectively.

Generally, when forming an MIS transistor, various characteristics as designed, such as drain current ID, question voltage Vt
It is very difficult to manufacture the device to have a certain value such as h and current amplification factor β.

Moreover, even if it is formed as designed, it will change depending on environmental conditions such as temperature. FIG. 2 is an example of a circuit using MOS transistors.

T1 to T7 are MOSI-transistors, Cc is capacitance, +V
S) -VS is the power supply, ZL is the load, V, N(+), V,
N(-) is an input terminal, and Vout is an output terminal. Transistor T, ~T. A differential amplifier' is formed.
Incidentally, in such a differential amplifier, a pair of transistors T2 and T3 receiving input are required to have the same characteristics. That is, in order to eliminate the input offset of the differential amplifier, it is necessary not to form the various characteristics of the input transistors T2 and T3 exactly as designed, but to make the characteristics of both the transistors equal. FIG. 3 shows a pair of transistors T2, T as described above. FIG. 2 is a conventional general plan view when forming a 12a and 12b are drain regions connected to nodes N2 and N3 via an electrode window 16 and wirings 17 and 19.

A common source region 13 is connected to a node Ni via an electrode window 16 and a wiring 18.

15a and 15b are respective gates that connect input terminals V and N(
-), V, and N(+).

However, by forming the transistors in such a shape, it is not possible to obtain a pair of transistors having the same characteristics.

The characteristics of a MOS transistor are mainly its channel length L1.
It depends on the channel width and the impurity concentration of the substrate in the channel region. Therefore, if the shape is simply as shown in FIG. 3, various characteristics will vary due to the following reasons. (1) Variations in mask accuracy due to directionality Generally, the manufacture of MOS transistors includes many steps using multiple masks.

Due to the directionality of exposure during such an exposure process, the channel width w and channel length L of the transistor vary, and the current amplification factor β (W/L) and drain current 1 vary accordingly.
. (=β/2(■.-■Th)2:■c is gate voltage)
etc. will vary. (Ii) Variations due to the direction of expansion and contraction of the semiconductor substrate due to heat. After the heating process, such as when mounting a chip in a package, the substrate expands and contracts directionally, resulting in a decrease in channel length L1.
The width W varies.

(Iiii) Variation in ion implantation amount Ion implantation is performed in the channel portion of the MOS transistor to control Vth.

Generally, when ion implantation is performed, a large amount is implanted in the scanning part and only a small amount is implanted in other parts, resulting in a certain distribution. As a result, the impurity concentration in the channel portion varies and the threshold voltage Vth varies. An object of the present invention is to provide a pattern layout structure that can form a pair of transistors having the same characteristics without being affected by the above-mentioned variations.

A feature of the present invention is that, in an integrated circuit device in which circuits are integrated on a substrate, a source region, a drain region, and a gate region are divided into a plurality of sets.

a first transistor and a second transistor;
Gate regions of the second transistors are alternately arranged, the sources, drains, and gates of the first transistors are each commonly connected, and the sources, drains, and gates of the second transistors are each commonly connected. It's about being done. An embodiment of the present invention will be described in detail below with reference to the drawings.

Figure 4 shows the first and second transistors T2 and T3 in Figure 2.
FIG. 2 is a schematic plan view of a layout according to the present invention. There are three sets of source, drain, and gate regions of the first transistor T2 (Sal, Gal9Dal; Sa2?Ga
29Da2; S plow Ga39Da3)) Similarly, the second transistor T3 has three sets (S, l, G, l9Dbl; Sb2
9Gb29Db2; S town Gb39Db3),
Furthermore, they are arranged alternately. That is, the first transistor T2 has a source made up of Sal, Sa2, and Sa3, a drain made up of Dal, Da2, and Da3, and a gate made up of Gal, Ga2, and Ga3. The second transistor T3 has a source of S, l, Sb2, Sb3, a drain of D, l, D, 2, D, 3, and a gate of Gbl.
, Gb2, and G-Kyo. In general, the directionality of mask precision, the directionality of expansion and contraction, and the variation associated with the amount of ion implantation, which cause the variations in the various characteristics described above, have a predetermined gradient in the vertical and horizontal directions.

Therefore, if the transistors are arranged as shown in FIG. 4, the variations will cancel each other out, and variations in the characteristics of the first and second transistors will be prevented. In particular, if the ratio of the channel widths WlW2W3 of each set is formed to be 1:2:1, the horizontal and vertical symmetry will be created around the center line (not shown), and there will be gradients in the vertical and horizontal directions. It is possible to cancel out the variations with high precision. FIG. 5 is a detailed plan view of this embodiment.

Drain region Dal, Da2, D of the first transistor
a3 and the drain region D, l, D of the second transistor
b2 and Db3 are commonly connected through an AI wiring 100 (shaded area). Also gates Gal, Ga2, G
a3, Gbl, Gb9, and Gb3 are polycrystalline silicon layers 2
00 and are connected in common. The common source regions Sl, S2, and S3 are electrically connected through the diffusion layer 300, and an Al wiring is provided on each source region to lower the resistance value of the source region 7 region. As explained above, according to the present invention, variations in the characteristics of a pair of transistors can be canceled out and the characteristics of both transistors can be made equal. Very effective.

In the above embodiment, an example was shown in which each region was divided into three groups, but other methods of division are also included in the present invention. And especially if you make it line symmetrical in the vertical and horizontal directions,
Furthermore, variations can be canceled out more effectively.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of a general MIS transistor, Figure 2 is a circuit diagram showing an example of an integrated circuit using MIS transistors,
3 is a plan view showing a conventional layout structure, FIG. 4 is a schematic plan view showing an embodiment of the present invention, and FIG. 5 is a detailed plan view of FIG. 4.

Claims (1)

[Claims] 1. An integrated circuit device having circuits integrated on a substrate, including first and second transistors each having a source region, a drain region, and a gate region divided into a plurality of sets,
At least the gate regions of the first and second transistors are arranged alternately, the source, drain, and gate of the first transistor are connected in common, and the source, drain, and gate of the second transistor are connected in common. An integrated circuit device characterized in that the two are connected in common.