JPS6047678B2 - sample hold circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sample and hold circuit for a multi-purpose frequency stabilization device for television relay broadcasting.

A multi-purpose frequency stabilization device in a television relay broadcasting system requires semi-precision frequency stability, and it is desirable to keep fluctuations in the transmission frequency within ±5H2.

The above-mentioned frequency stability must be approximately 1 mV or less when the transmission frequency is viewed in the U-band and converted to the control voltage sensitivity of the voltage-controlled crystal oscillator in the local oscillation section. Therefore, in conventional sample-and-hold circuits, high-frequency noise that cannot be removed by the loop filter is added to the DC control voltage signal. FIG. 1 shows a sample and hold circuit of a multi-purpose frequency stabilizing device in a conventional television relay broadcasting system. In the figure, IN is a phase detection output signal input terminal, IN. is the control switching signal input terminal, SW is the signal switch, 1 is the loop filter, R19R29R39R5
9R69R7 is a resistor, C_o9C_l9C_s is a capacitor, IC_I, IC_2 are buffer amplifiers, OUT
is a control voltage signal output terminal. The phase detection output signal input from the phase detection output signal input terminal IN is sampled by the signal switch SW and the capacitor C_o in accordance with the control switching signal. The impedance of the sampled signal is converted by a buffer amplifier IC_I, passed through a loop filter 1, and then passed to a second buffer amplifier IC_. The level is shifted at the control voltage signal output terminal O as the control voltage signal output.
Output from UT. Here, R is the time constant of the sample and hold circuit. It is difficult to select w,・C_o (where Rsw is the ON resistance of the signal switch SW), the resistor R, which is the time constant of the loop filter 1, and the capacitor C_l, and it is difficult to select the second-order loop filter and the first-order loop filter. A mixture of loop filters 7 was used, and selection of loop response characteristics was restricted, making optimal design difficult. Therefore, the control voltage sensitivity of the voltage-controlled crystal oscillator of the local oscillator section fluctuates by more than lmV, resulting in drawbacks such as heat generation in image quality in television relay broadcasting equipment. The present invention has been made based on the above circumstances, and has two loop filters, a loop filter for sample and hold and a loop filter for removing high frequency noise, and reduces high frequency noise with respect to a DC control voltage signal. This is to maintain good frequency stability.

A detailed description will be given below with reference to the drawings. FIG. 2 shows an embodiment of the present invention.

In the figure, 2 is a loop filter, R8 is a resistor, C2, C
4 is a capacitor, and the other symbols are the same as in FIG. The phase detection output signal input from the phase detection output signal input terminal 1N1 is sampled by the signal switch SWl and the capacitor C1 in the first loop filter 1 according to the control switching signal from the control switching signal input terminal 1N2, and The first loop filter 1 reduces high frequency noise. The sampled signal is sent to a buffer amplifier ICl.
The impedance of the signal is converted by the loop filter 2, high frequency noise is removed, and the signal is applied to the buffer amplifier IC2. The level of the sampled signal is level-shifted by the part amplifier IC2 and outputted to the control voltage signal output terminal 0UT as a control voltage signal output. Here, a description will be given of the reduction of high-frequency noise with respect to the DC control voltage of the control voltage signal output using the configuration shown in the embodiment of the second loop filter. First, the capacitor C4 and the resistor R4 in the second loop filter 2 are inserted between the buffer amplifier ICl and IC2. From the configuration of R8, the loop gain at point a is R in DC terms.
A decrease in the loop gain of 4/R4+R5+R8 results in a decrease in the loop gain of R4/R4+R8 in terms of high frequency. Therefore, when viewed as a relative value, the high frequency noise is reduced relative to the DC control voltage. Moreover, the loop filter 1 determines the response characteristics of the loop filter 1 by serving as the time constant of the sample and hold circuit and the time constant of the loop filter 1, and the second loop filter 2 is also designed to reduce high frequency noise. The response characteristics of the loop filter 2 can be determined. Furthermore, since the loop filter 1 and the loop filter 2 are both second-order loop filters, the response characteristics of the loop filter 1 and the loop filter 2 can be made ideal, and the high frequency noise can be almost completely removed. can do. As explained above, in this embodiment, high-frequency noise can be removed without affecting the DC control voltage signal, so image quality degradation due to high-frequency noise can be used in the sample-hold circuit of the multi-wave common frequency stabilization device in television relay broadcasting equipment. It has the advantage of being able to suppress

The present invention can remove high-frequency noise that cannot be removed by conventional loop filters in a sample-and-hold circuit, so it can be used in a sample-and-hold circuit of a multi-wave frequency stabilizing device used in a television relay broadcasting device.

[Brief explanation of the drawing]

FIG. 1 shows a sample and hold circuit of a multiwave common frequency stabilizing device in a conventional television relay broadcasting device. FIG. 2 shows a sample and hold circuit of the multi-wave frequency stabilizing device of the present invention. 1, 2...Loop filter, INl...Phase detection output signal input terminal, I
N2... Control switching signal input terminal, SWl...
...Signal switch, ICl, IC2...Buffer amplifier, R1-R8...Resistor, CO-C4...
...Capacitor, 0UT...Control voltage signal output terminal.

Claims (1)

[Claims] 1. A sample hold circuit that samples a phase detection output signal using a signal switcher and a capacitor, and outputs the sampling signal via a first buffer amplifier IC_1, a loop filter 1, and a second buffer amplifier IC_2. , the signal switch SW_1 and the first buffer amplifier IC
A first loop filter 1 for sample and hold is connected between the resistor Ra connected to the positive input terminal of C_1 samples, and the first loop filter reduces high frequencies, and furthermore, a second loop filter 2 is inserted between the first buffer amplifier IC_1 and the second buffer amplifier to reduce high frequency noise. A sample hold circuit characterized by: 2 The configuration of the second loop filter 2 is changed to resistors R_4, R
The sample-and-hold circuit according to claim 1, characterized in that an RC warpass filter circuit comprising a capacitor C_8 and a capacitor C_4 is used.