JP2785945B2 - Satellite receiver - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a satellite broadcast receiver.

2. Description of the Related Art Conventionally, each loop filter for DQPSK demodulation and bit clock recovery of a satellite broadcast receiver is performed with one fixed constant.

Problems to be Solved by the Invention The loop filter for DQPSK demodulation and the loop filter for bit clock recovery have a close relationship with the bit error rate in digital data demodulation of a satellite broadcast receiver, and the cutoff frequency of the loop filter must be set low. For example, the bit error rate can be improved, but the pull-in range becomes narrow. As for the bit clock reproduction, it is the basic clock for PCM signal processing at the subsequent stage.
It is also the basis for data input to the final stage D / A converter, and it is difficult to increase the sampling frequency accuracy to the D / A converter while securing the pull-in range. Jitter has traditionally ignored it. However, given the accuracy of current digital audio, clock jitter can also be the jitter of the sampling frequency.
Before the D / A converter input, clock regeneration is performed again.

Therefore, there is a problem that the clock jitter causes a jitter of the sampling frequency and degrades the accuracy of the signal after the D / A conversion. This will be described briefly below.

FIGS. 8A to 8C show a sample sequence based on the sampling theorem. If the period of the sample sequence is constant and the amplitude direction is preserved, the accuracy of the signal after D / A conversion does not deteriorate as shown in FIG. 8 (a). However, if the clock jitter of the bit clock recovery has occurred, the eighth
As shown in FIG. 3B, jitter occurs in the sampling frequency obtained by dividing the frequency. Therefore, if the transmitted data in the amplitude direction is stored and D / A converted as it is, the accuracy of the D / A converted signal deteriorates due to the jitter of the sampling frequency. FIG. 8 (c) shows a sample sequence of a difference between a regular sample sequence without jitter and a sample sequence when the sampling frequency has a jitter, and shows a state of deterioration of signal accuracy.

The present invention solves the above-mentioned conventional problems, and provides a satellite broadcast receiver capable of improving the accuracy of D / A conversion by improving the sampling period by improving the bit error rate and the precision of reproducing the bit clock. It is intended to do so.

Means for Solving the Problems To solve the above problems, a satellite broadcast receiver of the present invention is provided with a video signal processing unit and a DQPSK demodulation unit to which an FM demodulation output of a satellite broadcast reception signal is input, and the DQPSK demodulation unit The relationship between the first and second loop filters and the time constants of the first and second loop filters is (first loop filter time constant) <(second loop filter time constant).
And a first switch for switching between the first and second loop filters is provided, and a 0 ° phase signal and a 90 ° phase signal of the DQPSK demodulation unit are input, thereby reproducing the bit clock and the original data. The relationship between the third and fourth loop filters and the time constants of the third and fourth loop filters is described in the differential conversion bit clock recovery unit that performs the conversion to (third loop filter time constant) <( (Fourth loop filter time constant) and a second switch for switching between the third and fourth loop filters is provided. When the frame synchronization detection protection circuit detects a frame synchronization signal included in the data, the frame synchronization monitor signal and the noise detection DC output of the C / N detection of the video signal processing unit are output. Is provided, and a first switch of the DQPSK demodulation unit is directly controlled by the output of the AND gate, so that the first loop filter is switched to the second loop filter. And when the AND gate output through the delay circuit is output together with the comparator output and the frame synchronization monitor signal, the second switch of the differential conversion bit clock reproducing unit is controlled to The third loop filter is switched to the fourth loop filter.

Operation According to the above configuration, first, the first switch is connected to the first loop filter having a fast time constant in the loop filter of the DQPSK demodulation section, and the time constant of the loop filter of the differential conversion bit clock recovery section is also large. DQPSK demodulation is performed in a state where the second switch is connected to the fast third loop filter, and then the differential conversion bit clock recovery unit operates, and the 0 ° phase signal from the DQPSK demodulation unit and the 90 ° phase signal are output. The clock locked to the phase signal and the original data obtained by differentially converting the 0 ° phase signal and the 90 ° signal are output from the differential conversion bit clock reproducing unit, and then the frame synchronization in the PCM signal processing unit is performed. The detection protection circuit performs detection protection of a frame synchronization signal included in the data, and outputs a frame synchronization monitor signal of “H” or “L”. When this frame synchronization monitor signal is detected, DQPSK demodulation and bit clock recovery are operating reliably. At this point, the “H” signal of the frame synchronization monitor signal causes the DQPSK demodulation unit loop filter to operate. The stability of DQPSK demodulation is improved by switching the constant to the second loop filter which is much slower by the first switch, and after a certain time delay, the time constant of the loop filter for bit clock recovery Is switched by the second switch to the fourth loop filter which is much slower, thereby improving the bit error rate and improving the stability of the bit clock reproduction. Is improved.

Also, for example, when frame synchronization is lost,
Immediately, the time constants of the respective loop filters of the DQPSK demodulation unit and the differential conversion bit clock recovery unit are switched to the first one by the first and second switches, and the data is drawn again.

Furthermore, when the C / N ratio is deteriorated and noise is increased, the above operation is repeated and vibration may occur.
The DC value (noise amount) of C / N detection and output is compared by the comparator, and the time constant of each loop filter of the DQPSK demodulation unit and the differential conversion bit clock recovery unit is extremely slow by the comparator output signal. By taking an AND gate with the frame synchronization monitor signal so as not to switch, bit clock reproduction with extremely high precision can be performed.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a satellite broadcast receiver showing one embodiment of the present invention. In FIG. 1, the FM demodulated output signal a
The signal is input to a BPF (band-pass filter) 1 of 5.727272 MHz, and is simultaneously input to the video signal processing circuit 3 and the BPF 4 of the video signal processing unit 2. The BPF 4 is a band pass filter for extracting a noise component from the FM demodulated output signal a. The output of the BPF 4 is input to the amplifier 5 and amplifies the extracted noise as necessary for detection. The detector 6 to which the output of the amplifier 5 is input is for obtaining a DC output (detection output) according to the magnitude of the noise power. The video signal processing circuit 3 is for removing components of the energy spread signal peculiar to satellite broadcasting.

As shown in FIG. 2, the FM demodulated signal a has a video luminance component A, a video color subcarrier component (center frequency is 3.58 MHz) B, and an audio subcarrier component (center frequency is 5.7).
27272 MHz) C and a harmonic D of the image color component. Also, as shown in FIG. 3, the demodulated noise generally increases in noise power as the frequency increases, as generally called triangular noise. Therefore, the BPF 4 for extracting only the noise component except the demodulated signal component has a center frequency of about 8 MHz and a bandwidth of 1 MHz.
It is desirable to select about z. For example, if the center frequency of this BPF4 is selected to be 11 MHz or higher, the demodulated signal component can be reduced.However, the frequency band of the demodulated output of the FM demodulator of the BS tuner is generally from 50 Hz to about 8 MHz. Is not guaranteed, so that the output level of the noise component is lowered. At this time, it is necessary to increase the gain of the amplifier 5 at the subsequent stage, and the variation in the level of the noise component is undesirably increased.

The noise extracted by the BPF 4 is amplified by the amplifier 5 to a level sufficient for detection by the detector 6 using a diode, input to the detector 6 and detected. When the amplifier 5 has no amplitude limiting function, the detection output rapidly increases when the C / N ratio is deteriorated as shown in FIG. 4 when the C / N ratio of the human-powered signal is changed. In the case of satellite broadcasting, C / N
It is considered that a so-called threshold phenomenon occurs when the ratio is about 9 dB or less, and the noise level of the demodulated output sharply increases. If the detection output as shown in FIG. 4 is displayed as it is, the linearity of the display output with respect to the change in the C / N ratio is poor, and the range of the C / N ratio that can be displayed is limited. For this reason, it is necessary to devise an amplifier.If the amplitude of the noise is limited to a certain value by giving an amplitude limiting effect to the gain of the amplifier, the linearity of the detection output with respect to the C / N ratio is improved. As shown in FIG.

The amplifier 5 having the amplitude limiting function can be realized by using a transistor differential amplifier as shown in FIG. Here, the bias resistor _{R 1 · R 2 · R 3} · R 4 are transistors _{Q 1 · Q 2, R 5} · R 6 is the load _{resistance, R 7 · R 8 · R} 9 denotes an emitter resistor, C
1, C2 is a coupling capacitor. As shown in FIG. 7, the input / output characteristics of this differential amplifier are such that the gain is constant in the region where the input is small, but does not increase beyond the potential difference between the power supply voltage and the emitter voltage even when the output amplitude increases. As shown in FIG. 7, there is a gain saturation region E. If this amplifier is used as the last stage of the noise amplifier 5, the noise amplitude does not become larger than a certain value, so that the noise power input to the detector 6 is accompanied by the deterioration of the C / N ratio due to the threshold phenomenon. As a result, the detection output as shown in FIG. 5 can be obtained.

Thus, by inputting the detection output b proportional to the noise power obtained by the detector 6 to the comparator 7, the C / N ratio does not deteriorate at this time, and a sufficient C / N ratio can be secured. Then, an “H” level signal is input to the AND gates 8 and 9 as the output of the comparator 7.

Next, the output of the 5.727272 MHz BPF1 is input to the DQPSK demodulation unit 10, and at this time, the switch 11 is connected to the loop filter 12 having the faster time constant, and performs the demodulation of the DQPSK demodulation unit 10. Thereafter, the 0-degree phase signal d and the 90-degree phase signal e as outputs from the DQPSK demodulation unit 10 are output as demodulated signals, and the 0-degree phase signal d and the 90-degree phase signal e are output from the differential conversion bit clock reproduction unit 13. Is input to At this time, switch 14
Selects the loop filter 15 having the faster time constant, and performs bit clock recovery and differential conversion. Data f from differential conversion bit clock recovery unit 13
And the clock g are input to the PCM signal processing unit 16, and the data f input to the PCM signal processing unit 16
Is input to the frame synchronization detection protection circuit 18. The frame synchronization detection and protection circuit 18 detects a frame synchronization signal included in the data f, and if there is a frame synchronization signal, performs frame synchronization while protecting the lack thereof. At this time,
The frame synchronization monitor signal c becomes "H" level. The "H" synchronous monitor signal c is ANDed with the comparator output signal by the AND gate 8, and the output of the AND gate 8 becomes "H" level. Switch to. Next, after the output of the AND gate 8 is delayed by the delay circuit 20, the AND of the frame synchronization monitor signal c is obtained by the AND gate 21, and then the output of the AND gate 21 is compared with the output of the AND gate 21 by the comparator The output signal is ANDed, and the output of the AND gate 9 switches the switch 14 of the differential conversion bit clock recovery unit 13 to the loop filter 22 having a slow time constant. As described above, after the PCM signal processing unit 16 enters the synchronous state, the DQPSK demodulation unit 10 and the differential conversion bit clock reproduction unit 1
The respective loop filters 12 and 15 are switched to the loop filters 19 and 22 having slow time constants by the switches 11 and 14, respectively.

Here, if the output of the comparator 7 changes from "H" level to "L" level (when the C / N ratio is deteriorated), the AND gates 8, 9 are immediately set so that the time constant of the loop filter is increased. , 21 are switched.
Further, the delay circuit 20 and the AND gate 21 are connected to the DQPSK demodulation unit 1
After switching to the slower time constant of the loop filter 19 of 0, the loop filter of the differential conversion bit clock recovery unit 13
It is for switching to the slower time constant of 22.

Effects of the Invention As described above, according to the present invention, a noise component is extracted from the FM demodulated output and detected, so that an output proportional to the noise power is obtained. By converting the time constant of each loop filter of the conversion bit clock regeneration unit from a fast time constant to a slow time constant by a frame synchronization monitor signal, the bit error rate is improved and the accuracy of the bit clock regeneration is improved. The accuracy of the digital-to-analog conversion is improved by improving the accuracy of the sampling period to achieve the improvement, and the practical effect is very large.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a satellite broadcast receiver according to one embodiment of the present invention, FIG. 2 is a spectrum diagram of a demodulated signal at a demodulated output of a Bs tuner, and FIG. 3 is a spectrum of demodulated noise at the demodulated output. Fig. 4 is a characteristic diagram showing the relationship between noise detection output and C / N ratio when an amplifier having no amplitude limiting effect is used. Fig. 5 is noise when an amplifier having an amplitude limiting effect is used. FIG. 6 and FIG. 7 are circuit diagrams and an input / output characteristic diagram showing an example of an amplifier having an amplitude limiting function, and FIG. 8 is a jitter diagram in bit clock reproduction. FIG. 7 is a diagram for explaining the quality of an audio reproduction signal due to jitter in an audio sampling period due to the above. 1 ... 5.727272MHz BPF, 2 ... Video signal processing unit, 3 ...
... Video signal processing circuit, 4 ... BPF, 5 ... Amplifier, 6 ...
... Detector, 7 ... Comparator, 8,9,21 ... And gate, 10 ... DQPSK demodulator, 11,14 ... Switch, 12,15,1
9, 22: loop filter, 13: differential conversion bit clock recovery unit, 16: PCM signal processing unit, 17: descrambling circuit, 18: frame synchronization detection protection circuit, 20: delay circuit, a …… FM demodulation output signal, b …… Detection output signal, c
…… Frame synchronization monitor signal, d …… 0 ° phase signal, e…
… 90 ° phase signal, f… data signal, g… clock signal.

Claims (1)

(57) [Claims] A video signal processing unit to which an FM demodulated output of a satellite broadcast reception signal is input and a DQPSK (differential four-phase phase shift keying) demodulation unit are provided, and the DQPSK demodulation unit has a first and a second loop. A first filter and a second filter;
The relationship between the time constants of the loop filters of (1) and (2) is configured such that (first loop filter time constant) <(second loop filter time constant), and a first switch for switching between the first and second loop filters is provided. , 0 of the DQPSK demodulation unit
A differential conversion bit clock recovery unit for receiving the {phase signal and the 90} phase signal and recovering the bit clock and converting the data into data is provided. A loop filter is provided, and the relationship between the time constants of the third and fourth loop filters is set as (third loop filter time constant) <(fourth loop filter time constant).
A second switch for switching between the third and fourth loop filters; a PCM signal processing unit to which a clock and data of the differential conversion bit clock recovery unit are input; A descrambling circuit for inputting the data and a frame synchronization detection and protection circuit; and a comparator for inputting a noise detection DC output of C / N (signal power to noise power ratio) detection of the video signal processing unit. When the frame synchronization detection and protection circuit detects a frame synchronization signal included in the data,
An AND gate to which the frame synchronization monitor signal and the output of the comparator are input is provided, and the output of the AND gate directly controls the first switch of the DQPSK demodulation unit to output the first switch from the first loop filter to the second switch. 2 and controls the second switch of the differential conversion bit clock recovery unit when the AND gate output through the delay circuit is output together with the comparator output and the frame synchronization monitor signal. A satellite broadcast receiver configured to switch from the third loop filter to the fourth loop filter.