JPS6047517A - Automatic selection type logical circuit for clock signal - Google Patents

Abstract

PURPOSE:To improve operating performance by providing plural clock signals which differ in timing, and selecting a clock signal matching with the signal delay time of a section and correcting the timing of the clock signal. CONSTITUTION:A clock signal T3 from a generating circuit 1 drives a front- stage latch S11, and a signal T4 is inputted to a selecting circuit 2 to control the selection of a clock signal. A signal T5 drives rear-stage latches E11 and E12 of a normal path, and a signal T6 drives latches E11 and E12 of a path having a long delay time between E11 and E12.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to logic circuits, and more particularly to a lock signal automatic selection type logic circuit suitable for improving the performance of logic circuits that operate synchronously.

[Background of the invention]

FIG. 1 shows a standard configuration of a synchronous logic circuit that operates synchronously by applying a clock signal to a front-stage latch and a rear-stage latch. In the figure, after the signals of the front-stage latches 81 and S2 are outputted by the clock signal T1, they are propagated through the combinational circuit CS, and then the signals of the rear-stage latches E are output by the clock signal 'l.
It is stored in l,In. The path from the front stage latches 81, 82 to the rear stage latches El, E2 includes Sl-, B1. 8
1-Fi2, 82-El, 82-B2 (7) 4 types of Kaal. The state of the delay time of the cholera path is shown in the timing chart diagram of FIG. The delay time is the intermediate combinational circuit C.
It depends on the delay time of S.

In the above-mentioned synchronous logic circuit, in order to ensure synchronous operation, a clock signal TI is applied to the front stage latches 81 and 82.
After entering, the rear latch El.

The timing time D2 of the clock signal T2 entering B2 had to be later than the delay time of the sl-g2 route, which is the maximum delay time of the route.

However, the signal on the 81-B2 path is not always valid. For example, as shown in FIG.
All gates G1 to G4 on the path from 1 to latch E2 are:
If it is an AND gate, the output signal of latch S1 is 'O
In the case of ``, the input signal of the latch E2 becomes @O'' regardless of the inputs i1 to i8. In other words, when the output word of latch S1 is 4 consecutively outputting 10'', the timing of the clock signal T2 of the subsequent latch E2 may be shorter than the delay time D2 in FIG. 2. However, in the past, the clock signal T2 was normally transferred to the subsequent latch E2 at the timing of the delay time DZ, so the clock signal timing time was determined by the maximum path signal delay time between the latches. This has the disadvantage that the operational performance of the circuit is limited.

[Purpose of the invention]

The present invention has been made in view of the above points, and an object of the present invention is to provide an automatic clock signal selection type logic circuit that improves operating performance by selecting a clock signal that matches the signal delay time of a section.

[Summary of the invention]

The key point of the present invention is to prepare a plurality of clock signals with different timings in a synchronous logic circuit that is controlled by applying a clock signal to the front-stage latch and the rear-stage latch, and to automatically select the clock signal that matches the signal delay time of the section. ,
Thereafter, the timing of the clock signal is corrected using the selected clock signal.

[Embodiments of the invention]

An embodiment of the present invention will be described below based on the drawings.

FIG. 4 is a block circuit diagram showing an automatic clock signal selection type logic circuit according to the present invention. In the same figure, 1 is a clock generation circuit, and as shown in FIG. 6, a lock signal T8 is generated.
~T6 is generated. The clock signal T8 is supplied to the front stage latch 8.
11, and the clock signal T4 is input to the clock selection circuit 2 to control the selection of the clock signal. Clock signal T5 is output from the subsequent latch Ell of the normal path.
.

(3) The clock signal T6 is used to drive the rear latch Bi1°B12 of the path where the delay time between the front latch 811 and the rear latch ELL B12 is large. Since there are a large number of gate stages and a large delay time from the front stage latch 811 to the rear stage latch Bll, the rear stage latch Ell usually needs to be driven by the clock signal T6. However, since the gates Gll to G14 between the front-stage latch Sll and the rear-stage latch El1 are AND gates, when the output signal of the front-stage latch 811 is continuously θ'', the rear-stage latch Flill is driven by the clock signal T5 faster than the clock signal T6. There is no problem even if G11 to G14 are OR gates, and the output signal of the front latch 81 is continuously @
When outputting 1'', there is no problem even if the latter latch Bll is driven quickly or with the 4-way signal T5.

FIG. 5 is a block circuit diagram showing another clock signal automatic selection type logic circuit according to the present invention. In the same figure, l,
Similarly to FIG. 4, 2 indicates a clock generation circuit and a clock selection circuit, respectively. From front stage latch 821 to rear stage latch B
The path leading to i21 has a large number of gate stages and normally needs to be driven by the clock signal T6 shown in FIG. However, since the gate 20 is an AND gate, if the output signal value of the front stage latch 822 continuously outputs "0", there is no problem even if the rear stage latch E21 is driven by the clock signal T5 faster than the clock signal T6. In this way, the latter latch Ell in FIG. 4 and the latter latch E21 in FIG. 5 are driven by the clock signal T.
Selecting whether to drive with 5 or T6 is
This is a clock selection circuit 2.

Details of the clock selection circuit 2 are shown in FIG. In the figure, B81 is a latch that stores the output signal stored in the pre-stage latch 811 of FIG. 4, and is driven by the clock signal T4 shown in FIG. 6. That is, the signal value of the front-stage latch 811 in FIG. 4 is stored until the clock signal T4 is input.

Ga4 is an exclusive OR gate, and if the signal value of latch L81 and the signal value of front stage latch 811 in FIG. 4 are different, 11
''. 08B is a NOR gate that performs the logical sum of the signal value of the previous stage latch SL and the output of the exclusive OR gate G81 and inverts it. 08B and G84 are AND gates.
G85 is a 0 gate, and if the output signal value of the front stage latch 811 in FIG.
output signal T4, and the output signal value of the previous stage launch S11 is "
1'', if the signal value has changed from the previous signal, the clock signal T6 inputted through the gate 84 is output. In other words, the clock signal T6 input through the gate 84 is output.
is given either clock signal T5 or T6. The output signal of the NOT circuit 1 is used to correct subsequent clock signals when the zero gate G85 outputs the clock signal T6, and is input to the clock generation circuit 1 shown in FIG. 4.

When the above clock selection circuit is used in the logic circuit shown in FIG. 5, the output signal of the front-stage latch 822 shown in FIG.
The output of R gate G85 is connected to terminal 4 of rear stage latch E21,
The output 5 of the NOT circuit N81 is connected to the terminal 5 of the clock generation circuit.
When the output signal value of the front stage latch 822 is continuously '0', the clock selection circuit 2 selects the clock signal T5 and drives the rear stage latch E21. If the value is 1” or the signal value changes from the previous signal, the clock signal T
Select 6.

Figure 7 shows the details of the clock generation circuit, and Figure 9 shows the details of the clock generation circuit.
Generates the timing signal shown in the figure. When the output 5 of the NOT circuit N81 of the clock selection circuit 2 is '1', the AN
D gate G41.0 Gate G4B, NOT circuit N41
．． A loop composed of delay elements DLl generates a rectangular wave 52.
is output, and a rectangular waveform 54 is output from the AND gate G41.

This square wave 54. However, NOT circuit N482, ANDNO
The pulse width of the pulse 57 is determined by a loop made up of the gate and the delay element DL8. This pulse 57 causes buffers 841 to B44 and delay elements DL4 to DL7 to
Clock signals T8 to T6 are outputted via the circuit. That is, when the clock selection circuit 2 selects the clock signal T5, the clock generation circuit (power 1) generates the clock signals T8 to T6 shown in FIG.

Still, when the output of NOT circuit 1381 becomes "0", AN
A rectangular waveform 5 is generated by a loop composed of a DNO gate, an OR gate 43, a NOT circuit N41, and a delay element D'L2.
8 is output, and a square wave 55 is output from the AND game) G42. This rectangular wave 55 causes the pulses 57 to
is output, and clock signals T8 to T6 are output. That is, when the clock selection circuit selects the clock signal T6, the clock signal is generated at a period between b and c of the pulse 57.

As a result of the above, the front stage latch Sll in FIG.
□ When outputting P+, the second stage latch Ell is driven by the fast clock signal T5, and when the first stage latch Sll continuously outputs W11 or when the output signal changes, it is driven by the clock signal T6. As a result, (8) the operational performance of the logic circuit is improved compared to the conventional synchronous logic circuit which is always driven by the clock signal T6.

FIG. 8 shows another embodiment using a plurality of clock selection circuits. In the figure, latches L1 to L8. Latch L2 to latch L4. The paths from latch L4 to latch L7 are paths with long delay times, and clock selection circuits 2-1.2-2.2-8 are provided for selecting clock signals, respectively.

T7~T1? , are clock signals from the clock generation circuit 1, and are output at the timing shown in FIG.

The clock selection circuit 2-1.2-2 has a clock signal T.
9. TIO, Tll are input, and clock signals TIO,
One of the Tlls is selected. The clock signal T9 is
Like the clock signal T4 in FIG. 8, it becomes a control signal. The clock selection circuit 2-8 receives a clock signal T7. One of T8 is selected. Clock signal TIB becomes a control signal. OR game) 051 is each clock selection circuit 2-
When one of the selection circuits 1 to 2-8 selects a slower timing, that is, a clock signal T8t times Tll, the clock generation circuit 1 outputs a signal for correcting the timing.

〔Effect of the invention〕

As explained above, the clock signal automatic selection type logic circuit according to the present invention prepares a plurality of clock signals with different timings and automatically selects the clock signal suitable for the signal state of the path. It has the excellent effect of improving the operating performance of synchronous logic circuits.

[Brief explanation of drawings]

Figure 1 is a block diagram showing a conventional synchronous logic circuit; Figure 2 is a block diagram showing a conventional synchronous logic circuit;
The figure is a timing chart showing the timing, No. 8.
4 and 5 are block circuit diagrams showing an embodiment of the clock signal-5g1h selection type logic circuit according to the present invention, and FIG. Figure 5 is a timing diagram to explain the operation of the logic circuit, Figure 7 is a block circuit diagram showing the clock circuit, and Figure 8 is a timing diagram to explain the operation of the logic circuit.
9 is a block circuit diagram showing the clock selection circuit, FIG. 9 is a timing diagram for explaining the operation of the clock generation circuit of FIG. 7, and the slo diagram is another implementation of the clock signal automatic selection type logic circuit according to the present invention. Block circuit diagram showing an example, 1st
FIG. 1 is a timing chart for explaining the operation of the logic circuit shown in FIG. 10. 1-? 0 Tsuk generation circuit, 2.2-1.2-2.2-
8...Clock selection circuit. Representative Patent Attorney Akio Takahashi Figure 5 Figure 6 Figure 6 Fang Figure 7 Figure 8 87

Claims (1)

[Claims] (1) In a synchronous logic circuit that is controlled by giving a clock signal to the front-stage latch and the rear-stage latch, there is a clock generation circuit that generates multiple clock signals with different timings, and a clock generation circuit that generates multiple clock signals with different timings, and a clock generation circuit that generates multiple clock signals with different timings, and a clock generation circuit that generates multiple clock signals with different timings, and a clock generation circuit that generates multiple clock signals with different timings, and a clock generation circuit that generates multiple clock signals with different timings. A clock selection circuit is provided which recognizes the change state of the signal in the middle of the route and selects the clock signal for the subsequent latch, and the core clock selection circuit selects the clock signal that matches the signal state of the route from the plurality of clock signals emitted from the clock generation circuit. A clock signal automatic selection logic circuit characterized in that a clock signal is selected.