JPH08162946A - Counter circuit - Google Patents

Abstract

PURPOSE: To provide a counter circuit for turning the outputs of all flip-flops to be the same at the time of supplying power, performing an arithmetic processing at a high speed without malfunctions and evading the complication of circuit constitution in the counter circuit constituted of a Johnson counter circuit. CONSTITUTION: The Johnson counter circuit is provided with a logic circuit part 2 connected to the outputs of the respective flip-flops FF1 and FFn positioned at both end parts of the column of the plural serially connected flip-flops FF1 to FFn. The output of the logic circuit part 2 is fed back to a flip-flop group (FP2 to FF(n-1)) other than the respective flip-flops positioned at both end parts of the Johnson counter circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a counter circuit, and more particularly to an improvement of a counter circuit constructed by using a Johnson counter circuit.

[0002]

2. Description of the Related Art Conventionally, a counter circuit has been used as an indispensable circuit in the design of a circuit such as an LSI. As such a counter circuit, one having a configuration in which a plurality of flip-flops (FF1 to FFn) are serially connected is generally used. Among them, as shown in FIG. 22, at least three flip-flops are used. In the state where the flip-flops are serially connected, the output of the flip-flop FFn at the final stage of the flip-flop group connected to the serial is inverted and connected to the input terminal of the flip-flop FF1 at the first stage. The Johnson counter circuit configured as described above is frequently used.

That is, in the conventional Johnson counter circuit shown in FIG. 22, when the number of flip-flops is n, the output of each flip-flop is 1 / n of the clock.
It is configured so that the divided waveforms of (1) and (2) are shifted by one cycle of the clock and output. As another specific example of the counter circuit in the related art, as shown in FIG. 23, a plurality of sets (n sets) each including a selector SE and a flip-flop FF are serially arranged. However, it is configured to convert the parallel data taken in only by the rising edge of the clock signal to serial and output it.

On the other hand, FIG. 24 shows another specific example of the conventional counter circuit, in which a plurality of toggle flip-flop groups (FF1 to FF4) are serially connected to each other, and a predetermined number. (N-1) th toggle flip-flop FF1
Is input to the clock signal input terminal of the toggle flip-flop of the nth stage, and thereby data having a plurality of frequency division ratios is output in parallel from serial data.

That is, as an arithmetic element using a flip-flop, it is used in various fields such as various counter circuits including a Johnson counter circuit, a multiplexer circuit or a demultiplexer circuit, and the like. One of the drawbacks from the characteristics is that it is uncertain whether a "H" level signal or a "L" level signal will be output at the output when the flip-flop is powered on. In each of the arithmetic circuits described above in which a plurality of flip-flops are serially connected, the output level of each flip-flop is not constant, so that a desired operation is not executed.

That is, when it is assumed that four flip-flops (FF1 to FF4) are used in the counter circuit shown in FIG. 22, a desired operation at the output level of each flip-flop in the counter circuit is performed. Is, for example, as shown in Table 1.

[0007]

[Table 1]

That is, in the above counter circuit,
The output of each flip-flop is 1 of the cycle of the clock signal.
The cycle becomes / 4, and the phases are shifted by one clock cycle. That is, in the above specific example, each output of the flip-flops FF1 to FF4 is a normal desired operation unless it takes any one of the states (1) to (8) in Table 1 above. Is something that cannot be executed.

On the other hand, when the power supply is turned on to a state other than any of the above states, for example, as shown in the state (1) of Table 2, the flip-flops FF1 to FF4 are
If you start from the state 0, 1, 0, 1
The operation is as shown in Table 2, and the output of each flip-flop does not have a cycle of 1/4 of the cycle of the clock signal.

[0010]

[Table 2]

In the prior art, in order to solve the problem of such flip-flop, by inputting a reset signal from an external terminal, the output state of each flip-flop is forcibly changed to the state (1) in Table 1. In order to attain the state (5), the operation was performed so as to be either the "L" level or the "H" level. In such a method, it is necessary to provide an extra pin for the external terminal, and it is necessary to configure a system for inputting a reset signal from the outside every time the power is supplied, which makes the operation complicated and inconvenient. At the same time, there was a problem that the cost would rise.

Further, in the conventional method as shown in FIG. 23, when the system clock has a high frequency, it becomes necessary to increase the operating speed of the shift register. There is a problem in that it is necessary to increase the power and thus increase the power consumption. On the other hand, in the conventional method as shown in FIG. 24, since the frequency division output in each flip-flop is delayed by the number of passing stages of the flip-flop,
There was also a problem that it was difficult to match the timing.

Further, as one method for solving such a problem, there is an automatic setting circuit system of a shift counter.
Although disclosed in Japanese Unexamined Patent Publication No. 8-82761, since the circuit configuration is complicated in such a method, there are problems such as an increase in circuit area and an increase in manufacturing cost, which is not practical.

[0014]

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks of the prior art, and in various counter circuits composed of a plurality of flip-flops including a Johnson counter circuit, when the power is turned on. By providing the outputs of all the flip-flops to be the same, a counter circuit that does not malfunction and can perform arithmetic processing at high speed and that avoids the complexity of the circuit structure is provided.

[0015]

The present invention employs the following technical configuration to achieve the above object. That is, as the basic configuration of the counter circuit according to the present invention, at least three flip-flops are serially connected, and the output of the last-stage flip-flop is inverted to the first-stage flip-flop. In the Johnson counter circuit configured to be connected to the input terminal, the logic circuit section connected to the output of each flip-flop located at both ends of the serially connected flip-flop row is The counter circuit is provided and is configured to feed back the output of the logic circuit section to a group of flip-flops other than the flip-flops located at both ends of the Johnson counter circuit.

[0016]

Since the counter circuit according to the present invention employs the technical configuration as described above, the logic of the output of the first-stage flip-flop and the output of the last-stage flip-flop in the Johnson counter circuit is considered. Then, by using the result of the logic, all the remaining flip-flops are forcibly and automatically set or reset, and the outputs of all the flip-flops are set to “H” level or “L”. It is controlled so that it is aligned with any of the levels.

Therefore, in the counter circuit according to the present invention, at the same time when the power is turned on or after an extremely short time,
Since the outputs of all the flip-flops forming the counter circuit are aligned at a constant level, it is possible to accurately execute a predetermined operation in a short time.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific examples of the counter circuit according to the present invention will be described in detail below with reference to the drawings. That is, in FIG.
3 is a block diagram showing an example of a configuration of a specific example of a counter circuit according to the present invention, in which at least three flip-flops (FF1 to FFn) are serially connected, and the flip-flop at the final stage In the Johnson counter circuit configured such that the output Q of FFn is inverted and connected to the input terminal D of the first-stage flip-flop FF1, a plurality of serially connected flip-flop arrays FF1 to FFn The logic circuit section 2 connected to the outputs of the flip-flops FF1 and FFn located at both ends of the logic circuit section 2 is provided.
The counter circuit 1 is configured to feed back the output of the above to the flip-flop groups (FF2 to FFn-1) other than the flip-flops located at both ends of the Johnson counter circuit.

That is, the counter circuit 1 according to the present invention shown in FIG. 1 basically only adds the logic circuit portion 2 and does not make the circuit configuration so complicated as compared with the conventional circuit configuration. Moreover, it is possible to realize a target counter circuit. The logic circuit section 2 in the present invention is not particularly limited, but for example, an AND gate circuit, N
It is possible to use conventionally used logic circuit elements such as an AND gate circuit, an OR gate circuit, and a NOR gate circuit.

Further, in the present invention, the logic circuit section 2 concerned.
Is a flip-flop F located at both ends of a plurality of serially connected flip-flops FF1 to FFn.
The outputs of F1 and FFn are respectively input, and after performing a predetermined logical operation, the output is fed back as a control signal to either the set terminal or the reset terminal of the remaining flip-flop group (FF2 to FFn-1). ,
The respective flip-flops FF2 to FFn-1 are forcibly and automatically matched with the same output level.

Here, when the logic circuit section 2 inputs output signals of the same level from the flip-flops FF1 and FFn, a predetermined logic output is supplied to each of the flip-flops FF2 to FFn-1. By setting, all flip-flops will be set to the same output level. FIG. 2 is a block diagram showing a first concrete example of the counter circuit 1 according to the present invention. In the concrete example, the AND circuit is connected to the logic circuit section 2.
An example of using the gate circuit 21 is shown.

That is, in this example, the output of the AND gate circuit 21 is the flip-flops FF2 to FF.
It is supplied to the n−1 set terminal S. In this example, when the "H" level output signal is input from the flip-flops FF1 and FFn, the AND gate circuit 21 outputs the "H" level logical output to the respective flip-flops FF2 to FFn-. Since it is supplied to the set terminal S of 1, the output level of each of the flip-flops FF2 to FFn-1 is also set to the "H" level, and therefore all the flip-flops FF1 to FFn of the counter circuit 1 are set.
Output is unified to the “H” level and is automatically set.

Next, FIG. 3 is a block diagram showing a second concrete example of the counter circuit 1 according to the present invention. In this concrete example, the NAND circuit is provided in the logic circuit section 2.
It shows an example of using the gate circuit 22. That is,
In this specific example, the output of the NAND gate circuit 22 is supplied to the reset terminals R of the flip-flops FF2 to FFn-1.

In this embodiment, when the "L" level output signal is input from the flip-flops FF1 and FFn, the NAND gate circuit 22 outputs the "H" level logical output to the respective flip-flops FF2. To the reset terminal R of the flip-flops FF2 to FFn-1, the output levels of the flip-flops FF2 to FFn-1 are also set to the "L" level. The outputs are unified to the "L" level and automatically reset.

That is, in the above-described specific example of the present invention, the counter circuit 1 outputs the outputs of the flip-flops FF2 to FFn-1 according to the output results of the flip-flops FF1 and FFn at both ends after the power is turned on. It is possible to automatically draw the level to the desired state. According to the present invention, if the outputs of the flip-flops FF1 and FFn at both ends of the Johnson counter circuit are both "L" level, the outputs of the internal flip-flops must be all "L" level during normal operation. I won't.

On the contrary, the flip-flops FF1 at both ends
If the outputs of FFn and FFn are both at "H" level, all the outputs of the internal flip-flops must be at "H" level during normal operation. Therefore, if the outputs of the flip-flops FF1 and FFn at both ends are both at "L" level, the remaining flip-flops FF2 to FFn-1
The output of all flip-flops can be set to the “L” level by resetting.

If the outputs of the flip-flops FF1 and FFn at both ends are both at "H" level, the remaining flip-flops FF2 to FFn-1 are reset to output the outputs of all the flip-flops. It can be set to H "level. This operation is because the outputs of both ends are at the same level no matter what the outputs of the flip-flops after the power is turned on.

The operation will be described below. That is, the Johnson counter circuit has a configuration in which the output of the flip-flop is inverted and input to the first stage (left end) at the final stage (right end), and the output of the first flip-flop is sequentially shifted to the final flip-flop as it is. . Now, if the outputs of the flip-flops at both ends are both at "L" level, the remaining flip-flop groups FF2 to FFn- on the internal side
In the case of the configuration in which 1 is reset, if it takes the longest time until the "L" level signal appears at the outputs of the flip-flops at both ends, 1,0,1,0,0 ,.
It is 1,0.

1,0,0,0, ... 0,0,0,
Since 1, 1, 0, 0, 0, ... 0, 0, 0 is a correct operation, the output of each flip-flop after power-on is 1,
Even if it starts at 0, 1, 0, 0, ... 0, 0, 0, if the data shifts one bit to the right and the data at the right end is inverted and appears at the left end, ,
1,1,1,1,1, ... 1,0,1, then 0,1,1,1,1, ...
Then, all the inside is reset and 0,0,0,0,
0, ..., 0, 0, 0.

Next, FIG. 4 shows a third concrete example of the counter circuit 1 according to the present invention. That is, in the third specific example of the counter circuit 1 according to the present invention, at least three flip-flops are serially connected, and the output of the last-stage flip-flop FFn is inverted. In the Johnson counter circuit configured to be connected to the input terminal D of the first-stage flip-flop FF1, part of the flip-flop group is composed of flip-flops having two data input terminals. In addition, the logic circuit section 2 connected to the outputs of the respective flip-flops located at both ends of the plurality of serially connected flip-flop arrays is provided, and the output of the logic circuit section 2 is provided to the Johnson counter circuit. Flip-flop group FF3 ′ to FFn ′ having the two data input terminals
A counter circuit is shown configured to provide feedback to one of the data input terminals.

As the configuration of the logic circuit section 2 used in this example, the same logic operation circuits as those in the above-mentioned first and second examples can be used. Further, the flip-flop FFn ′ having two data input terminals used in this example is the usual first data input terminal D1, clock input terminal C, reset terminal R, set terminal S and output terminal. Unlike Q, it has a second data input terminal D2 to which the output of the logic circuit section 2 is connected.

The flip-flop FFn 'having two data input terminals used in this embodiment is preferably
In the Johnson counter circuit constituting the counter circuit 1, the clock signal may be arranged at all the flip-flop FF positions after a predetermined number of flip-flops counting from the flip-flop FF1 to which the clock signal is input first. desirable.

In this specific example, among a plurality of flip-flop groups constituting the Johnson counter circuit,
The two flip-flops FF1 and FF2 at the next stage to which the clock signal is input first are left as they are, and all the remaining flip-flops FF3 to FFn are flip-flops having the two data input terminals. FF3 'to FFn'.

Of course, in this specific example, all the flip-flops may be formed by flip-flops having two data input terminals, but as described above, the control signal from the logic circuit section is supplied. The receiving flip-flops are preferably the flip-flops from the first to the third flip-flops. In this specific example, the logic output signal of the logic circuit section 2 is different from that in the specific example described above.
The control signal is also output to the flip-flop in the last stage of the flip-flop string.

FIGS. 5 and 6 are block diagrams for explaining another mode of the third embodiment of the present invention shown in FIG. That is, in FIG.
As an example of modification of the flip-flop FFn ′ having two data input terminals in FIG. 4, an AND gate circuit 21 is used as the logic circuit section 2 of FIG. Logic circuit 51,
For example, an OR gate circuit is connected, one input of the OR gate circuit 51 is connected to the output Q of the flip-flop FF2 at the previous stage, and the other input is connected to the output of the logic circuit section 21.

That is, in the above specific example, the OR gate circuit is externally attached to the data input terminals of the flip-flops at least from the third flip-flop FF3 to the final flip-flop FFn. 51 is provided so that when the outputs of the first-stage and final-stage flip-flops are both at "H" level, the outputs of all flip-flops are automatically initialized to "H" level. Will be converted.

Further, in FIG. 6, the logic circuit section 2 of FIG.
The OR gate circuit 23 is used as
Flip-flop FFn ′ having a plurality of data input terminals
As a modification example, another logic circuit 52, for example, an AND gate circuit is connected to the data input terminal of the normal flip-flop FF3, and one input of the AND gate circuit 52 is connected to the output Q of the previous flip-flop FF2. In addition, the other input is connected to the output of the logic circuit section 23.

That is, in the above specific example, the AND gate circuit is externally attached to the data input terminals of at least the flip-flops FF3 from the third stage to the final stage flip-flop FFn. 52 is provided so that when both the outputs of the first-stage and last-stage flip-flops are at “L” level, the “L” level signal is input to the input terminal of the AND gate circuit 52. Since they are input, the outputs of all the flip-flops are automatically initialized to "L" level.

That is, in the specific examples of FIGS. 5 and 6, the data input terminal of the flip-flop having the two data input terminals is externally connected to the data input terminal of the flip-flop having the one data input terminal. Done AND
It shows an example configured by either a gate circuit or an OR gate circuit. FIG. 7 is a block diagram showing an example of the configuration of the fourth specific example of the present invention, in which at least three flip-flops F are provided.
A Johnson counter circuit in which F1 to FFn are serially connected, and the output of the flip-flop FFn at the final stage is inverted and connected to the input terminal of the flip-flop FF1 at the first stage. The data selector means 60 is provided in a part of the flip-flops of the flip-flop group, and the flip-flops FF1 and FFn are located at both ends of the serially connected flip-flops. Of the flip-flop of the preceding stage in response to the logic of the output of the logic circuit section 2 while providing the logic circuit section 2 connected to the output of the logic circuit section 2 and connecting the output of the logic circuit section 2 to the data selector means 60. Either one of the output Q and a signal having a predetermined fixed level is selected to be an input terminal of a predetermined flip-flop. Counter circuit 1 configured as to force are shown.

The structure of the selector means 60 in this example is not particularly limited, but at least two different data input terminal portions D1 and D are inputted.
2 has a control signal input terminal,
According to the logic of the logic signal input to the input terminal of the control signal, if it has a function of selecting one of the two kinds of data and outputting it from the output terminal,
Anything can be used.

In this specific example, the data selector means 60 is provided between a predetermined flip-flop FFn and a flip-flop FFn-1 arranged in the preceding stage, and the first data is used. The input terminal D1 is connected to the output Q of the preceding flip-flop FFn-1, and a signal having a predetermined level, for example, an "H" level signal is constantly input to the second data input terminal D2. There is.

The output of the data selector means 60 is connected to the data input terminal D of the next-stage flip-flop FFn, and AN is an example of the logic circuit section 2.
The D gate circuit 21 is used. Then, when the output of the logic circuit section 21 is, for example, “H” level, the data selector means 60 is configured to select the data input to the second data input terminal. , When the outputs of the first-stage and final-stage flip-flops are both at "H" level, a "H" level signal is input to the data selector means 60.
The outputs of all flip-flops will be automatically initialized to "H" level.

In the above specific example, the flip-flop FFn- of the preceding stage, which is input to the first means input terminal D1 of the data selector means 60 during normal operation.
The output data of 1 passes through the data selector means 60 and the data input terminal D of the flip-flop FFn at the next stage.
And operates in shift register mode.

On the other hand, FIG. 8 shows a modification of the specific example shown in FIG. 7, in which the NOR gate circuit 24 is used as the logic circuit section 2 and the data selector means 60 is used.
In the second data input terminal D2, a signal having a predetermined level, for example, an "L" level signal is always input. Therefore, in this specific example, when the outputs of both the first and last flip-flops are at "L" level, the output of the NOR gate circuit 24 becomes "H" level,
Since the "H" level signal is input to the data selector means 60, the outputs of all the flip-flops are "L".
It will be automatically initialized to the level. .

In the above-mentioned specific example, the data selector means 60 is the first to receive the clock signal first among the Johnson counter circuits constituted by serially connecting the at least three flip-flops. It is desirable that the flip-flops are arranged in all the third and subsequent flip-flops counted from the flip-flops arranged in. or,
FIG. 9 is a block diagram for explaining the outline of the configuration of the fifth specific example according to the present invention, in which at least 3
Flip-flops FF1 to FFn are serially connected, and the flip-flops FFn at the final stage are connected.
In the Johnson counter circuit configured to invert the output of the flip-flop FF1 and to be connected to the input terminal of the flip-flop FF1 at the first stage, it is located at both ends of the plurality of serially connected flip-flops. A logic circuit section 2 connected to the outputs of the respective flip-flops FF1 and FFn is provided, and the outputs of the logic circuit section 2 are located at both ends of the Johnson counter circuit, and other than the respective flip-flop groups FF2 to FF2. FFn-
In the counter circuit configured to feed back to 1, the outputs of all the flip-flops FF1 to FFn forming the Johnson counter circuit are ORed with the clock signal CLK, and the logical result is the first signal. And a delay circuit 71 for delaying the clock signal by a time corresponding to the input / output delay time of the logic gate and outputting it as a second signal. It is shown.

That is, the above specific example is one of the application examples of the Johnson counter circuit according to the present invention, and the input of the logic gate circuit 70 to the first signal which is the output of the logic gate circuit 70 is input. Only the time corresponding to the output delay time,
The second signal generated by delaying the clock signal is generated so that the arithmetic circuit in the next stage can be synchronized.

FIG. 10 shows another application example of the counter circuit using the Johnson counter circuit according to the present invention, which has the configuration shown in each of the above specific examples. Is a unit counter circuit, a counter circuit having a structure in which a plurality of the unit counter circuits are combined and arranged in multiple stages and connected. That is, in FIG. 10, for example, a counter circuit including m-stage Johnson counters JC1 to JCm,
A plurality of flip-flops FF ₁₁ to ff _1N1 each Johnson counter to the clock input terminal C, respectively clock signal _{CLK, FF 21 ~FF 2N2 ··· FF} m1 ~
FF _mNm are connected in cascade, and the signal at each output terminal Q of the (k-1) th stage Johnson counter flip-flop is input via the OR gate to each clock of the k-th stage or more Johnson count flip-flop. A counter circuit configured to simultaneously input to the terminal C is shown, and Johnson counter circuit parts JC1 to JC of the counter circuit are shown.
In m, an automatic initializing circuit including the logic circuit section 2 of the present invention is incorporated.

Further, FIG. 11 shows still another application example of the counter circuit using the Johnson counter circuit according to the present invention, in which m-stage Johnson counter JC1 is used.
~ (C-1) logic gates LG1 connected between a counter circuit having JCm and each Johnson counter
A counter circuit having a LGM-1, a plurality of flip-flops FF ₁₁ Each Johnson counter circuit _{~FF 1N1, FF 21 ~FF 2N2 ···} FF m1 ~F
F _mNm are connected in cascade, and the clock signal CLK is simultaneously input to each clock input terminal C of the flip-flop of the first-stage Johnson counter, and the first logic gate LG
At 1, the logical sum of the clock signal and the signal at each output terminal Q of the flip-flop of the first-stage Johnson counter is generated, and the result is used as the first signal S1. The second logic gate LG2 is input to each clock input terminal C of the flip-flop of the Johnson counter at the same time.
Then, a logical sum of the first signal S1 and the signal at each output terminal Q of the flip-flop of the Johnson counter of the second stage is generated, and the result is used as the second signal S2. A counter circuit is shown in which the signal Sm-1 of 1) is simultaneously input to each clock input terminal C of the flip-flop of the Johnson counter of the mth stage, and the Johnson counter circuit sections JC1 to JCm of the counter circuit are shown.
In addition, the automatic initializing circuit including the logic circuit unit 2 according to the present invention is incorporated.

12 and 13 show a sixth concrete example of the counter circuit according to the present invention.
In this case, the parallel data is latched in response to the output of the serial / parallel data converting means 121 for taking in the serial data SL and converting it into a plurality of bits of parallel data, and the counter circuit 123 driven by the clock signal CLK. An example of using the above-described counter circuit 2 according to the present invention as the counter circuit 123 in the demultiplexer circuit composed of the output latch means 122 is shown, and in FIG. 13, a clock is shown. The counter circuit 132 is driven by the signal CLK, and the parallel / serial data conversion means 131 is responsive to the output of the counter circuit to take in a plurality of bits of parallel data, convert the parallel data into serial data, and output the serial data. Counter circuit in a multiplexer circuit As 32 illustrates an example of using the counter circuit 2 according to the present invention described above.

Further, FIG. 14 shows a seventh specific example as an application example of the counter circuit according to the present invention. In the figure, at least three flip-flops FF1 to FF are provided.
a first Johnson counter circuit JC1 in which n is serially connected and the output of the flip-flop FFn at the final stage is inverted and connected to the input terminal of the flip-flop FF1 at the first stage. A second Johnson counter circuit JC2, and the first Johnson counter circuit JC1 operates at the rising edge of the input clock signal, and the second Johnson counter circuit JC2 receives it. The first Johnson counter circuit JC1 is configured to operate at the falling edge of the clock signal, and the first Johnson counter circuit JC1 outputs the output of the final flip-flop FFn and the flip-flop FFn-1 immediately before the final flip-flop. The output of the first logic circuit unit 141 and the output of the final stage flip-flop FFn The second Johnson counter circuit JC2 has a second logic circuit section 142 that takes a logic with the output of the flip-flop FF1 of the first stage, and the second Johnson counter circuit JC2 has the output of the flip-flop FFn of the last stage and the flip-flop FF1 of the first stage. Third logic circuit unit 143 that takes a logic with the output of
And the output of the first logic circuit section 141 is used as a control signal of each flip-flop in the second Johnson counter circuit JC2, and further, the second and third The counter circuits are shown so that the outputs of the logic circuit sections 142 and 143 are respectively output as the first load pulse signal RP1 and the second load pulse signal RP2.

In this example, each of the flip-flops FF1 to FF1 constituting the second Johnson counter circuit JC2 is
When the output of the first logic circuit section 141 is input to the FFn, the flip-flop FFn at the final stage is input to the set terminal S, and the remaining flip-flops FF1 to FFn-1 are input. Is preferably input to the reset terminal R.

In the above embodiment of the present invention, the counter circuit automatically adjusts the timing for automatically adjusting the timings of the first Johnson counter circuit JC1 and the second Johnson counter circuit JC2. Is a circuit used in. Further, in this example, the first and second Johnson counter circuits JC1 and JC2 can be operated separately at the rising and falling edges of the clock signal, so that the frequency doubled apparently. Since it has been handled, it is possible to operate the circuit of the next stage at high speed.

Alternatively, the operating speed of a normal flip-flop can be reduced to half, so that the power of the flip-flop can be suppressed. Further, particularly in this example, the first load pulse signal RP1 and the second load pulse signal RP2 may be output with their phases being deviated by exactly a half cycle of the clock signal. Since it is possible, it is possible to accurately synchronize with the circuit in the next stage.

The operation of the counter circuit in this specific example is shown in the timing chart of FIG. The waveforms in FIG. 25 are the first and second Johnson counter circuits JC1 and J.
The case where C2 is composed of four flip-flops is shown as an example, and the output Q of each flip-flop is shown.
Is output with a constant delay time DT1 with the input clock signal.

In the figure, the load pulse signal is normally at "H" level, but the flip-flops FF of the first and fourth stages are used.
When both the outputs Q of 1 and FFn are at "L" level, a negative pulse is output.
Further, between the times t1 and t2, when the output Q of the third flip-flop FF3 is at "L" level and the output Q of the fourth flip-flop FF4 is at "H" level, The logic signal 1 is output from the logic circuit unit 141.

The logic signal 1 output from the first logic circuit section 141 is the delay time DT2 of the NOR gate circuit.
Only, the output Q of the third flip-flop FF3 is delayed from the time t0 when the output Q falls to "L" level. That is, the logic signal 1 output from the first logic circuit unit 141 is the third flip-flop FF.
It is output after a delay time obtained by adding the delay time DT1 of the flip-flop FF3 and the delay time DT2 of the NOR gate circuit in the first logic circuit section 141 has elapsed from the falling edge of 3.

On the other hand, the second Johnson counter circuit JC
2, the logic signal 1 output from the first logic circuit section 141 is input at the time t1, but the fourth
Since the flip-flop FF4 is input to the set terminal, the flip-flop FF4 at the “H” level is
Output does not change, and the flip-flops FF1 to FF3
, The logical signal 1 is input to the reset terminal, but this does not affect the output that has already become "L" level, and therefore at time t3 when the clock signal falls from time t1, the fourth signal is output. The output Q of the flip-flop FF4 is "L"
When the level becomes the level, the second load pulse signal RP2 outputs a negative pulse at the time t4 delayed by the delay time DT3 of the third logic circuit section 143, and the output point of the negative pulse is the The load pulse signal RP1 of 1 is output at a timing shifted by a half cycle of the clock signal cycle.

On the other hand, FIG. 15 shows a counter circuit having a modified form of another application example of the counter circuit according to the present invention shown in FIG. That is, in the mode of FIG. 15, the first logic circuit unit 1 shown in FIG.
Reference numeral 41 is configured to take the logic of the output of the final-stage flip-flop FFn, the output of the last-stage flip-flop FFn-1 and the clock signal.

Similar to FIG. 14, the operation of the counter circuit in this specific example is shown in the timing chart of FIG.
The waveform in FIG. 26 shows an example in which the first and second Johnson counter circuits JC1 and JC2 are composed of four flip-flops. Here, in the present specific example, since the first logic circuit section 141 is also configured to be controlled by the clock signal,
Compared with the specific example described above, the delay of the flip-flop itself becomes invisible, and the processing speed is improved accordingly.

Specifically, at time t5, after the output Q of the third-stage flip-flop FF3 falls, time t6.
Then, when the clock signal falls, from the time t6,
At time t7 when the delay time DT2 of the NOR gate circuit in the first logic circuit section 141 has elapsed, the output of the first logic circuit section 141 becomes "H" level. That is, in this specific example, the logic signal 1 output from the first logic circuit section 141 is the first logic signal from the fall time of the clock signal after the fall of the third flip-flop FF3. The output is delayed by the delay time DT2 of the NOR gate circuit in the logic circuit section 141.

FIG. 16 shows a counter circuit which is a modification of the seventh concrete example shown in FIG. 14, and more specifically, it is used in the counter circuit shown in FIG. Flip-flops FF1 and FF located at both ends of a plurality of serially connected flip-flops in the first Johnson counter circuit JC1.
A fourth logic circuit section 144 composed of an AND gate circuit connected to the output of n is provided, and the output of the fourth logic circuit section 144 is other than the flip-flops located at both ends of the Johnson counter circuit JC1. 14 shows a counter circuit configured to feed back to the flip-flop groups FF2 to FFn-1 of FIG.
It is possible to obtain a faster counter circuit with less malfunctions than the counter circuit of FIG.

On the other hand, FIG. 17 shows a counter circuit which is a modification of the concrete example shown in FIG. 15, and specifically, the first counter used in the counter circuit shown in FIG. Of the Johnson counter circuit JC1 of each of the flip-flops FF1 and FFn located at both ends of the plurality of serially connected flip-flops.
And a fourth logic circuit section 145 composed of an AND gate circuit connected to the output of the fourth logic circuit section 1
The counter circuit shown in FIG. 15 is configured to feed back the output of 45 to the flip-flop groups FF2 to FFn-1 other than the flip-flops located at both ends of the Johnson counter circuit JC1. In comparison with, it is possible to obtain a counter circuit which has less malfunction and has a higher speed.

The fourth logic circuit section used in the specific example shown in FIGS. 16 and 17 is an AND gate circuit, NA.
It is desirable to be composed of one selected from an ND gate circuit, an OR gate circuit and a NOR gate circuit.
Further, the flip-flops in the first Johnson counter circuit to which the outputs of the fourth logic circuit units 144 and 145 used in the specific examples in FIGS. 16 and 17 are input are two. It may be a flip-flop having a data input terminal, and the fourth logic circuit unit 14
The flip-flops in the first Johnson counter circuit, to which the outputs of Nos. 4, 145 are input, respond to the logic of the output of the logic circuit section to output the output of the preceding flip-flop and a predetermined fixed level. Data selector means configured to select any one of the signals it has and input it to the input terminal of a predetermined flip-flop may be provided.

FIG. 18 is a block diagram for explaining the configuration of the eighth concrete example of the counter circuit according to the present invention. In the figure, n flip-flops FF1 to FF1 which operate at the rising edge of the input clock signal are shown. FFn and n selector circuits 601 to 60n that select parallel data once every n cycles of the clock signal are configured as a pair, and n pairs of pairs are serially connected. The shift register STR1, n flip-flops FF1 to FFn that operate at the falling edge of the input clock signal, and n selector circuits 60 that select parallel data once every n cycles of the clock signal.
1 to 60n each include a second shift register STR2 in which n pairs, each of which is configured as a pair, are serially connected, and the counter circuit as shown in FIG. 14, for example. , The second of the counter circuit
The first load pulse signal RP1 output from the logic circuit unit 142 of FIG. 1 is input to each of the selector circuit groups 601 to 60n forming the first shift register STR1 and the third logic circuit of the counter circuit. The second load pulse signal RP2 output from the section 143 is the selector circuit groups 601 to 60 that constitute the second shift register.
A multiplexer circuit is shown configured to be input to each of the n.

Also in the multiplexer circuit in this specific example, it is possible to execute the multiplexer operation at half the operating frequency of the clock as compared with the conventional multiplexer circuit. FIG. 19 is a counter circuit showing another mode of the concrete example of FIG. 18, in which the output of the first shift register STR1 and the output of the second shift register STR2 in FIG. 18 are separately provided. The first data input terminal D1 and the second data input terminal D2 of the circuit 61
When the "H" level clock signal is input to the set input terminal of the selector circuit 61, the output of the first shift register STR1 is selected, and the selector circuit 61 is also input. The multiplexer circuit is configured so that the output of the second shift register STR2 is selected when the "L" level clock signal is input to the set input terminal of.

Further, FIG. 20 is a block diagram showing the structure of the ninth embodiment of the present invention. That is,
In the figure, n toggle flip-flops FF1 to FFn
Are serially connected to each toggle flip-flop F
A counter circuit configured to output predetermined data in parallel from the outputs of F1 to FFn, wherein a clock signal input to the toggle flip-flop FFm in a predetermined stage is input to the corresponding stage. The toggle flip-flop FFm is configured to be controlled in response to the output of each toggle flip-flop FFm-1 up to the preceding stage. For that purpose, the control means 721 to 72n are provided for the toggle flip-flop FFm. It is arranged corresponding to each of the groups.

In this specific example as well, the output timings of the toggle flip-flops FF1 to FFn may vary, so that the output timings of the toggle flip-flops FF1 to FFn are set to be uniform. It is a thing. FIG. 21 is a block diagram for explaining a more specific configuration example of the above specific example, which is n toggle flip-flops FF1 to FFn.
Are serially connected to each toggle flip-flop F
A counter circuit configured to output predetermined data in parallel from the outputs of F1 to FFn, wherein the toggle flip-flop FFn at the nth stage to the toggle flip-flop FFn at the (n-1) th stage. The input of the clock signal in each toggle flip-flop up to -1 is m
In the toggle flip-flop in the stage, (m
-3) The output of the toggle flip-flop of the third stage and (m-
2) It is configured to be controlled by a second logical sum obtained from the output of the toggle flip-flop of the second stage and the output of the toggle flip-flop of the (m-1) th stage. There is something.

That is, in this example, as the control means 72, the selector circuit 62 similar to that described above is used.
1 to 62n for each toggle flip-flop FF1 to FF
It is arranged so as to correspond to each n, and whether or not a predetermined toggle flip-flop FFm may be hit with a clock signal is determined based on the output of the toggle flip-flop FFm-1 in the previous stage. The output of the toggle flip-flop FFm-1 is input to the set input terminal S of the selector circuit 62m provided corresponding to the toggle flip-flop FFm. If it is H "level, the predetermined" H "level signal input to the second data input terminal D2 is input to the clock input signal terminal C of the toggle flip-flop FFm, and the toggle signal of the previous stage is changed. If the output of the flip-flop FFm-1 is at the "L" level, the clock input to the first data input terminal D1 is output. Click signal is selected, in which it is supplied to the clock input signal terminal C of the toggle flip-flop FFm slewing.

That is, in this example, for example, the second
The input of the clock signal of the toggle flip-flop FF2 in the first stage is restricted by the toggle flip-flop FF1 in the first stage.
Of the first stage and second stage toggle flip-flops FF1 and FF2 are input to the OR circuit LC10. , The OR circuit LC1
0 is used to limit the input of the clock signal of the toggle flip-flop FF4 at the fourth stage to the logical sum and the toggle flip-flop F at the third stage.
The output of F3 is input to the logical sum circuit LC11, and the logical sum output from the logical sum circuit LC11 is performed.

The operation timing in this specific example is shown in FIG.
7 is shown. That is, the timing chart of FIG. 27 shows an example of a counter circuit in which four toggle flip-flops are serially connected. Now, at time t0, when the first clock rises, a predetermined delay time elapses. At time t1, first the first-stage toggle flip-flop FF1 rises, then at time t2, when the clock signal rises, the first-stage toggle flip-flop FF1 falls at time t3, and the clock signal rises at time t4. The falling edge and the selector circuit simultaneously fall through the clock signal passing through.

Next, when the clock signal rises at time t5, the selector circuit also rises at the same time, and the first-stage toggle flip-flop FF1 rises at the same time as the second flip-flop FF1 rises at time t6 after the elapse of a predetermined delay time. The toggle flip-flop FF2 at the second stage also rises, and synchronization is achieved. In this specific example, the operation is repeated until the time t7, and the toggle flip-flop FF1 of the first stage to the toggle flip-flop FF4 of the fourth stage are reached.
It is possible to realize a synchronized state in which all the output timings are aligned.

[0072]

According to the present invention, in various counter circuits composed of a plurality of flip-flops including a Johnson counter circuit, all flip-flops have the same output when the power is turned on. ,Thereby,
It is intended to provide a counter circuit which does not malfunction and can be operated at high speed and which avoids complexity of the circuit structure.

Furthermore, by using the counter circuit according to the present invention, it is possible to easily manufacture a control signal generating circuit for synchronizing various control circuits accurately and at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of a counter circuit according to the present invention.

FIG. 2 is a block diagram showing an example of a configuration of a first concrete example of the counter circuit according to the present invention.

FIG. 3 is a block diagram showing an example of a configuration of a second specific example of the counter circuit according to the present invention.

FIG. 4 is a block diagram showing an example of a configuration of a third concrete example of the counter circuit according to the present invention.

FIG. 5 is a block diagram showing a configuration example of another aspect of the third specific example shown in FIG.

6 is a block diagram showing a configuration example of another aspect of the third concrete example shown in FIG. 4;

FIG. 7 is a block diagram showing an example of a configuration of a fourth concrete example of the counter circuit according to the present invention.

FIG. 8 is a block diagram showing a configuration example of another aspect of the fourth specific example shown in FIG. 7.

FIG. 9 is a block diagram showing an example of a configuration of a fifth specific example of the counter circuit according to the present invention.

FIG. 10 is a block diagram showing an example of a counter circuit configured by using the counter circuit according to the present invention.

FIG. 11 is a block diagram showing another example of a counter circuit configured by using the counter circuit according to the present invention.

FIG. 12 is a sixth diagram of a counter circuit according to the present invention.
3 is a block diagram showing an example of a configuration of a specific example of FIG.

FIG. 13 is a block diagram showing a configuration example of another aspect of the sixth specific example shown in FIG. FIG.
9 is a block diagram showing a configuration example of another aspect of the third specific example shown in FIG.

FIG. 14 is a seventh circuit of the counter circuit according to the present invention.
3 is a block diagram showing an example of a configuration of a specific example of FIG.

FIG. 15 is a block diagram showing a configuration example of another aspect of the seventh specific example shown in FIG.

16 is a block diagram showing a configuration example of another aspect of the seventh specific example shown in FIG.

FIG. 17 is a block diagram showing a configuration example of still another aspect of the seventh specific example shown in FIG.

FIG. 18 is an eighth counter circuit according to the present invention.
3 is a block diagram showing an example of a configuration of a specific example of FIG.

FIG. 19 is a block diagram showing a configuration example of another aspect of the eighth specific example shown in FIG. 18.

FIG. 20 is a ninth circuit of a counter circuit according to the present invention.
3 is a block diagram showing an example of a configuration of a specific example of FIG.

FIG. 21 is a block diagram showing a configuration example of another aspect of the ninth specific example shown in FIG. 20.

FIG. 22 is a block diagram showing a configuration example of a counter circuit using a conventional flip-flop.

FIG. 23 is a block diagram showing another configuration example of a counter circuit using a conventional flip-flop.

FIG. 24 is a block diagram showing another configuration example of a counter circuit using a conventional flip-flop.

FIG. 25 is a timing chart in the counter circuit shown in FIG.

FIG. 26 is a timing chart in the counter circuit shown in FIG.

FIG. 27 is a timing chart in the counter circuit shown in FIG. 21.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Counter circuit 2 ... Logic circuit part 21 ... AND gate circuit 22 ... NAND gate circuit 23 ... OR gate circuit 24 ... NOR gate circuit 52 ... AND gate circuit 60, 61, 62 ... Selector circuit 70 ... Logic gate circuit 71 ... Delay Means 72 ... Control means 121, 131 ... Conversion means 122 ... Latch means 123, 132 ... Counter circuit 141 ... First logic circuit section 142 ... Second logic circuit section 143 ... Third logic circuit section 144, 145 ... Fourth Logic circuit part

Claims (27)

[Claims] 1. At least three flip-flops are serially connected, and the output of the final flip-flop is inverted and connected to the input terminal of the first flip-flop. In the Johnson counter circuit, a logic circuit section connected to the outputs of the respective flip-flops located at both ends of the serially connected flip-flop row is provided, and the output of the logic circuit section is A counter circuit characterized by being configured to feed back to a flip-flop group other than the flip-flops located at both ends of the Johnson counter circuit. 2. The counter circuit according to claim 1, wherein the logic output output from the logic circuit section is configured to be input to a set terminal or a reset terminal in the flip-flop. . 3. The counter circuit according to claim 1, wherein the logic circuit section is composed of either an AND gate circuit or a NAND gate circuit. 4. At least three flip-flops are serially connected, and the output of the last flip-flop is inverted and connected to the input terminal of the first flip-flop. In the Johnson counter circuit, a part of the flip-flop group is composed of flip-flops having two data input terminals and is located at both ends of a plurality of serially connected flip-flops. A logic circuit section connected to the output of each flip-flop is provided, and the output of the logic circuit section is fed back to one data input terminal of the flip-flop group having the two data input terminals of the Johnson counter circuit. A counter circuit characterized by being configured as described above. 5. A data input terminal of a flip-flop having the two data input terminals is configured by either an AND gate circuit or an OR gate circuit connected to the outside of the flip-flop. The counter circuit according to claim 4. 6. A flip-flop having the two data input terminals is a Johnson counter circuit configured by serially connecting the at least three flip-flops.
5. The counter circuit according to claim 4, wherein the counter circuit is applied to all flip-flops after the th. 7. The counter circuit according to claim 4, wherein the logic circuit section is composed of either an AND gate circuit or an OR gate circuit. 8. At least three flip-flops are serially connected, and the output of the last flip-flop is inverted and connected to the input terminal of the first flip-flop. In the Johnson counter circuit, data selector means is provided in a part of the flip-flops of the flip-flop group, and each of the flip-flops is located at both ends of the plurality of serially connected flip-flops. A logic circuit section connected to the output of the flip-flop is provided, and the output of the logic circuit section is connected to the data selector means. In response to the logic of the output of the logic circuit section, Select one of the signals with a predetermined fixed level and input it to the input terminal of a predetermined flip-flop. A counter circuit characterized by being configured. 9. The data selector means is provided in all the third and subsequent flip-flops counted from the first-stage flip-flop in the Johnson counter circuit configured by serially connecting the at least three flip-flops. 9. The counter circuit according to claim 8, wherein the counter circuit is provided. 10. The counter circuit according to claim 9, wherein the data selector means is inserted between a predetermined flip-flop and a preceding flip-flop. 11. The data selector means has a first input terminal for inputting a data output of a preceding flip-flop of a predetermined flip-flop and a second input for receiving a signal having a predetermined fixed voltage level. A first input terminal or a second input terminal in response to a logic signal input from the logic circuit section, the output terminal being connected to a data input terminal of the predetermined flip-flop.
10. The counter circuit according to claim 9, wherein the counter circuit is configured to select a data signal input to any one of the input terminals and to supply the selected data signal to the data input terminal of the flip-flop. 12. The counter circuit according to claim 8, wherein the logic circuit section is composed of either an AND gate circuit or a NOR gate circuit. 13. At least three flip-flops are serially connected, and the output of the final flip-flop is inverted and connected to the input terminal of the first flip-flop. In the Johnson counter circuit, a logic circuit section connected to the outputs of the respective flip-flops located at both ends of the serially connected flip-flop row is provided, and the output of the logic circuit section is In a counter circuit configured to feed back to a flip-flop group other than the flip-flops located at both ends of the Johnson counter circuit, the outputs of all the flip-flops configuring the Johnson counter circuit and the clock signal A logic gate circuit that takes the logical sum and outputs the logical result as the first signal A counter circuit for delaying the clock signal by a time corresponding to the input / output delay time of the logic gate and outputting it as a second signal. 14. A counter circuit, wherein the counter circuit specified in each of the above-mentioned claims is used as a unit counter circuit, and a plurality of the unit counter circuits are combined and arranged in multiple stages and connected. 15. The counter circuit specified in each of the above claims, serial data is fetched,
A demultiplexer circuit comprising serial / parallel data conversion means for converting into parallel data of a plurality of bits, and latch means for latching and outputting the parallel data in response to an output of the counter circuit. 16. A counter circuit specified in each of the above claims, and in response to an output of the counter circuit, fetches a plurality of bits of parallel data, converts the parallel data into serial data, and outputs the serial data. A multiplexer circuit comprising parallel / serial data conversion means. 17. At least three flip-flops are serially connected, and the output of the final flip-flop is inverted and connected to the input terminal of the first flip-flop. The first Johnson counter circuit is composed of a first Johnson counter circuit and a second Johnson counter circuit, and the first Johnson counter circuit operates at the rising edge of the input clock signal, and the second Johnson counter circuit , The first Johnson counter circuit is configured to operate at the falling edge of the input clock signal, and the first Johnson counter circuit outputs the output of the final stage flip-flop and the flip-flop of the stage immediately before the final stage. The output of the first logic circuit section that takes the logic of the output, the output of the last-stage flip-flop, and the output of the first-stage flip-flop A second logic circuit section that takes the logic of the force and the second Johnson counter circuit takes the logic of the output of the last-stage flip-flop and the output of the first-stage flip-flop. A logic circuit section, and the output of the first logic circuit section is used as a control signal for each flip-flop in the second Johnson counter circuit, and further, the second and third circuits are provided. The counter circuit is characterized in that the outputs of the logic circuit section are output as a first load pulse signal and a second load pulse signal, respectively. 18. A first logic circuit section in the first Johnson counter circuit comprises a logic of an output of a flip-flop of the last stage, an output of a flip-flop of a stage immediately before the last stage, and a clock signal. 18. The counter circuit according to claim 17, wherein the counter circuit is configured to take 19. The first logic circuit section in the first Johnson counter circuit further comprises outputs of respective flip-flops located at both ends of a plurality of serially connected flip-flop arrays. And a fourth logic circuit portion connected to the flip-flop group other than the flip-flop groups located at both ends of the Johnson counter circuit. The counter circuit according to any one of claims 17 to 18, wherein: 20. The fourth logic circuit unit comprises an AND gate circuit, a NAND gate circuit, an OR gate circuit and a NO.
20. The counter circuit according to claim 19, comprising one selected from the R gate circuits. 21. The flip-flop in the first Johnson counter circuit to which the output of the fourth logic circuit section is input is a flip-flop having two data input terminals. Item 19. The counter circuit according to Item 19. 22. The flip-flop in the first Johnson counter circuit, to which the output of the fourth logic circuit unit is input, responds to the logic of the output of the logic circuit unit, 20. A data selector means is provided which is configured to select either one of the output and the signal having a predetermined fixed level and input the selected one to the input terminal of a predetermined flip-flop.
The described counter circuit. 23. A pair of n flip-flops that operate at the rising edge of an input clock signal and n selector circuits that select parallel data once every n times of the clock signal are formed as a pair. A first shift register having n pairs of serially connected pairs and n operating on the falling edge of the input clock signal.
N flip-flops and n selector circuits that select parallel data once every n cycles of the clock signal are formed as a pair, and n pairs of pairs are serially connected. A shift register and a counter circuit according to any one of claims 17 to 22, wherein the first load pulse signal output from a second logic circuit section of the counter circuit is the first load pulse signal. The second load pulse signal that is input to each of the selector circuit groups that configure the first shift register and that is output from the third logic circuit unit of the counter circuit is the selector that configures the second shift register. A multiplexer circuit characterized in that it is configured to be input to each of the circuit groups. 24. Outputs of the first and second shift registers are connected to an output signal switching circuit, and in response to a voltage level of a clock signal input to the shift register, the first shift register and the first shift register are connected. 24. The multiplexer circuit according to claim 23, wherein one of the outputs of the second shift register is selected and output. . 25. A counter circuit in which n toggle flip-flops are serially connected and predetermined data is output in parallel from the output of each toggle flip-flop, and the counter circuit is provided in predetermined stages. It is characterized in that the input of the clock signal in the toggle flip-flop in the stage is controlled in response to the output of each toggle flip-flop in the stage up to the stage before the toggle flip-flop. Counter circuit to do. 26. A counter circuit, in which n toggle flip-flops are serially connected, and predetermined data is output in parallel from the output of each toggle flip-flop, which is the n-th stage The input of the clock signal in each toggle flip-flop from the toggle flip-flop to the (n-1) th toggle flip-flop is (m- 3) It is obtained from the first logical sum of the output of the toggle flip-flop of the (m−2) th stage and the output of the toggle flip-flop of the (m−2) th stage, and the output of the toggle flip-flop of the (m−1) th stage. A counter circuit which is configured to be controlled by a second logical sum. 27. The toggle flip-flop has at least two types of input data terminals, and selects one input data from the two types of input data in response to the second logical sum output. 27. The counter circuit according to claim 26, further comprising selector means configured so as to be capable of controlling.