CN217643311U - Clock generation circuit, data operation circuit and chip - Google Patents

Abstract

The embodiment of the utility model provides a clock generation circuit, data operation circuit and chip, its characterized in that, clock generation circuit includes: the feedback circuit comprises a functional circuit, a first output circuit, a second output circuit and a feedback loop; the feedback loop is used for generating a feedback signal according to the output signal of the functional circuit; the functional circuit is used for generating a pulse clock signal according to the clock source signal, generating a delay feedback signal according to the pulse clock signal based on the feedback signal, and generating an output signal according to the delay feedback signal and the clock source signal; a first output circuit for generating a first pulse trigger signal according to the output signal; and the second output circuit is used for generating a second pulse trigger signal according to the output signal, and the time difference between the first pulse trigger signal and the second pulse trigger signal is a specified time length.

Description

Clock generation circuit, data operation circuit and chip

Technical Field

The embodiment of the utility model provides a relate to semiconductor device technical field, especially relate to a clock generation circuit, data operation circuit and chip.

Background

Clock generation circuits are widely used, such as clock generation circuits of computers, clock generation circuits of electronic watches, and the like, and the clock generation circuits for generating clocks may also be generally referred to as clock generators. In the prior art, the clock width (duty ratio) of a clock generator is specified by a clock source, in other words, limited by the pulse width of a clock source signal, after a fixed pulse width of the clock source is processed by several stages of the clock generator, the pulse width may change, which results in that the requirements under certain specific scenes cannot be met.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a clock generation circuit, data operation circuit and chip to at least part solves above-mentioned problem.

The utility model discloses a first aspect of the embodiment provides a clock generation circuit, and clock generation circuit includes: the feedback circuit comprises a functional circuit, a first output circuit, a second output circuit and a feedback loop;

the feedback loop is used for generating a feedback signal according to the output signal of the functional circuit;

the functional circuit is used for generating a pulse clock signal according to a clock source signal, generating a delay feedback signal according to the pulse clock signal based on the feedback signal, and generating the output signal according to the delay feedback signal and the clock source signal;

the first output circuit is used for generating a first pulse trigger signal according to the output signal;

the second output circuit is used for generating a second pulse trigger signal according to the output signal, and the time difference between the first pulse trigger signal and the second pulse trigger signal is a specified time length.

Optionally, the clock generation circuit is applied to a two-stage shift register, the specified duration is greater than or equal to a duration of a retention time of a next shift register in the two-stage shift register, the first pulse trigger signal is used to control a previous shift register in the two-stage shift register, and the second pulse trigger signal is used to control a next shift register in the two-stage shift register.

Optionally, the functional circuit comprises: the logic turning module comprises a plurality of stages of phase inverters which are connected in series, wherein the input end of the most front stage of phase inverter is used as the first input end of the functional circuit, and the plurality of stages of phase inverters are used for sequentially turning the clock source signal to generate a pulse clock signal.

Optionally, the functional circuit further comprises: the delay module is connected with the logic overturning module; the delay module comprises a selector and a plurality of delay sub-circuits;

each delay sub-circuit corresponds to different delay time and is used for delaying the received pulse clock signal for a corresponding preset time length based on the feedback signal;

the selector is used for selecting the delay sub-circuit, so that the delay sub-circuit delays the pulse clock signal for preset duration based on the feedback signal to generate a delay feedback signal.

Optionally, the functional circuit further comprises: and the NAND gate module is connected with the delay module, and respectively receives the clock source signal and the delay feedback signal and is used for performing NAND logic processing on the clock source signal and the delay feedback signal to obtain the output signal.

Optionally, the logic flip module includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor;

the grid electrodes of the first PMOS transistor and the first NMOS transistor are connected and are a first input end of the functional circuit; the gate of the second NMOS transistor is a second input terminal of the functional circuit.

Optionally, the nand gate module includes a sixth PMOS transistor, a seventh PMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor, gates of the sixth PMOS transistor and the sixth NMOS transistor are both connected to the clock source signal, gates of the seventh NMOS transistor and the seventh PMOS transistor are both connected to the delay feedback signal, a drain of the sixth PMOS transistor is connected to a source of the sixth NMOS transistor and connected to the output end, a drain of the seventh NMOS transistor is grounded, and a drain of the seventh NMOS transistor is connected to the output end.

Optionally, the first output circuit includes cascaded M-stage inverters, configured to flip the output signal an odd number of times and invert the output signal an even number of times to generate the first pulse trigger signal, where M is an integer greater than or equal to.

Optionally, the second output circuit includes cascaded N-stage inverters, configured to flip the output signal an odd number of times and invert the output signal an even number of times, so as to generate the second pulse trigger signal, where N is an integer greater than or equal to N, and N is greater than M.

In a second aspect, a data operation circuit is provided, which includes a control circuit, an operation circuit, and a clock generation circuit, which are interconnected, where the clock generation circuit is the clock generation circuit described in any embodiment.

In a third aspect, a chip is provided, which includes at least one of the data operation circuits.

According to the utility model provides a clock generation circuit, include: the feedback circuit comprises a functional circuit, a first output circuit, a second output circuit and a feedback loop; the feedback loop is used for generating a feedback signal according to the output signal of the functional circuit; the functional circuit is used for generating a pulse clock signal according to the clock source signal, generating a delay feedback signal according to the pulse clock signal based on the feedback signal, and generating the output signal according to the delay feedback signal and the clock source signal; the first output circuit is used for generating a first pulse trigger signal according to the output signal; the second output circuit is used for generating a second pulse trigger signal according to the output signal, and the time difference between the first pulse trigger signal and the second pulse trigger signal is a specified time length, so that the pulse trigger signal with the pulse width meeting the requirement of a specific scene can be generated.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments made with reference to the following drawings:

fig. 1 is a schematic circuit diagram of a clock generation circuit according to an embodiment of the present invention.

Fig. 2 is a schematic circuit structure diagram of a clock generating circuit according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of an embodiment of the present application applied to a two-stage shift register.

Fig. 4 is a schematic circuit structure diagram of a clock generation circuit according to a fourth embodiment of the present invention.

FIG. 5A is a schematic structural diagram of a delay module according to an embodiment of the present disclosure;

fig. 5B is a schematic structural diagram of a U-shaped delay chain according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of a data operation unit according to an embodiment of the present invention.

Fig. 7 is a schematic structural diagram of a chip according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely configured to illustrate the relevant utility model and are not limitations of the utility model. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present invention will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Example one

Referring to fig. 1, fig. 1 is a schematic circuit structure diagram of a clock generation circuit according to an embodiment of the present invention. The clock generation circuit includes: a functional circuit 1, a first output circuit 2, a second output circuit 3 and a feedback loop 4.

The feedback loop is used to generate a feedback signal from the output signal of the functional circuit 1. For example, a first input terminal of the functional circuit 1 receives a clock source signal, an output terminal of the functional circuit is connected to the first output circuit 2 and the second output circuit 3, and the output terminal of the functional circuit 1 is connected to a second input terminal of the functional circuit to form the feedback loop.

The functional circuit 1 is configured to generate a pulse clock signal according to the clock source signal, and generate a delay feedback signal (such as X described below) according to the pulse clock signal based on the feedback signal, so as to generate the output signal according to the delay feedback signal and the clock source signal.

The first output circuit 2 is configured to generate a first pulse trigger signal according to the output signal.

And the second output circuit 3 is configured to generate a second pulse trigger signal according to the output signal, where a time difference between the first pulse trigger signal and the second pulse trigger signal is a specified time duration.

In this embodiment, the time difference between the first pulse trigger signal and the second pulse trigger signal may be a time length specified in advance according to actual requirements, for example, when the clock generation circuit is applied to a two-stage shift register, the first pulse trigger signal is used to control a previous-stage shift register in the two-stage shift register, the second pulse trigger signal is used to control a next-stage shift register in the two-stage shift register, and the specified time length is greater than or equal to the time length of the holding time of the next-stage shift register in the two-stage shift register.

Example two

Fig. 2 is a schematic circuit structure diagram of a clock generating circuit according to an embodiment of the present invention. As shown in fig. 2, the functional circuit 1 includes: a logic flip module 10, a delay module 11 and a nand gate module 12. The logic flip module 10 includes a plurality of serially connected inverters, wherein an input end of a first-stage inverter is used as a first input end of the functional circuit, and an output end of a last-stage inverter is used as an output end of the functional circuit; the several stages of inverters are configured to sequentially invert the clock source signal to generate a pulse clock signal (as in S3 below).

The delay module 11 is connected to the logic flip module 10, and the delay module 11 includes a selector and a plurality of delay sub-circuits; each delay sub-circuit corresponds to different delay time and is used for delaying the received pulse clock signal for a corresponding preset time length based on the feedback signal to generate a delay feedback signal (as X below); the selector is configured to enable the delay sub-circuit to delay the pulse clock signal for a preset duration based on the feedback signal according to the selected delay sub-circuit to generate a delayed feedback signal (such as FB).

The nand gate module 12 is connected to the delay module 11, and the nand gate module 12 receives the clock source signal and the delayed feedback signal, respectively, and is configured to perform a nand logic process on the clock source signal and the delayed feedback signal to obtain the output signal (such as OUT described below).

EXAMPLE III

Fig. 3 is a schematic diagram of an embodiment of the present application applied to a two-stage shift register. In fig. 3, the first pulse trigger signal is denoted as (CKN 2, CKP 2), and the second pulse trigger signal is denoted as (CKN 1, CKP 1).

As shown in fig. 3, the operation principle is briefly described as follows: illustratively, after the data Dn is transmitted into the shift register of the previous stage, when the clock rising edge of the CLKP1 comes, the shift register of the previous stage outputs the data Dn; when the rising edge of the clock CLKP2 comes, the next stage shift register starts to latch the data Dn output by the previous stage shift register, and the next stage shift register starts to latch the data to the time period when the data latch is completed.

Therefore, the embodiment of the utility model provides a clock generation circuit, based on time delay feedback signal, can produce first pulse trigger signal and second pulse trigger signal, first pulse trigger signal with second pulse trigger signal's time difference is for the specified duration, should be specified duration more than or equal to the length of time of back one-level shift register's holding time in the two-stage shift register to can guarantee that preceding one-level shift register can satisfy the holding time of shift register with another data transmission to back one-level shift register after this holding time, and then realize the accurate storage of data.

Example four

Fig. 4 is a schematic circuit diagram of a clock generating circuit according to a fourth embodiment of the present invention. For example, the clock generation circuit may be applied to a two-stage shift register, and the specified time period is equal to or longer than a holding time of a shift register of a subsequent stage in the two-stage shift register.

As shown in fig. 4, the logic flipping module 10 includes: the first PMOS transistor P1, the third PMOS transistor P3, and the fourth PMOS transistor P4, and the first NMOS transistor N1, the third NMOS transistor N3, and the fourth NMOS transistor N4 may be used to logically flip the clock source signal. The first PMOS transistor P1 and the first NMOS transistor N1 form a first-stage inverter, the third PMOS transistor P3 and the third NMOS transistor N3 form a second-stage inverter, and the fourth PMOS transistor P4 and the fourth NMOS transistor N4 form a second-stage inverter, that is, the logic flip module 10 includes a three-stage inverter, an output signal of the first-stage inverter is denoted as S1, an output signal of the second-stage inverter is denoted as S2, an output signal of the third-stage inverter is denoted as S3, and the S3 serves as a pulse clock signal output by the logic flip module.

The gates of the first PMOS transistor P1 and the first NMOS transistor N1 are both connected to the clock source signal CLK, the source of the first PMOS transistor P1 is connected to the power supply, and the drain of the first PMOS transistor P1 is connected to the drain of the first NMOS transistor N1. The gates of the third PMOS transistor P3 and the third NMOS transistor N3 are connected to S1, the drains of the third PMOS transistor P3 and the third NMOS transistor N3 are connected to each other, and the source of the third NMOS transistor N3 is grounded. The gates of the fourth PMOS transistor P4 and the fourth NMOS transistor N4 are connected to S2, the drains of the fourth PMOS transistor P4 and the fourth NMOS transistor N4 are connected to each other and to S3, the source of the fourth PMOS transistor P4 is connected to the power supply, and the source of the fourth NMOS transistor N4 is grounded.

And S3, recording a signal obtained by processing through the delay module 11 as X, wherein X represents a delay feedback signal.

It should be noted that, in other embodiments, the number of stages of the inverter included in the logic flipping module 10 is determined according to an application scenario, and is not limited to three stages.

As shown in fig. 4, the delay module 11 includes a selector and a plurality of delay sub-circuits; a selector and a plurality of delay sub-circuits; each delay sub-circuit corresponds to different delay time and is used for delaying the received pulse clock signal for a corresponding preset time length based on the feedback signal so as to generate a delay feedback signal; the selector is used for selecting the delay sub-circuit, so that the delay sub-circuit delays the pulse clock signal for a preset time length based on the feedback signal to generate a delay feedback signal.

In fig. 4, 4 delay sub-circuits (sequentially denoted as delay 1, delay 2, delay 3, and delay 4) are taken as an example, and it can be understood that in practical applications, a person skilled in the art can set any appropriate number of delay sub-circuits according to requirements.

The nand gate module comprises a sixth PMOS transistor P6, a seventh PMOS transistor P7, a sixth NMOS transistor N6, and a seventh NMOS transistor N7, gates of the sixth PMOS transistor and the sixth NMOS transistor are both connected with the clock source signal, gates of the seventh NMOS transistor and the seventh PMOS transistor are both connected with the delay feedback signal, a drain of the sixth PMOS transistor is connected with a source of the sixth NMOS transistor and connected with the output end of the functional circuit, a source of the seventh NMOS transistor is grounded, and a drain of the seventh PMOS transistor is connected with the output end. The sources of the sixth PMOS transistor P6 and the seventh PMOS transistor P7 are connected to the power supply. The source of the seventh NMOS transistor is grounded. The drain of the seventh PMOS transistor N7 is connected to the output of the functional circuit 1.

Further, after the gates of the sixth PMOS transistor P6 and the sixth NMOS transistor N6 are connected, the gates of the first PMOS transistor P1 and the first NMOS transistor N1 are connected, and the connected gates are used as a first input end of the functional circuit 1.

Referring to fig. 4, the feedback loop 4 includes a phase inverter, a pull-down module, and a pull-up module, an input end of the phase inverter is connected to an output end of the functional circuit, an input end of the pull-down module is connected to an output end of the phase inverter, an output end of the pull-down module is connected to an input end of the pull-up module, and an output end of the pull-up module is connected to the second-stage phase inverter in the logic flipping module 10, specifically, to a source of the third PMOS transistor P3.

Specifically, the inverter included in the feedback loop 4 includes an eighth PMOS transistor P8 and an eighth NMOS transistor N8, gates of the eighth PMOS transistor P8 and the eighth NMOS transistor N8 are both connected to the output terminal of the functional circuit 1, a source of the eighth PMOS transistor P8 is connected to the power supply, a drain of the eighth PMOS transistor P8 is connected to a drain of the eighth NMOS transistor N8, a source of the eighth NMOS transistor N8 is grounded, and an output signal of the inverter is denoted as FB, which is a delay feedback signal.

Specifically, the pull-down module includes a second PMOS transistor N2 having a drain connected to the drain of the first NMOS transistor N1, a source grounded, and a gate connected to the output terminal of the inverter (formed by P8 and N8) to receive the feedback signal FB.

Specifically, the drawing-up module includes: the gates of the second PMOS transistor P2, the fifth PMOS transistor P5 and the fifth NMOS transistor N5 are connected to the output terminal of the inverter (formed by P8 and N8) to receive the feedback signal FB. The source electrode of the fifth PMOS transistor P5 is connected with the power supply, the source electrode of the fifth NMOS transistor N5 is grounded, the drain electrode of the fifth PMOS transistor P5 is connected with the drain electrode of the fifth NMOS transistor N5 and is connected with the grid electrode of the second PMOS transistor P2, the source electrode of the second PMOS transistor P2 is connected with the power supply, and the drain electrode of the second PMOS transistor P2 is connected with the source electrode of the third PMOS transistor P3.

Here, it should be noted that the specific circuit structure of the inverter, the pull-down module and the pull-up module included in the feedback loop 4 is only an example and is not limited thereto.

For ease of understanding, the clock pulse signal generation process of the clock generation circuit shown in fig. 4 is explained below by way of a more detailed embodiment: the clock source signal CLK =0, the clock source signal CLK being a rising edge signal (0 ≠ 1), and CLK =1 are explained:

(1) When the clock source signal CLK =0, the circuit is in a stable state, and at this time, the delay time has reached, and the delay module does not perform the delay processing on S3:

when the clock source signal CLK =0, the first PMOS transistor P1 is turned on, and N1 is turned off, where S1 is 1, the third NMOS transistor N3 is turned on, P3 is turned off, S2 is 0, the fourth PMOS transistor P4 is turned on, N4 is turned off, and S3 is 1, where S3 is not delayed because the delay time of the delay module 11 has reached, so that the signal at S3 is directed to X, and thus X =1.

When the clock source signal CLK =0, the sixth PMOS transistor P6 is turned on, the sixth NMOS transistor N6 is turned off, and X =1 turns off the seventh PMOS transistor P7, turns on the seventh NMOS transistor N7, turns OUT =1, and turns on the eighth NMOS transistor N8, so that FB =0, where the sixth PMOS transistor P6, the sixth NMOS transistor N6, the seventh PMOS transistor P7, and the seventh NMOS transistor N7 are equivalent to forming a nand gate.

In addition, since FB =0, it is ensured that the second NMOS transistor N2 is turned off (equivalent to the pull-down block being turned off, without pull-down effect), the fifth NMOS transistor N5 is turned off and the second PMOS transistor P2 is turned off (equivalent to the pull-up block being turned off, without pull-up effect), so that CLK is equivalent to being directly subjected to the three-stage inversion process (P1 and N1 constitute the first-stage inversion to generate the signal at S1, at this time 1, P3 and N3 constitute the second-stage inversion to generate the signal at S2, at this time 0, P4 and N4 constitute the third-season inversion to generate the signal at S3, at this time 1), so as to generate OUT, at this time 1.

Since OUT =1, at this time, after being processed by the first output circuit 2, CKN2=1, ckp2=0; after being processed by the second output circuit 3, CKN1=1 and ckp1=0.

(2) When the clock source signal CLK is a rising edge signal (0 ≠ 1), the delay module performs delay processing on S3, so that X remains at 1 during the non-arrival delay time, and OUT generates a falling edge:

when the clock source signal CLK is a rising edge signal (0 ≠ 1), the sixth PMOS transistor P6 is turned off, and the sixth NMOS transistor N6 is turned on, but since OUT remains 1 and N8 is turned on, FB remains 0, and N2, N5, and P2 remain off, S1 remains 1, S2 remains 0, and S3 remains 1, which is equivalent to that CKL does not cause S1, S2, and S3 to change when CKL is a rising edge signal, and further X does not change, that is, X remains 1, and OUT remains 1.

Since X is kept to be 1, and CLK is a rising edge signal, the signal is processed by the nand gate formed by the sixth PMOS transistor P6, the sixth NMOS transistor P7, the seventh PMOS transistor P7, and the seventh NMOS transistor N7, so that OUT is inverted. In the inversion of OUT, after being processed by the first output circuit 2, CKN2 ↓ (i.e., generating a falling edge) and CKP2 ↓ (i.e., generating a rising edge) are processed by the first output circuit 2; after being processed by the second output circuit 3, CKN1 ↓ (i.e., generating a falling edge) and CKP1 ↓ (i.e., generating a rising edge) are caused to flow.

(3) Clock source signal CLK = 1:

as described earlier, since OUT is flipped to OUT =0, at this time, P8 is turned on, so that FB ≠ to FB =1 when the clock source signal CLK =1;

FB =1 ensures that N2 is turned on (the pull-down module is turned on, and the pull-down effect is turned on), N5 is turned on, and P2 is also turned on (the pull-up module is turned on, and the pull-up effect is turned on), thereby causing S1 to flip (symbols ↓) to S1=0, S2 to flip (symbols ↓) to S2=1, and S3 to flip (symbols ↓) to S3=0, which corresponds to the CKL being the rising edge signal, causing S1, S2, and S3 to change.

Since OUT =0, CKN2=0, ckp2=1 after being processed by the first output circuit 2; after being processed by the second output circuit 3, CKN1=0 and ckp1=1.

And after the delay time is reached, S3=0, so that X is changed from 1 to 0, and the preset time is shorter than the time corresponding to the pulse width of the clock source signal, so that CLK is still kept at 1 at this time, and OUT forms a rising edge until OUT =1 after being processed by the NAND gate.

When OUT =1, P8 is turned on, thereby making FB become 0 again, turning off the second NMOS transistor N2 again, turning off the fifth NMOS transistor N5, and turning off the second PMOS transistor P2.

When the CLK is turned to 0, similar to the case of (1) above, S1 ↓ is 1, S2 ↓ is 0; s2 ↓ ] causes the fourth NMOS tube N4 to be turned on, the fourth PMOS tube P4 to be turned off, and S3 ↓ ] up to 0, thereby ensuring that OUT =1, further causing CKN2 ↓ (i.e., generating a rising edge) to 1, ckp2 ↓ (i.e., generating a falling edge) to 0, CKN1 ↓ (i.e., generating a rising edge) to 1, ckp1 ↓ (i.e., generating a falling edge) to 0, thereby re-entering the stable state.

Referring to the circuit diagram of fig. 4, the first output circuit 2 may include a first inverter and a second inverter, two clock signals output through the first inverter and the second inverter have opposite phases, the second output circuit 3 includes four inverters connected in series, and the second output circuit 3 may also output CKN1 and CKP1 having opposite phases. The signal at OUT (together with the signal at FB) output by the functional circuit may be delayed for a first time period by an inverter in the first output circuit 2, and then a first clock pulse signal CKP2 may be output; the signal at OUT output by the functional circuit may be delayed for a second duration by an inverter in the second output circuit 3, outputting the second clock signal CKP1. In this embodiment, the time difference between the first time period and the second time period is equal to or greater than the time period of the holding time of the shift register of the latter stage in the two-stage shift register shown in fig. 4.

It will be appreciated that the more inverters included in the circuit, the longer the delay is indicated; in the present embodiment or fig. 4, the extended period (second period) of the second output circuit 3 is taken as an example to be longer than the extended period (first period) of the first output circuit 2.

In an application scenario of this embodiment, the method may be applied to the two-stage shift register shown in fig. 3, at this time, when the time difference between the second time length and the first time length is set to be greater than or equal to the time length of the holding time of the next-stage shift register in the two-stage shift register shown in fig. 3, further the CKP2 may be input to the next-stage shift register, and the CKP1 may be input to the previous-stage shift register, so as to ensure that after the current data of the next-stage shift register is latched, the next data is input again, and the accurate storage of the current data is ensured. It should be understood that the delay time period difference of the second output circuit 3 and the first output circuit 2 may also be larger than the holding time period of the latter shift register of the two stages.

5A is a schematic structural diagram of a delay module in the embodiment of the present application; referring to fig. 5A, optionally, in a specific embodiment, the delay module includes several stages of U-shaped delay chains of a chain set, each stage of U-shaped delay chain includes a selector and a delay selection switch (also called a delay device), and the selector is configured to control a delay duration of a current stage of U-shaped delay chain or a delay duration of a next stage of U-shaped delay chain, so as to turn on the several stages of U-shaped delay chains one by one to form a delay chain with different delay times to delay S3 by using different delay devices for different delay times.

5B is a schematic structural diagram of a U-shaped delay chain in the embodiment of the application; referring to fig. 5B, in an alternative embodiment, the structure of the delay chain may include: the Delay circuit comprises n +1 Delay selection switches (Delay Mux, also called as delayers), one Delay selection switch participates in forming a primary U-shaped Delay chain, n is an integer which is more than or equal to 1, the n +1 Delay selection switches form the n + 1-stage U-shaped Delay chain, in addition, the primary U-shaped Delay chain also comprises a selector used for generating gating signals, and each Delay selection switch works or stops working under the control of the corresponding gating signal. Specifically, the gating signals corresponding to the n +1 delay selection switches are EN (0), EN (1).. EN (n-1), EN (n) in sequence. When EN (i) =1, i is more than or equal to 0 and less than or equal to y, the corresponding delay selection switch is effective, the delay function can be achieved, and meanwhile, the delay selection switch corresponding to EN (0) -EN (i-1) is also effective; otherwise, when EN =0, the corresponding delay selection switch does not operate, and does not play a role of delay. When EN =1, it indicates that the U-shaped delay chain of the stage is In series, in goes to Out _ Ext, and Out _ Ext is actually In of the U-shaped delay chain of the next stage, so that the delay circuit is equivalent to passing through two stages of delay circuits, namely, 2 times of delay.

EN (0), EN (1) · EN (n-1), EN (n) are specifically generated by a selector, and the selector specifically performs a logical operation on a hot code (also referred to as one hot) generated by the decoder, thereby generating EN (0), EN (1) ·. EN (n-1), EN (n). The specific principle is as follows: when EN [ i ] =1, the control circuit guarantees EN [ x ] =1 (0 < = x < i), AND since EN [ n ] is a one-hot code structure AND EN [ y ] =0 (i < y < n), assuming EN [ i ] =1 strobe, for the strobe stage AND the pre-strobe stage EN [ x ] (x < i), out is strung through In _ Ext, thereby forming the return path of the U-type loop chain, AND EN [ i +1] =0, in-DelayCell-AND2-Out forms the return path, AND Out _ Ext =0, for EN [ y ] =0 (y > i + 1) stage, since In =0, all output nodes become 0, AND therefore In _ Ext =0 of EN [ i +1] stage, thereby making Out = AND2 output, i.e. forming a U-type loop.

It is assumed that the delay of each delay selection switch is 50 ps/step, i.e., the corresponding delay time is 50ps.

For example, taking EN [0] =1, EN [1] =1, EN [2] =0 as an example, since EN [2] =0, the delay time of the third stage U-shaped delay chain is the last stage delay of this time delay, and the delay time is 150ps; by analogy, when EN (0 n-1) =1, EN (n) =0, the nth stage U-shaped delay chain is the last stage delay of the delay, and the delay time is (n + 1) × 50ps.

In fig. 5B, the In terminal is used for receiving the second output signal, and the Out terminal is used for outputting the delay signal.

Referring to fig. 5B, optionally, in one embodiment, a structure of a Delay selection switch (Delay Mux) includes: the Delay circuit (Delay Cell), two AND gates (AND 1, AND 2), one or gate, AND one not gate, AND the connection relationship of these logic circuit structural components is specifically shown in fig. 5B, which forms a U-shaped structure as a whole. The delay circuit may specifically include: the buffer is used for buffering S3 and outputting the S3 to the input ends of the two AND gates through the multiplexer, and the low level or the high level input in the S3 is output to the input ends of the two AND gates through the multiplexer so as to perform delay processing through the plurality of working delay selection switches or one delay selection switch, and perform delay processing on the S3.

With reference to 5B, the principle of causing the delay time to be 150ps when EN [0] =1, EN 2] =0 is explained in detail as follows:

when EN [2] =0, EN [1] =1, EN [0] =1, S3 will occur, AND will be transmitted from the U-type delay chain enabled by EN [0] by 50ps, then to the U-type delay chain circuit enabled by EN [1], then from the U-type delay chain circuit enabled by EN [1], to the EN [2] circuit, after the U-type delay chain enabled by EN [2] passes through the AND gate (AND 2) in the middle, AND after the OR gate processing, the reverse return is performed, the Out of the U-type delay chain enabled by EN [2], the Out of the U-type delay chain enabled by EN [1], the Out of the U-type delay chain enabled by EN [0], AND finally the output.

Referring to fig. 5B, in the above process, EN [0] =1, AND In the U-shaped delay chain corresponding to EN [0], the output of the not gate is 0, the output of the AND2 is 0, the output of the ANDs 1 is 1, that is, S3 is input to the In end of the U-shaped delay chain corresponding to EN [1], but at this time, when the output of the AND2 is 0, AND In _ Ext is 0, the output of the or gate is 0; EN [1] =1, AND in the corresponding U-shaped delay chain, if the output of the not gate is 0, the output of the AND2 is 0, AND the output of the ANDs 1 is 1, but at this time, in _ Ext is also 0, the output of the or gate is 0; EN [2] =0, AND in the corresponding U-shaped delay chain, the output of the NOT gate is 1, the output of the AND2 is 1, the output of the AND1 is 0, namely the delayed S3 is not input into the U-shaped delay chain corresponding to EN [3 ]; but at this time, the or gate behaves as a buffer, so that Out = AND2. The output of the U-shaped delay chain corresponding to EN [2] is 1, and is sequentially input to EN [1] and the output Out of the U-shaped delay chain corresponding to EN [0 ]. Referring to the above process, in each U-shaped delay chain, since there is one delay circuit, S3 is delayed by 50ps, so that the U-shaped delay chains corresponding to the EN [0], EN [1] and EN [2] are delayed by 3 times in total, and 3 × 50ps =150ps in total.

The embodiment of the utility model provides an in the clock generation circuit, exemplarily, functional circuit 1 receives behind the rising edge signal of clock source signal, through output behind a branch road upset, then through the rising edge of first output circuit and/or second output circuit upset back as the clock pulse signal of new generation, and through feedback loop 4 with the falling edge signal input functional circuit 1 of this upset, with start delay module 11 carry out the delay of predetermineeing time duration (wherein, predetermine time duration and be less than the time duration that clock source signal pulse width corresponds), then functional circuit 1 is based on the feedback signal, utilize NAND gate module 12 to clock source signal with the time delay feedback signal carries out NAND logic operation, thereby realizes clock source signal carries out the back porch and cuts the edge operation, obtains the falling edge of the clock pulse signal of new generation, and then obtains new clock pulse signal. That is to say, the pulse width of the newly generated clock pulse signal can be preset by the delay sub-circuit, and then the clock pulse signal which is arbitrarily smaller than the pulse width of the clock source signal can be obtained, further, when the delay duration of the first output circuit 2 is smaller than the delay duration of the second output circuit 3, and the time difference between the two is greater than or equal to the duration of the holding time of the next shift register in the two shift registers shown in fig. 4, it can be ensured that the next data is input again after the current data latch of the next shift register is completed, thereby ensuring the accurate storage of the current data. That is, a clock signal of a pulse width that meets the requirements of a particular scene may be generated.

The embodiment of the present invention provides a clock generating circuit, which can be a customized standard circuit, for example, can be a clock signal generator, and provide a clock pulse signal for a scene needing the pulse signal, such as: a clock generator that may be a pulse latch, a skew clock generator for a shift register, a multi-way non-overlapping clock generator, etc. For another example: the clock generator can be used as a clock generating circuit in a CPU/CPU and is used for generating a clock pulse signal under a super-large scale calculation scene; the clock generating circuit can also be used as a clock generating circuit in an AI (Artificial Intelligence) chip and is used for generating clock pulse signals under the high-density computing scene; the circuit can also be used as a System-level clock generation circuit such as an SOC (System on Chip)/FPGA (Field Programmable Gate Array) for generating a clock pulse signal in a low power consumption calculation scenario.

The embodiment of the utility model provides a still provide a data arithmetic unit, fig. 6 is the embodiment of the utility model provides an embodiment data arithmetic unit's schematic structure drawing. As shown in fig. 6, the data operation unit 500 includes a control circuit 501, an operation circuit 502, and a plurality of clock circuits 503. The control circuit 501 controls the clock circuit 503 so that the clock circuit 503 generates a clock pulse signal having a predetermined pulse width, and the arithmetic circuit 502 performs arithmetic processing on data according to the clock pulse signal. The clock circuit 503 is the clock circuit in any of the embodiments described above.

The embodiment of the utility model provides a still provide a chip, figure 7 is the utility model discloses in the embodiment of the chip the schematic structure diagram. As shown in fig. 7, the chip 600 includes a control unit 601, and one or more data operation units 500. The control unit 601 inputs data to the data operation unit 500 and processes the data output by the data operation unit 500.

The embodiment of the utility model provides an electronic terminal is still provided, it includes at least one like this application embodiment the chip.

The expressions "first", "second", "first" or "second" used in various embodiments of the present disclosure may modify various components regardless of order and/or importance, but these expressions do not limit the respective components. The above description is only configured for the purpose of distinguishing an element from other elements. For example, the first user equipment and the second user equipment represent different user equipment, although both are user equipment. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.

When an element (e.g., a first element) is referred to as being "operably or communicatively coupled" or "connected" (operably or communicatively) to "another element (e.g., a second element) or" connected "to another element (e.g., a second element), it is understood that the element is directly connected to the other element or the element is indirectly connected to the other element via yet another element (e.g., a third element). In contrast, it is understood that when an element (e.g., a first element) is referred to as being "directly connected" or "directly coupled" to another element (a second element), then no element (e.g., a third element) is interposed between the two.

The above description is only a preferred embodiment of the application and is illustrative of the principles of the technology employed. It will be understood by those skilled in the art that the scope of the present invention is not limited to the specific combination of the above-mentioned features, but also covers other embodiments formed by any combination of the above-mentioned features or their equivalents without departing from the spirit of the present invention. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims (11)

1. A clock generation circuit, the clock generation circuit comprising: the feedback circuit comprises a functional circuit, a first output circuit, a second output circuit and a feedback loop;

the feedback loop is used for generating a feedback signal according to the output signal of the functional circuit;

the functional circuit is used for generating a pulse clock signal according to a clock source signal, generating a delay feedback signal according to the pulse clock signal based on the feedback signal, and generating the output signal according to the delay feedback signal and the clock source signal;

the first output circuit is used for generating a first pulse trigger signal according to the output signal;

the second output circuit is used for generating a second pulse trigger signal according to the output signal, and the time difference between the first pulse trigger signal and the second pulse trigger signal is a specified time length.

2. The clock generation circuit of claim 1,

the clock generation circuit is applied to two stages of shift registers, the specified duration is longer than or equal to the duration of the holding time of the next stage of shift register in the two stages of shift registers, the first pulse trigger signal is used for controlling the previous stage of shift register in the two stages of shift registers, and the second pulse trigger signal is used for controlling the next stage of shift register in the two stages of shift registers.

3. The clock generation circuit of claim 1, wherein the functional circuit comprises: the logic turning module comprises a plurality of stages of phase inverters which are connected in series, wherein the input end of the most front stage of phase inverter is used as the first input end of the functional circuit, and the plurality of stages of phase inverters are used for sequentially turning the clock source signal to generate a pulse clock signal.

4. The clock generation circuit of claim 1, wherein the functional circuit further comprises: the delay module is connected with the logic overturning module; the delay module comprises a selector and a plurality of delay sub-circuits;

each delay sub-circuit corresponds to different delay time and is used for delaying the received pulse clock signal for a corresponding preset time length based on the feedback signal;

and the selector is used for delaying the pulse clock signal for a preset time length according to the delay sub-circuit so as to generate a delay feedback signal based on the feedback signal.

5. The clock generation circuit of claim 4, wherein the functional circuit further comprises: and the NAND gate module is connected with the delay module, and the NAND gate module respectively receives the clock source signal and the time delay feedback signal and is used for performing NAND logic processing on the clock source signal and the time delay feedback signal to obtain the output signal.

6. The clock generation circuit of claim 3,

the logic turnover module comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor;

the grid electrodes of the first PMOS transistor and the first NMOS transistor are connected and are a first input end of the functional circuit; the gate of the second NMOS transistor is a second input terminal of the functional circuit.

7. The clock generation circuit of claim 5,

the nand gate module comprises a sixth PMOS transistor, a seventh PMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor, gates of the sixth PMOS transistor and the sixth NMOS transistor are both connected with the clock source signal, gates of the seventh NMOS transistor and the seventh PMOS transistor are both connected with the delay feedback signal, a drain of the sixth PMOS transistor is connected with a source of the sixth NMOS transistor and connected with the output end of the functional circuit, a drain of the seventh NMOS transistor is grounded, and a drain of the seventh NMOS transistor is connected with the output end.

8. The clock generation circuit of claim 1, wherein the first output circuit comprises a cascade of M-stage inverters configured to invert the output signal an odd number of times and invert the output signal an even number of times to generate the first pulse trigger signal, M being an integer greater than or equal to M.

9. The clock generation circuit of claim 8, wherein the second output circuit comprises a cascade of N-stage inverters configured to invert the output signal an odd number of times and invert the output signal an even number of times to generate the second pulse trigger signal, N being an integer greater than or equal to M.

10. A data arithmetic circuit comprising interconnected control circuitry, arithmetic circuitry and clock generation circuitry, said clock generation circuitry being as claimed in any one of claims 1 to 9.

11. A chip comprising at least one data arithmetic circuit as claimed in claim 10.

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