JP4713130B2 - Flip-flop with scan, semiconductor device, and method for manufacturing semiconductor device - Google Patents

Description

  The present invention relates to a flip-flop with scan that operates at high speed and can be configured with a small number of transistors.

  The area occupied by the flip-flop in the area, power consumption, and critical path delay in the logic circuit of the semiconductor integrated circuit is large, and it is desired to reduce the area of the flip-flop, reduce the power consumption, and increase the speed. In addition, a flip-flop with a scan is often used in order to easily test the designed LSI. In particular, it is important to reduce the area of the flip-flop with a scan, to reduce power consumption, and to increase the speed.

  In recent years, flip-flops using a latch circuit that captures data in a period with a pulse width shorter than a clock cycle have been proposed for high-speed applications. Hereinafter, a conventional example of the flip-flop having such a configuration will be described with reference to the circuit diagrams of FIGS.

  FIG. 11 shows a flip-flop with scan called SDFF (Semi-Dynamic Flip-Flop), which is a configuration example described in Patent Document 1 (hereinafter referred to as Conventional Example 1).

  In FIG. 11, D is a data signal, CK is a clock signal, SI is a test input signal, SCAN is a test selection signal, Q is an output signal, VDD is a VDD power supply, and GND is a GND potential.

  N20 to N23 are nMOS transistors, and a series connection by nMOS transistors N20 and N21 and a series connection by nMOS transistors N22 and N23 are connected in parallel to form a selector circuit S0. In this configuration, data of the nMOS transistor N21 Either the control by the signal D or the control by the test input signal SI of the nMOS transistor N23 is controlled by the test selection signal SCAN inverted by the inverter circuit INV7, the nMOS transistor N22 controlled by the test selection signal SCAN, Are selected exclusively.

  P1 is a pMOS transistor whose source is connected to the VDD power source, N3 is an nMOS transistor whose source is connected to the GND potential, and a clock signal CK is inputted to each gate. An nMOS transistor N1 is connected in series to the drain of the pMOS transistor, and the selector circuit S1 is inserted in series between the source of the nMOS transistor N1 and the drain of the nMOS transistor N3. Here, the connection node between the drain of the pMOS transistor P1 and the drain of the nMOS transistor N1 is X1. The output terminal of the two-input NAND circuit ND1 is connected to the gate of the nMOS transistor N1. A node X1 is input to one input terminal of the NAND circuit ND1, and a clock signal CK is input to the other input terminal after being delayed by two inverter circuits INV1 and INV2. Here, the connection node between the inverter circuit INV2 and one input terminal of the NAND circuit ND1 is CKD.

  The node X1 is connected to the gate of the pMOS transistor P2 whose source is connected to the VDD power source and to the gate of the nMOS transistor N5 whose source is connected to the GND potential. Further, an nMOS transistor N4 receiving a clock signal CK at its gate is inserted in series between the pMOS transistor P2 and the nMOS transistor N5. Here, the output potential obtained from the connection node between the pMOS transistor P2 and the nMOS transistor N4 is the output signal Q.

  The latch circuit constituted by the inverter circuits INV3 and INV4 is connected to the node X1, and the latch circuit constituted by the inverter circuits INV5 and INV6 is connected to the drain of the pMOS transistor that outputs the output signal Q.

  Next, the operation of the flip-flop circuit with scan configured as described above will be described.

  First, the case where the test selection signal SCAN is at a low level, that is, the data signal D is selected will be described.

  While the clock signal CK is at a low level, the pMOS transistor P1 is turned on, so that the potential of the node X1 is at a high level. At this time, since the nMOS transistor N4 and the pMOS transistor P2 are cut off, the output signal Q is held at the previous value.

  Subsequently, when the clock signal CK changes to a high level, the potential of the node CKD does not immediately change to a high level, but changes to a high level after a delay time by the inverter circuits INV1 and INV2. Since the nMOS transistor N1 is on during the period when the clock signal CK is high level and the potential of the node CKD is low level (hereinafter referred to as an evaluation period), if the data signal D is high level during this period The node X1 changes from the high level to the low level, and the output signal Q changes to the high level by the pMOS transistor P2. If the input signal D is at the low level during the evaluation period, the node X1 remains at the high level, and the output signal Q is changed to the low level by the nMOS transistors N4 and N5.

  Subsequently, when the clock signal CK is at a high level and the potential of the node CKD is in a high level state (hereinafter referred to as a holding period), if the potential of the node X1 is at a high level, two inputs Since the nMOS transistor N1 is cut off by the NAND circuit ND1, the high-level potential is held by the inverter circuits INV3 and INV4 without being affected by the value of the data signal D. When the node X1 enters the holding period at the low level, since the pMOS transistor P1 is cut off, the potential of the node X1 is held at the low level by the inverter circuits INV3 and INV4 regardless of the value of the input signal D.

  Usually, the inverter circuit is composed of two MOS transistors, and the 2-input NAND circuit is composed of four MOS transistors. Therefore, the flip-flop circuit of the conventional example 1 shown in FIG. 11 is composed of a total of 28 MOS transistors.

  FIG. 12 shows another configuration example of a flip-flop circuit with scan also called SDFF (hereinafter referred to as Conventional Example 2). Here, the same components as those in FIG. 11 are denoted by the same reference numerals, and the description thereof is omitted.

  12 has the same function as the flip-flop with scan shown in FIG. 11, but in FIG. 11, in order to hold the potential of the node X1 (corresponding to the node n1 in FIG. 12) at a high level in the holding period. The nMOS transistor N1 and the NAND circuit ND1 provided are deleted, and instead, an AND-or inverter circuit AOI1 composed of an OR inverter circuit to which the output of the 2-input AND circuit and the test selection signal SCAN are input, and 2 The difference is in that AOI2 including an OR inverter circuit to which an output of the input AND circuit and a signal obtained by inverting the test selection signal SCAN by the inverter circuit INV7 are input is added. That is, when the data signal D is at a low level and the clock signal CK rises from a low level to a high level, the potential of the node CKD changes from a low level to a high level in the holding period, so that the value of the test selection signal SCAN Regardless, the nMOS transistors N20 and N22 are cut off. Therefore, regardless of the value of the data signal D, the potential of the node X1 is held at a high level and has the same function as the nMOS transistor N1 in FIG.

Here, since the AND-or inverter circuit is normally composed of six MOS transistors, the circuit shown in FIG. 12 is composed of a total of 35 MOS transistors.
US Pat. No. 5,898,330

  However, in the conventional flip-flop with scan shown in FIG. 11, four transistors, nMOS transistors N1, N20, M21, and N3, are operated in series between the node X1 and the ground, and are operated in series. There is a problem that the delay time becomes large in the transition of the potential of the node X1.

  Further, in the conventional flip-flop shown in FIG. 12 in which the number of transistors is reduced by one and the delay time is reduced, the number of transistors is increased by AND-or inverter circuits AOI1 and AOI2 added to maintain the same function. There is a problem that the number of MOS transistors used for the above increases.

  The present invention solves the above problem, and aims to increase the operation speed by reducing the number of transistors in the signal transmission path of the number of serial transistors that perform signal transmission at the time of data input, The purpose is to reduce the number of transistors.

  In order to achieve the above object, the present invention reduces the number of series transistors (discharge transistors) on the data signal input side in the selection circuit that selects when a data signal is input and when a test signal is input. At the same time, on the test signal input side that does not require high-speed operation, the series transistors are not reduced, and an increase in the number of unnecessary transistors due to the reduction is suppressed.

In other words, the flip-flop with scan according to the first aspect of the present invention includes a plurality of nMOS transistors, and receives first logic information including a clock signal, a data signal, a test input signal, and a test selection signal, An input unit that outputs second logical information based on the first logical information; an output unit that receives information based on at least the second logical information and outputs a signal based on the second logical information; A control unit that inputs a control signal for generating the second logic information from the first logic information to the input unit; and the second logic information from the input unit to the output unit. A flip-flop including a first node for transmitting, and the input unit includes a first flip-flop of the first logic information when the clock signal transitions from a low level to a high level. A selection unit that selects whether to generate the second logic information by enabling either the data signal or the test input signal based on the test selection signal, and when the clock signal is at a low level, The second logic information is output as a high level signal to the first node, and the nMOS included in a path through which a current flows when the first node changes from a high level to a low level in the input unit. The number of transistors is smaller when the data signal is selected than when the test input signal is selected.

  According to a second aspect of the present invention, in the flip-flop with scan according to the first aspect, the input unit is first connected to the control unit via first, second and third nodes, and Second, when the clock signal is at a low level, a high level is output to the first node. Third, when the data signal is at a high level, the test selection signal is at a low level, and When the input state transitions from the first state in which the clock signal is at low level to the second state in which the test selection signal is at low level and the clock signal is at high level, the third node If the potential of the first node is high level, the potential of the first node is changed from the high level to the low level within a predetermined time, and the data signal and the test signal are maintained while the second state is maintained. Regardless of the level of the input signal, the potential of the first node is held at a low level. Fourth, when the data signal is at a low level, the first state is changed to the second state. When the input state transitions, the potential of the first node is set to a high level state, and if the potentials of the second and third nodes transition from a high level to a low level after the predetermined time or more, While maintaining the second state, the potential of the first node is held at a high level regardless of the levels of the data signal and the test input signal, and fifth, the test input signal is at a high level. In the third state, from the third state in which the test selection signal is high level and the clock signal is low level, the test selection signal is high level and the clock signal is low. If the second node potential is high level, the first node potential is shifted from the high level to the low level within the predetermined time when the second state is shifted to the fourth state. While maintaining the fourth state, the potential of the first node is held at a low level regardless of the levels of the data signal and the test input signal, and sixth, the test input signal is at a low level. In the case of level, when the third state is shifted to the fourth state, if the potential of the third node is low level, the potential of the first node is set to high level, If the potential of the second node transits from a high level to a low level after elapse of a predetermined time or more, the previous state is maintained regardless of the level of the data signal and the test input signal while maintaining the fourth state. The potential of the first node is held at a high level, and the control unit, when the data signal is at a low level, shifts from the first state to the second state when the data signal is at a low level. The potential of the node 3 is changed from a high level to a low level after elapse of the predetermined time or more, and further, when the test input signal is at a low level, the potential is shifted from the third state to the fourth state. The potential of the second node is changed from a high level to a low level after elapse of the predetermined time or more, the potential of the third node is kept at a low level, and the output unit receives the clock signal When the level is high, a signal obtained by inverting the signal appearing at the first node is output as an output signal. Further, when the clock signal is low level, the level of the previous signal is maintained. The features.

  According to a third aspect of the present invention, in the flip-flop with scan according to the first aspect, the input unit is first connected to the control unit via first, second, and third nodes, and Second, when the clock signal is at a low level, a high level is output to the first node. Third, when the data signal is at a high level, the test selection signal is at a low level, and From the first state where the clock signal is at a low level, when the test selection signal is at a low level and the clock signal is at a second state where the clock signal is at a high level, the third node is at a high level. If so, the potential of the first node is changed from the high level to the low level, and the second state is maintained regardless of the state of the data signal and the test input signal. The potential of the first node is held at a low level, and fourthly, when the data signal is at a low level, the first node is switched from the first state to the second state. And, fifth, when the test input signal is at a high level, the test selection signal is at a high level and the clock signal is at a low level. If the second node is at a high level when the test selection signal is at a high level and the clock signal is at a high level, the potential of the first node is set to a high level. The potential of the first node is held at a low level regardless of the potentials of the data signal and the test input signal during the transition from the low level to the low level and maintaining the fourth state. Sixth, when the test input signal is at a low level and the third node is at a low level when the third state is shifted to the fourth state, the first node First, when the data signal is at a high level, the control unit changes from the high level to the low level when the data signal is shifted from the first state to the second state. In response to the potential change of the first node that makes a transition, the potentials of the second and third nodes are held at a high level, and secondly, the first state when the data signal is at a low level. From the high level to the low level in response to the signal of the first node that maintains the high level when the transition to the second state from the high level to the low level. , Enter the test When the force signal is at the high level, when the third state shifts to the fourth state, the second and third nodes receive the potential change of the first node that changes from the high level to the low level. And fourthly, when the test input signal is at a low level, when the test input signal is shifted from the third state to the fourth state, the high level is maintained. In response to the signal of the first node, the potential of the second node is changed from the high level to the low level, and the potential of the third node is kept at the low level. When the signal is at a level, the output signal is an inverted signal of the signal appearing at the first node. Further, when the clock signal is at a low level, the previous signal level is maintained. And butterflies.

According to a fourth aspect of the present invention, in the flip-flop with scan according to the first aspect, the input unit and the control unit are connected via first, second and third nodes, and the control unit and the output Are connected to each other via the fourth and fifth nodes, and the input unit first outputs a high level to the first node when the clock signal is at a low level. Second, when the data signal is at a high level, the test selection signal is at a low level from the first state in which the test selection signal is at a low level and the clock signal is at a low level, and If the third node is at the high level when the clock signal is shifted to the second state where the clock signal is at the high level, the potential of the first node is shifted from the high level to the low level. While maintaining the state, regardless of the potential of the data signal and the test input signal, the potential of the first node is held at a low level, and thirdly, when the data signal is at a low level, When transitioning from the first state to the second state, the potential of the first node is held at a high level, and fourth, when the test input signal is at a high level, the test selection signal When the test selection signal is at a high level and the clock signal is at a high level, the third state, at which the clock signal is at a low level, shifts to the fourth state in which the clock signal is at a high level. If the second node is at a high level, the potential of the first node is changed from a high level to a low level, and the data signal and the Regardless of the potential of the strike input signal, the potential of the first node is held at the low level, and fifth, when the test input signal is at the low level, the third state to the fourth state When the third node is at a low level, the potential of the first node is held at a high level when the third node is at a low level. When transitioning from the first state to the second state, the first node signal that transitions from a high level to a low level is received, and the potentials of the second and third nodes are held at a high level. At the same time, the potential of the fourth node is held at a high level, the potential of the fifth node is changed from a low level to a high level, and secondly, when the data signal is at a low level, 1's When the state is shifted to the second state, the signal of the first node maintaining the high level is received, the potentials of the second and third nodes are shifted from the high level to the low level, and the first 4, the potential of the node 4 is changed from the high level to the low level, the potential of the fifth node is maintained at the low level, and third, in the case of the test input signal high level, from the third state When the state shifts to the fourth state, the signal of the first node that transitions from a high level to a low level is received, the potential of the second node is held at a high level, and the potential of the third node Is kept at the low level, the potential of the fourth node is held at the high level, the potential of the fifth node is changed from the low level to the high level, and fourth, the test is performed. When the force signal is at the low level, when the state shifts from the third state to the fourth state, the signal of the first node that maintains the high level is received, and the potential of the second node is set to the high level. To the low level, the potential of the third node is kept at the low level, the signal of the fourth node is changed from the high level to the low level, and the potential of the fifth node is changed to the low level. First, when the output unit receives a high level signal from the fourth and fifth nodes, the output unit outputs a high level output signal and a low level inverted output signal. 2. When a low level signal is received from the fourth and fifth nodes, a low level output signal and a high level inverted output signal are output, and third, a high level signal is output to the fourth node. When receiving the signal of the fifth node to the low level, characterized by holding the level of the output signal and the inverted output signal to the previous level.

According to a fifth aspect of the present invention, in the flip-flop with scan according to the first aspect , the number of nMOS transistors when the data signal is selected is three, and the nMOS transistor when the test input signal is selected The number of is four.

According to a sixth aspect of the present invention, in the flip-flop with scan according to the first aspect , the number of nMOS transistors when the data signal is selected is two, and the nMOS transistor when the test input signal is selected The number of is characterized by three.

According to a seventh aspect of the present invention, in the flip-flop with a scan according to the second or third aspect , the control unit firstly changes the second state from the first state when the data signal is at a high level. When a transition is made, a high-level signal is output to the fifth node in response to a potential change of the first node that transitions from a high level to a low level, and second, the data signal is low. In the case of the level, when the transition from the first state to the second state occurs, the signal of the first node that maintains the high level is received and the low level signal is output to the fifth node. Third, when the test input signal is at a high level, the potential of the first node that transitions from a high level to a low level when the third state is shifted to the fourth state. In response, the high level signal is output to the fifth node, and fourthly, when the test input signal is low level, the third state is shifted to the fourth state. Receiving a signal of the first node maintaining the high level, outputting a low level signal to the fifth node, and fifthly, an inverted signal of the fourth node is propagated. And an inverter circuit for propagating an inverted signal of the sixth node to the second node between the sixth node and the second node, and And a 2-input NOR circuit that receives the signal of the node 6 and the test selection signal and outputs the result of the NOR logic operation to the third node.

The invention according to claim 8 is the flip-flop with scan according to claim 7 , wherein the two-input NOR circuit is connected to a ground circuit and a series circuit of two pMOS transistors, one of which is connected to a power supply potential. The inverter circuit is a CMOS inverter, and is composed of one pMOS transistor connected to the power supply potential of the two-input NOR circuit, and the CMOS transistor. The pMOS transistor is shared as one pMOS transistor.

The semiconductor device of the invention of claim 9, wherein the said scan with flip-flop according to any one of claims 1 to 8, a data signal generating circuit for generating the data signal to be input to the scan with flip flops The data signal generation circuit is arranged adjacent to the flip-flop with scan.

According to a tenth aspect of the present invention, there is provided a semiconductor device manufacturing method comprising: a first step of arranging the flip-flop with scan according to any one of the first to ninth aspects; and a data signal of the flip-flop with scan. A second step of disposing a data signal generation circuit to be generated adjacent to the flip-flop with scan; a third step of disposing a circuit other than the data signal generation circuit; and data of the flip-flop with scan And a fourth step of preferentially wiring signals .

As described above, in the invention according to any one of claims 1 to 4, the potential of the first node is set when the data signal is selected by the test selection signal and when the test input signal is selected. The delay time is shortened only when either the data signal or the test input signal is selected by changing the number of nMOS transistors included in the current flow path when changing from high level to low level. The operation can be speeded up, and when the other signal is selected, the speed is not increased unnecessarily, the circuit scale is reduced, and the number of MOS transistors is reduced. That is, it is possible to simultaneously realize speeding up and reduction in circuit scale.

According to the first aspect of the present invention, when the data signal is selected, when the potential of the first node is changed from the high level to the low level, compared to when the test input signal is selected. Since the number of nMOS transistors included in the path through which the current flows is small, this structure makes the operation when the data signal is selected faster than the operation when the test input signal that does not normally require high-speed operation is selected. Thus, high-speed operation can be realized and the number of MOS transistors can be reduced.

According to the fifth aspect of the present invention, the number of nMOS transistors included in the path through which the current flows when the potential of the first node is changed from the high level to the low level is selected by switching with the test selection signal. When the data signal is selected, the number is three, and when the test input signal is selected, the number is four. Similarly, in the invention according to the sixth aspect , when the data signal is selected, the number is two. Since three signals are selected when a signal is selected, this configuration speeds up the operation when a data signal is selected as compared to when a test input signal that normally does not require high-speed operation is selected. As a result, high-speed operation can be realized, and the number of MOS transistors can be reduced.

Subsequently, in the invention according to claim 8 , when the two-input NOR circuit and the inverter circuit for outputting a signal to the second node are configured, the pMOS transistor connected to the power supply potential is shared. It is possible to reduce the number of transistors.

According to the ninth aspect of the present invention, since the circuit for generating the data signal to be input to the flip-flop with scan is arranged adjacent to the flip-flop with scan, noise applied to the data signal can be reduced, and the semiconductor device Can be operated stably.

Furthermore, in the invention described in claim 10 , the first step of arranging the flip-flop with scan and the second step of arranging the data signal generation circuit for generating the data signal of the flip-flop with scan adjacent to the flip-flop with scan , A third step of arranging a circuit other than the data signal generation circuit, and a fourth step of preferentially wiring the data signal of the flip-flop with scan, so that noise added to the data signal is reduced. It is possible to manufacture a semiconductor device that can be reduced in size and operate stably .

  As described above, according to the invention described in any one of claims 1 to 4, the first signal is selected when the data signal is selected by the test selection signal and when the test input signal is selected. Only when either the data signal or the test input signal is selected due to the difference in the number of nMOS transistors included in the path through which the current flows when changing the potential of the node from high level to low level The delay time can be shortened, the operation speed can be increased, and when the other signal is selected, the speed is not increased unnecessarily, the circuit scale can be reduced and the number of MOS transistors can be reduced. And a reduction in circuit scale can be realized at the same time.

According to the first aspect of the present invention, the potential of the first node is changed from the high level to the low level when the data signal is selected as compared to when the test input signal is selected. Since the number of nMOS transistors included in the path through which current flows is small, the structure operates when a data signal is selected as compared to the operation when a test input signal that does not normally require high-speed operation is selected. By speeding up, it is possible to realize high speed operation and reduce the number of MOS transistors.

According to the fifth aspect of the present invention, the number of nMOS transistors included in the path through which the current flows when the potential of the first node is changed from the high level to the low level is selected by switching with the test selection signal. Thus, when the data signal is selected, the number is three, and when the test input signal is selected, the number is four. Similarly, according to the invention described in claim 6 , when the data signal is selected, the number is two. In addition, when the test input signal is selected, the number is three. With such a configuration, the operation when the data signal is selected is compared with the case where the test input signal that normally does not require high-speed operation is selected. By increasing the speed, high-speed operation can be realized and the number of MOS transistors can be reduced.

Subsequently, according to the eighth aspect of the invention, when the two-input NOR circuit and the inverter circuit that outputs a signal to the second node are configured, the pMOS transistor connected to the power supply potential is shared. Thus, the number of MOS transistors can be reduced.

According to the invention of claim 9, since the circuit for generating the data signal to be input to the flip-flop with scan is arranged adjacent to the flip-flop with scan, noise applied to the data signal can be reduced, The semiconductor device can be stably operated.

According to the tenth aspect of the present invention, the first step of arranging the flip-flop with scan and the data signal generation circuit for generating the data signal of the flip-flop with scan are arranged adjacent to the flip-flop with scan. Since it has a second step, a third step for arranging circuits other than the data signal generation circuit, and a fourth step for preferentially wiring the data signal of the flip-flop with scan, it is added to the data signal. It is possible to manufacture a semiconductor device that can reduce noise and operate stably .

  Hereinafter, a flip-flop with scan, a semiconductor device, and a method of manufacturing the semiconductor device according to embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
First, a first embodiment of the present invention will be described.

  FIG. 1 is a circuit diagram showing a flip-flop with scan according to this embodiment, and FIG. 2 is a timing chart showing the operation thereof.

  In FIG. 1, D is a data signal, CK is a clock signal, SI is a test input signal, SCAN is a test selection signal (data signal, clock signal, test input signal, first logic information of the test selection signal), and Q is an output. Signal, VDD indicates a VDD power supply, and GND indicates a GND potential.

  AOI1 is an AND-OR circuit that outputs an operation result of NOR logic between the output of the 2-input AND circuit and the test selection signal SCAN, ND1 is a 2-input NAND circuit, N20 to N24 are nMOS transistors, and nMOS transistors N20 and N20 The selector circuit S1 is configured by connecting the series connection by N21 and the series connection by nMOS transistors N22, N23, and N24 in parallel.

  P1 is a pMOS transistor whose source is connected to the VDD power source, N3 is an nMOS transistor whose source is connected to the GND potential, and a clock signal CK is inputted to each gate. The selector circuit S1 is inserted between the drain of the pMOS transistor P1 and the drain of the nMOS transistor N3. Here, the connection node between the drain of the pMOS transistor P1 and the drain of the nMOS transistor N1 is the first node X1. A latch circuit composed of inverter circuits INV3 and INV4 is connected to the node X1 at the output terminal of the inverter circuit INV3, whereby the potential of the node X1 is latched.

  In the AND-or inverter circuit AOI1, the node X1 is connected to one input terminal, and a signal obtained by delaying the clock signal CK by the two inverter circuits INV1 and INV2 is input to the other input terminal. Here, the connection between the output terminal of the inverter circuit INV2 and the AND-or inverter circuit AOI1 is defined as a node CKD.

  In the selector circuit S1, the output terminal of the AND-or inverter circuit AOI1 is connected to the gate of the nMOS transistor N20, and a test selection signal is input to the gate of the nMOS transistor N23. A data signal D is input to the gate of the nMOS transistor N21, and a test input signal SI is input to the gate of the nMOS transistor N24. As a result, the AND or inverter circuit operates as an inverter circuit for the test selection signal SCAN except when both of the two signals input to the AND circuit of the AND or inverter circuit are at a high level. When the level is high, the nMOS transistor N20 is turned off and N23 is turned on, so that the selector circuit S1 operates on the data signal D, thereby reaching the GND potential from the node X1 through the nMOS transistors N20, N21 and N3. The current path is cut off. When the test selection signal SCAN is at a low level, the nMOS transistor N20 is turned on and N23 is turned off, so that the selector circuit S1 operates on the test input signal SI and the nMOS transistors N22, N23, N24 from the node X1. And the path of the current through N3 to the GND potential is cut off. When the two signals input to the AND circuit of the AND-or inverter circuit AOI1 are both at the high level, the output signal of the AND-or inverter circuit AOI1 is always at the low level regardless of the value of the test selection signal SCAN. Cut off N20. Further, the output terminal of the two-input NAND circuit ND1 is connected to the gate of the nMOS transistor N22 of the selector circuit S1. Thus, when both the two input signals of the NAND circuit ND1 are at the high level, the nMOS transistor N22 is turned off by outputting a low level signal, and when the two input signals are in other combinations, the high level signal is output. By outputting a signal, the nMOS transistor N22 is turned on. As described above, the operation of the input unit 11 including the pMOS transistor P1 and the six nMOS transistors N20 to N24 and N3 constitutes the AND-or inverter circuit AOI1, the inverter circuits INV1 and INV2 constituting the delay circuit, and the latch circuit. Control is performed by a control unit 21 including inverter circuits INV3 and INV4 and a NAND circuit ND1.

  Further, the node X1 is connected to the gate of the pMOS transistor P2 whose source is connected to the VDD power source and to the gate of the nMOS transistor N5 whose source is connected to the GND potential. Further, an nMOS transistor N4 receiving a clock signal CK at its gate is inserted in series between the pMOS transistor P2 and the nMOS transistor N5. Here, the potential obtained from the connection node between the pMOS transistor P2 and the nMOS transistor N4 becomes the output signal Q of the flip-flop circuit. This output signal Q is composed of inverter circuits INV5 and INV6, and is latched by a latch circuit connected to the drain of the pMOS transistor P2. With this configuration, when the clock signal CK is at a high level, the nMOS transistor N4 is turned on, and the pMOS transistor P2 and the nMOS transistor N5 output an output signal Q obtained by inverting the potential (second logic information) of the node X1. Works as an inverter. Further, since the nMOS transistor N4 is turned off when the clock signal CK is at a low level, if the potential of the node X1 is at a high level, the value of the output signal Q is set by the latch circuit composed of the inverter circuits INV5 and INV6. If the value is held and the potential of the node X1 is low level, the pMOS transistor P2 is turned on, and the output signal Q becomes high level. As described above, the output unit 31 including the pMOS transistor P2, the nMOS transistors N4 and N5, and the inverter circuits INV5 and INV6 outputs the signal Q based on the node X1.

  Next, the operation of the flip-flop circuit with scan having the above configuration will be described with reference to the timing chart of FIG.

  First, the case where the test selection signal SCAN is at the low level and the output signal Q is determined depending on the data signal D will be described (period t1 to t7 in FIG. 2).

  During a period in which the clock signal CK is at a low level (corresponding to periods t1, t4, and t7 in FIG. 2, the first state), the pMOS transistor P1 is turned on, so that the node X1 becomes a high level. At this time, since the nMOS transistor N4 and the pMOS transistor P2 are turned off, the potential of the output signal Q is held at the previous value.

  Next, when the clock signal CK transits to a high level, the node CKD does not immediately transit to a high level, but transits to a high level with a delay by a delay time generated by the inverter circuits INV1 and INV2. In a period in which the clock signal CK is at a high level and the node CKD is at a low level (corresponding to periods t2 and t5 in FIG. 2; the initial state of the second state; hereinafter referred to as an evaluation period), the AND-or inverter circuit AOI1 Since the output becomes high level and the nMOS transistor N20 is turned on, if the data signal D is high level during this period, the potential of the node X1 is changed from high level to low level via the nMOS transistors N20, N21, and N3. To change. As a result, the pMOS transistor P2 is turned on, and the output signal Q changes to the high level. On the other hand, if the data signal D is at the low level during the evaluation period (predetermined time), the node X1 remains at the high level, and the output signal Q is shifted to the low level by the nMOS transistors N4 and N5.

  Subsequently, the clock signal CK is at a high level and the node CKD is at a high level (corresponding to the period between t3 and t6 in FIG. 2. A state after a predetermined time or more has passed since the transition to the second state. (Hereinafter referred to as the holding period), if the node X1 is at a high level at this time, the nMOS transistor N20 is cut off by the AND-or inverter circuit AOI1, and therefore the value of the data signal D is not affected. The high level state is held by a latch circuit including inverter circuits INV3 and INV4. Further, when the node X1 enters the holding period at a low level, the pMOS transistor P1 is cut off, so that the potential of the node X1 is low by the latch circuit including the inverter circuits INV3 and INV4 regardless of the value of the data signal D. The level is retained.

  Next, a case where the test selection signal SCAN is at a high level, that is, a case where the test input signal SI is selected will be described. (Corresponding to the period from t11 to t17 in FIG. 2).

  During a period in which the clock signal CK is at a low level (corresponding to periods t11, t14, and t17 in FIG. 2 and in a third state), the node X1 is set to a high level by the pMOS transistor P1. At this time, since the nMOS transistor N4 and the pMOS transistor P2 are cut off, the output signal Q is held at the previous value. Subsequently, in the evaluation period (corresponding to the periods t12 and t15 in FIG. 2 and within a predetermined time after the transition to the fourth state), the node CKD is at the low level, so the output of the NAND circuit ND1 is Since the nMOS transistor N22 is turned on and the nMOS transistor N22 is turned on, if the test input signal SI is at the high level during this period, the node X1 changes from the high level to the low level, and the output signal Q is changed to the high level by the pMOS transistor P2. Transition to. On the other hand, if the test input signal SI is at the low level during the evaluation period, the node X1 remains at the high level, and the output signal transitions to the low level by the nMOS transistors N4 to N5 that are in the on state. Subsequently, the period shifts to a holding period (corresponding to periods t13 and t16 in FIG. 2; a state after a predetermined time has elapsed since the transition to the fourth state). For example, since both inputs of the NAND circuit ND1 are at a high level, the nMOS transistor N22 is cut off, so that the potential of the node X1 is not affected by the value of the test input signal SI, and the potential of the node X1 is the inverter circuits INV3 and INV4. Is held at a high level by the latch circuit. On the other hand, when the node X1 enters the holding period at the low level, since the pMOS transistor P1 is cut off, the low level of the node X1 is the latch composed of the inverter circuits INV3 and INV4 regardless of the value of the test input signal SI. The low level is held by the circuit.

  Usually, the inverter circuit is composed of 2 MOS transistors, the 2-input NAND circuit is composed of 4 MOS transistors, and the AND-or inverter circuit is composed of 6 MOS transistors, so that the flip-flop in FIG. A transistor is used.

  As described above, according to the present embodiment, the number of MOS transistors is increased by four compared with the circuit of the conventional example 1 of FIG. 11, but the number of series stages of nMOS transistors to which a data signal is applied is increased from four to three. The speed during operation can be improved. At the time of a test operation that does not require high-speed operation compared to the time of operation, the number of nMOS transistors connected to the test input signal SI is set to four, so that the MOS transistor 35 is compared with the circuit of the conventional example 2 of FIG. The number can be reduced from 32 to 32. As described above, it is possible to simultaneously increase the speed during normal operation and reduce the circuit area.

(Second Embodiment)
The scan flip-flop according to the second embodiment of the present invention will be described below with reference to the drawings.

  FIG. 3 is a circuit diagram showing the flip-flop with scan according to this embodiment, and FIG. 4 is a timing chart showing the operation thereof.

  In the flip-flop with scan shown in FIG. 3, the input unit 11 includes the pMOS transistor P1 and the nMOS transistors N20 to N24 and N3 on the input side, and the pMOS transistor P2, nMOS transistors N4 and N5 and the inverter circuits INV5 and 6 on the output side. Since the output unit 31 formed of a latch circuit has the same configuration as that shown in FIG. 1 in the first embodiment, the description thereof is omitted.

  In the present embodiment, in the selector circuit S1 including five nMOS transistors N20 to N24, the gate of the nMOS transistor N20 (third node X3 in FIG. 3) and the gate of N22 (second node in FIG. 3). The control unit 22 that generates the control signal input to X4) is different from that of the first embodiment. The configuration will be described below.

  N6 and P4 are an nMOS transistor and a pMOS transistor that constitute a transmission gate, and are connected in series at the fourth node X2 with a pMOS transistor P3 whose source is connected to the VDD power source. Here, the clock signal CK is input to the gate of the pMOS transistor P3 and the gate of the nMOS transistor N6, and the first node X1 is connected to the gate of the pMOS transistor P4.

  The inverter circuits INV3 and INV4 form a latch circuit as in the first embodiment, and the output side of the inverter circuit INV4 is connected to the source of the nMOS transistor that forms the transmission gate. The input side of the opposite inverter circuit INV4 is connected to the node X1. As a result, the latch circuit including the inverter circuits INV3 and INV4 latches the potential of the node X1 and propagates the inverted potential of the node X1 to the source of the nMOS transistor N6.

  The node X2 is connected to the input terminal of the inverter circuit INV1, and is further connected to the gate of the nMOS transistor N22 of the input unit 11 through the inverter circuit INV2 connected in series with the inverter circuit INV1. A connection node (sixth node) between the output terminal of the inverter circuit INV1 and the input terminal of the inverter circuit INV2 is connected to one input terminal of the two-input NOR circuit NR1. The test input signal SCAN is input to the other input terminal of the NOR circuit NR1, and the output terminal is connected to the gate of the nMOS transistor N20.

  The data signal D is input to the gate of the nMOS transistor N21, the test selection signal SCAN is input to the gate of the nMOS transistor N23, and the test input signal SI is input to the gate of the nMOS transistor N24 in the first embodiment. Is the same.

  With the above configuration, when the test selection signal SCAN is at the low level, the nMOS transistor N23 is turned off, and the current path from the node X1 to the GND potential through the nMOS transistors N22, N23, N24, and N3 is cut off. Here, if the clock signal CK is high level and the output of the NOR circuit NR1 is high level, the value of the node X1 is determined by the value of the data signal D. Therefore, the output signal Q is also determined depending on the data signal D. When the test selection signal SCAN is at a high level, the output of the NOR circuit NR1 is at a low level, so that the nMOS transistor N20 is turned off and a current path from the node X1 to the GND potential through the nMOS transistors N20, N21, and N3. Is cut off. Here, the value of the potential of the node X1 is determined by the test input signal SI when the clock signal CK is at a high level and the output of the node X4 is at a high level. Therefore, the output signal Q is also determined depending on the test input signal SI.

  The operation of the flip-flop with scan according to this embodiment will be described below with reference to FIGS.

  First, the case where the test selection signal SCAN is at a low level and the output signal Q is determined depending on the data signal D will be described (corresponding to the period from t1 to t7 in FIG. 4).

  During a period in which the clock signal CK is at a low level (corresponding to periods t1, t4, and t7 in FIG. 4, the first state), the potential of the node X1 is set to the high level by the pMOS transistor P1, and the node X2 is set by the pMOS transistor P3. Becomes a high level. At this time, since the nMOS transistor N4 and the pMOS transistor P2 are cut off, the output signal Q is held at the previous value.

  During the period when the clock signal CK is at the high level and the node X3 is at the high level (corresponding to the periods t2 and t5 in FIG. 4 and within a predetermined time after shifting to the second state), the nMOS transistors N20 and N3 Since the data signal D is at the high level during this period, the potential of the node X1 changes from the high level to the low level. At this time, the output of the inverter circuit INV4 changes from the low level to the high level. Therefore, the potentials of the nodes X2 and X3 are kept at a high level (corresponding to a period t3 in FIG. 4; a state after a predetermined time or more has elapsed since the transition to the second state). At this time, since the node X1 becomes low level, the pMOS transistor P2 is turned on, and the output signal Q changes to high level. If the input terminal D is at the low level, the node X1 remains at the high level, the output of the inverter circuit INV4 also remains at the low level, and the nMOS transistor N6 is on so that the node X3 is at the low level. Transition to. At this time, when the nMOS transistors N4 and N5 are turned on, the output signal Q shifts to a low level.

  When the clock signal CK is at a high level and the node X3 is at a low level (corresponding to a period t6 in FIG. 4; a state after a predetermined time has elapsed since the transition to the second state), Since the nMOS transistor N20 is cut off, the level of the node X1 is held by the latch circuit formed by the inverter circuits INV3 and INV4 without being affected by the value of the data signal D. Further, when the clock signal CK is at a high level and the node X1 is at a low level, the pMOS transistor P1 is cut off, so that the latch circuit constituted by the inverter circuits INV3 and INV4 does not depend on the value of the data signal D. Node X1 maintains a low level.

  Next, a case where the test selection signal SCAN is at a high level and the output signal Q is determined depending on the test input signal SI will be described (period t11 to t17 in FIG. 4).

  During the period in which the clock signal CK is at a low level (corresponding to the periods t11, t14, and t17 in FIG. 4 and the third state), the potential of the node X1 becomes high level by turning on the pMOS transistor P1, When the pMOS transistor P3 is turned on, the potential of the node X2 becomes high level. At this time, since the nMOS transistor N4 and the pMOS transistor P2 are cut off, the output signal Q is held at the previous value.

  In a period in which the clock signal CK is at a high level and the potential of the node X4 is at a high level (corresponding to periods t12 and t15 in FIG. 4, within a predetermined time after shifting to the fourth state), the nMOS transistor Since N22 is turned on, if the test input signal SI is at a high level during this period, the potential of the node X1 changes from a high level to a low level. At this time, the output of the inverter circuit INV4 changes from the low level to the high level. Therefore, the potentials of the nodes X2 and X3 are maintained at a high level (corresponding to a period t13 in FIG. 4; a state after a predetermined time or more has elapsed since the transition to the fourth state). At this time, since the pMOS transistor P2 is turned on, the output signal Q shifts to a high level. On the other hand, if the input terminal D is at the low level, the potential of the node X1 remains at the high level, the output of the inverter circuit INV4 also remains at the low level, and the nMOS transistor N6 is in the on state. Transition from level to low level. Then, the node X4 that is the output of the inverter circuit INV2 transitions to a low level. At this time, the output signal Q is changed to a low level by the nMOS transistors N4 and N5.

  When the clock signal CK is at a high level and the node X4 is in a low level state (corresponding to the period t16 in FIG. 4; a state after a predetermined time or more has passed since the transition to the fourth state), the nMOS Since the transistor N22 is cut off, the level of the node X1 is held by the inverter circuits INV3 and INV4 without being affected by the value of the test input signal SI. When the clock signal CK is at a high level and the potential of the node X1 is at a low level, the pMOS transistor P1 is cut off, so that the inverter circuits INV3 and INV4 cause the node X1 to be connected regardless of the value of the test input signal SI. The potential is maintained at a low level.

  Normally, the inverter circuit is composed of two MOS transistors, and the 2-input NOR circuit is composed of four MOS transistors. Therefore, the flip-flop with scan of this embodiment shown in FIG. 3 is composed of a total of 29 MOS transistors. .

  As described above, according to the present embodiment, the number of MOS transistors is increased by one compared to the circuit diagram of Conventional Example 1 in FIG. 11, but the number of nMOS transistors to which data signal D is applied is increased from four in series. The number can be reduced to three, and the speed during operation can be improved. Compared to the circuit of the conventional example 2 in FIG. 12, since the number of nMOS transistors to which the test input signal SI is applied is set to four in the test operation where high speed operation is not required compared to the operation, the MOS transistor The number can be reduced by 6 from 35 to 29. In this way, it is possible to simultaneously increase the speed during normal operation and reduce the circuit area.

(Third embodiment)
FIG. 5 is a circuit diagram showing the flip-flop with scan according to this embodiment, and FIG. 6 is a timing chart showing the operation thereof. In the present embodiment, elements constituting the same circuit as the circuit diagrams shown in FIGS. 1 and 3 in the first and second embodiments are denoted by the same reference numerals, and the description thereof is omitted. .

  In the present embodiment, the input unit 12 including the pMOS transistor P1, the nMOS transistors N3, and N20 to N24 is such that the selector circuit S1 including the nMOS transistors N20 to N24 is connected between the nMOS transistor N3 and the GND potential. However, the second embodiment is different from the second embodiment.

  In FIG. 3, the nMOS transistor N6 and the pMOS transistor P4, which are connected in series to the pMOS transistor P3 and constitute the transmission gate, are different from the pMOS transistor P3 in the circuit of FIG. 5 in the present embodiment. The pMOS transistor P4 is connected in series and inverts the value of the clock signal CK and outputs the inverted signal to the fourth node X2. The pMOS transistor P4 has a source connected to the VDD power supply and a drain connected to the node X2. 23.

  Further, in FIG. 1 and FIG. 3, the circuit of the output unit 31 constituted by the pMOS transistor P2, the nMOS transistors N4 and N5, and the inverter circuits INV5 and INV6 is the same as the source in FIG. A pMOS transistor P2 to be connected and an nMOS transistor N4 whose source is connected to the GND potential, a pMOS transistor P5 whose source is connected to the VDD power source, an nMOS transistor N8 whose source is connected to the GND potential, and an nMOS transistor N8 inserted therebetween. The nMOS transistor N7 is connected in series and an inverter circuit INV5. Here, the node X2 is connected to the gates of the pMOS transistor P2 and the nMOS transistor N7, and the output terminal Q is connected to the gates of the pMOS transistor P5 and the nMOS transistor N8. Further, the connection node of the pMOS transistor P2 and the nMOS transistor N4 has a gate of the pMOS transistor P4, an input terminal of the inverter circuit INV5, a connection node of the pMOS transistor P5 and the nMOS transistor N7, and an inverted output for outputting an inverted output signal. Signal terminal NQ is connected. The output terminal of the inverter circuit INV5 is connected to the gate of the pMOS transistor P5, that is, the output signal terminal Q. Thus, the output unit 32 is configured in the present embodiment.

  In the above configuration, when the test selection signal SCAN is at a low level, the nMOS transistor N23 is turned off, and the current path from the first node X1 through the nMOS transistors N3, N22, N23, N24 to the ground GND is cut off. . Here, if the clock signal CK is at a high level and the node X3 that is the output of the NOR circuit NR1 is at a high level, the value of the node X1 is determined by the value of the data signal D. Therefore, the output signal Q and the inverted output signal NQ are also determined depending on the data signal D. Further, when the test selection signal SCAN is at a high level, the NOR circuit NR1 outputs a low level signal to the node X3, so that the nMOS transistor N20 is turned off and a current from the node X1 to the ground GND through the nMOS transistors N20, N21, N3. The path of is cut off. Therefore, when the clock signal CK is high level and the potential of the node X4 is high level, the value of the node X1 is determined by the test input signal SI. Therefore, the output signal Q and the inverted output signal NQ are also determined depending on the test input signal SI.

  Hereinafter, the operation of the flip-flop with scan according to this embodiment will be described with reference to FIGS.

  First, a case where the test selection signal SCAN is at a low level and the output signal Q is determined depending on the data signal D will be described (period t1 to t7 in FIG. 6).

  During a period in which the clock signal CK is at a low level (corresponding to periods t1, t4, and t7 in FIG. 6; the first state), the node X1 is set to a high level by the pMOS transistor P1, and the node X2 is set to a high level by the pMOS transistor P3. Become a level. At this time, since the nMOS transistor N4 and the pMOS transistor P2 are cut off, the output signal Q is held at the previous value by the inverter circuit INV5, the pMOS transistor P5, and the nMOS transistors N7, N8.

  During a period in which the clock signal CK is at a high level and the node X3 is at a high level (corresponding to the periods t2 and t5 in FIG. 6, within a predetermined time after shifting to the second state), the nMOS transistor N20 is turned on. Therefore, if the data signal D is at high level during this period, the node X1 changes from high level to low level. At this time, the output (fifth node) of the inverter circuit INV4 changes from the low level to the high level. Therefore, the nodes X2 and X3 are kept at the high level (a state after a predetermined time or more has elapsed since the transition to the second state during the period t3 in FIG. 6). At this time, the nMOS transistor N4 is turned on, the inverted output signal NQ transitions to a low level, and the output signal Q transitions to a high level. If the input terminal D is at low level, the node X1 remains at high level, the output of the inverter circuit INV4 also remains at low level, and the nMOS transistor N6 is on, so that the node X2 transitions from high level to low level. To do. Then, the node X3 that is the output of the NOR circuit NR1 transitions to a low level. At this time, the pMOS transistor P2 is turned on, the inverted output signal NQ transitions to the high level, and the output signal Q transitions to the low level.

  When the clock signal CK is at a high level and the node X3 is at a low level (corresponding to a period t6 in FIG. 6; a state after a predetermined time or more has elapsed since the transition to the second state), the nMOS transistor N20 Is cut off, the level of the node X1 is held by the inverter circuits INV3 to INV4 without being affected by the value of the data signal D. When the clock signal CK is at the high level and the node X1 is at the low level, the pMOS transistor P1 is cut off, so that the node X1 is maintained at the low level by the inverter circuits INV3 to INV4 regardless of the value of the data signal D.

  Next, the case where the test selection signal SCAN is at the high level and the output signal Q is determined depending on the test input signal SI will be described (period t11 to t17 in FIG. 6).

  During a period in which the clock signal CK is at a low level (corresponding to periods t11, t14, and t17 in FIG. 4; the third state), the node X1 is set to the high level by the pMOS transistor P1, and the node X2 is set to the high level by the pMOS transistor P3. Become a level. At this time, since the nMOS transistor N4 and the pMOS transistor P2 are cut off, the inverted output signal NQ and the output signal Q are held at the previous values by the inverter circuit INV5, the pMOS transistor P5, and the nMOS transistors N7 and N8.

  During the period when the clock signal CK is at the high level and the node X4 is at the high level (corresponding to the periods t12 and t15 in FIG. 6 and within a predetermined time after shifting to the fourth state), the nMOS transistor N22 is turned on. Therefore, if the test input signal SI is at a high level during this period, the node X1 changes from a high level to a low level. At this time, the output of the inverter circuit INV4 changes from the low level to the high level. Therefore, the nodes X2 and X3 are kept at a high level (corresponding to a period t13 in FIG. 6; a state after a predetermined time or more has elapsed since the transition to the fourth state). At this time, the nMOS transistor N4 is turned on, the inverted output signal NQ transitions to the low level, and the output signal Q transitions to the high level. If the input terminal D is at low level, the node X1 remains at high level, the output of the inverter circuit INV4 also remains at low level, and the nMOS transistor N6 is on, so that the node X2 transitions from high level to low level. To do. Then, the node X4 that is the output of the inverter circuit INV2 transitions to a low level. At this time, the pMOS transistor P2 is turned on, the inverted output signal NQ transitions to the high level, and the output signal Q transitions to the low level.

  When the clock signal CK is at the high level and the node X4 is at the low level (corresponding to the period t16 in FIG. 6; a state after a predetermined time or more has passed since the transition to the fourth state), the nMOS transistor N22. Is cut off, the level of the node X1 is held by the inverter circuits INV3 to INV4 without being affected by the value of the test input signal SI. When the clock signal CK is at the high level and the node X1 is at the low level, the pMOS transistor P1 is cut off, so that the node X1 is maintained at the low level by the inverter circuits INV3 to INV4 regardless of the value of the test input signal SI.

  Since the normal inverter circuit is composed of two MOS transistors and the two-input NOR circuit is composed of four MOS transistors, the flip-flop with scan of this embodiment shown in FIG. 5 is composed of a total of 29 MOS transistors.

  As described above, according to the present embodiment, the number of MOS transistors is increased by one compared with the circuit of the conventional example 1 of FIG. 11, but the number of nMOS transistors to which a data signal is added can be reduced from four to three. , The speed during operation can be improved. In a test operation that does not require a high-speed operation compared to the operation, the number of nMOS transistors to which a test input signal is applied is set to four, so that the number of MOS transistors is reduced from 35 compared to the circuit of the conventional example 2 in FIG. It is possible to reduce 6 to 29. In this way, it is possible to simultaneously increase the speed during normal operation and reduce the circuit area.

  In the present embodiment, the nMOS transistor N3 to which the clock signal CK is input is located on the side closer to the node X1, but may be located on the side closer to the ground GND. Further, the nMOS transistor N7 can be deleted if the current driving capability of the nMOS transistor N8 is set to be smaller than about 1/5 of the pMOS transistor P3. At this time, a flip-flop with a scan can be constituted by a total of 28 MOS transistors.

  In the example of FIG. 5, the gate of the pMOS transistor P4 is connected to the inverting output terminal NQ, but may be connected to the node X1 as shown in FIG.

(Fourth embodiment)
FIG. 8 is a circuit diagram showing the flip-flop with scan according to the present embodiment. In the present embodiment, the elements constituting the same circuit as the circuit diagrams shown in FIGS. 1, 3, and 5 in the first to third embodiments are denoted by the same reference numerals, and the description thereof is omitted. To do.

  The inverter circuit INV2 in the third embodiment is a CMOS inverter circuit including a pMOS transistor P6 and an nMOS transistor N9 in the present embodiment, and the NOR circuit NR1 in the third embodiment is the same as that in the present embodiment. The pMOS transistor P7 whose source is connected to the node X4 is connected in parallel to the nMOS transistors N10 and N11 in series. Further, the pMOS transistor P6 of the inverter circuit INV2 is shared as a pMOS transistor connected in series. A test selection signal SCAN is input to the gate of the pMOS transistor P7 and the gate of the nMOS transistor N10, and the gate of the pMOS transistor P6 is connected to the gate of the nMOS transistor N11. The drain of the pMOS transistor P7 is connected to the gate of the nMOS transistor N20 in the input unit 12. Thus, the control unit 24 is configured in the present embodiment.

  With the above configuration, the number of MOS transistors in this embodiment can be reduced as compared with the third embodiment, that is, one pMOS transistor shared by the pMOS transistor P6 in FIG.

  As described above, according to the present embodiment, the number of MOS transistors is the same as that of the circuit of Conventional Example 1 in FIG. 11, and the number of nMOS transistors to which a data signal is applied can be reduced from four to three. Can be improved. In a test operation that does not require a high-speed operation compared to the operation, the number of nMOS transistors to which a test input signal is applied is set to four, so that the number of MOS transistors is reduced from 35 compared to the circuit of the conventional example 2 in FIG. 7 can be reduced to 28. In this way, it is possible to simultaneously increase the speed during normal operation and reduce the circuit area.

  In the example of FIG. 8 in the present embodiment, the gate of the pMOS transistor P4 is connected to the inverting output terminal NQ. However, as shown in FIG. 9, it may be connected to the node X1.

(Fifth embodiment)
A semiconductor device and a method for manufacturing the semiconductor device according to the fifth embodiment of the present invention will be described below with reference to the drawings.

  FIG. 10 is a flowchart showing a method for manufacturing the semiconductor device of the present embodiment. A first step S1 for disposing a flip-flop with scan; a second step S2 for disposing a data signal generation circuit for generating a data signal of the flip-flop with scan; adjacent to the flip-flop with scan; The circuit includes a third step S3 for arranging a circuit and a fourth step S4 for preferentially wiring the data signal of the flip-flop with scan.

  According to this embodiment, the wiring length of the data signal D can be shortened, and the noise (crosstalk noise) added by the transition of the wiring adjacent to the data signal D can be reduced. As a result, malfunction due to crosstalk noise added to the data signal D during the period from when the clock signal changes to when the output changes can be prevented. In particular, in the case of the dynamic circuit configuration in which the data signal D enters only the nMOS transistor as shown in the conventional example 1, the conventional example 2, and the first to fourth embodiments, the CMOS configuration in which both the pMOS transistor and the nMOS transistor enter The method of manufacturing a semiconductor device according to the present embodiment is effective because it is more susceptible to noise than

  According to this embodiment, a semiconductor device that operates stably can be manufactured.

(Sixth embodiment)
13 and 14 are circuit diagrams illustrating the flip-flop with scan according to the present embodiment. In the present embodiment, elements that constitute the same circuit as the circuit diagram shown in FIG. 5 in the third embodiment are denoted by the same reference numerals, and description thereof is omitted.

  In FIG. 13, D1 to DN represent a plurality of input signals, and B represents an nMOS logic block which is a logic circuit composed of nMOS transistors.

  14, D1 and D2 are data input signals, DX1 is a data selection signal, SL1 and SL2 are signals obtained based on the data selection signal DX1, and N25 to N28 are nMOS transistors.

  The flip-flop circuit with scan shown in FIG. 13 has a configuration in which the nMOS transistor N20 of the third embodiment shown in FIG.

  The flip-flop circuit with scan shown in FIG. 14 is a specific example in which the nMOS logic block B is composed of four nMOS transistors so as to realize the 2-input multiplexer function of FIG.

  When the signal SL1 based on the data selection signal DX1 is at a high level, the signal SL2 is at a low level, and the test selection signal SCAN is at a low level, the clock signal CK changes from low to high according to the value of the data input signal D1. The outputs Q and NQ change.

  When the signal SL1 is at the low level, the signal SL2 is at the high level, and the test selection signal SCAN is at the low level, the outputs Q and NQ are changed according to the value of the data input signal D2 when the clock signal CK transitions from low to high. Change.

  Regardless of the values of the signals SL1 and SL2, when the test selection signal SCAN is at a high level, the outputs Q and NQ change according to the value of the test input signal SI when the clock signal CK transitions from low to high. In this way, it has the function of a flip-flop with scan in which a two-input multiplexer is mounted.

  FIG. 15 shows an example in which the multiplexer configuration of the nMOS logic block B is used on the data input side of the selection circuit S1 in the input section of the conventional flip-flop with scan of FIG. In the change from FIG. 11 to FIG. 15, the inverter INV7 is deleted together with the nMOS transistors N20 and N21 of FIG. 11, and instead of these, two nMOS transistors N21 and N23 receiving two data signals D1 and D2 are provided in parallel. In order to switch the data signals D1 and D2, nMOS transistors N20 and N22 that receive signals SL1 and SL2 based on the data selection signal DX1 are connected in series to the data signals D1 and D2, respectively.

  In the change from FIG. 11 to FIG. 15, only the nMOS transistor N21 is deleted as in the change from FIG. 5 to FIG. 14, and instead of inserting the nMOS logic block B, the inverter INV7 is used. The nMOS transistor N20 to which the test selection signal SCAN is input is also replaced.

  Here, as in the case of the change from FIG. 5 to FIG. 14, the configuration by changing only the nMOS transistor N21 is also possible in FIG. 11, but in this case, five series nMOS transistors are in the current path for discharging the node X1. Will be included. Thus, when five nMOS transistors are connected in series between the node X1 and the GND, when the clock signal CK rises when the data input signals D1, D2, etc. are at the high level, the node X1 is discharged. The delay increases the possibility that the node ND1 changes from the high level to the low level before the node X1 changes from the high level to the low level, and the nMOS transistor N1 is turned off before the discharge of the node X1 ends. As a result, the node X1 becomes a high level, and the output Q originally becomes a low level when it becomes a high level, leading to a malfunction. From the above viewpoint, considering the operational stability, it is desirable that the number of nMOS transistors included in the current path for discharging the node X1 is as small as possible. As a conventional example compared with the present embodiment, the configuration of FIG. Is shown.

  When the change from FIG. 11 to FIG. 15 is performed, in the flip-flop circuit with scan shown in FIG. 15, the nMOS transistor N21 for inputting the test selection signal SCAN is deleted from the serial transistor on the data input side. When the test selection signal SCAN is at a high level and the test input signal SI is at a high level in the selection circuit, both the signals SL1 and SL2 need to be low. For this reason, the flip-flop with scan requires a circuit for setting the signals SL1 and SL2 to low when the test selection signal SCAN is at high level. As described above, when the test selection signal SCAN is at the high level, the signals SL1 and SL2 are set to low, and when the test selection signal SCAN is at the low level, the signal SL1 or SL2 is selected based on the data selection signal DX1. A selection signal generation circuit SLC0 shown in FIG. 15 is a circuit that selects a predetermined data signal to be valid from either of the data signals D1 and D2 by setting the signal to low.

In the conventional method, for example, when “!” Is a logical inversion, “+” is a logical sum, and “·” is a symbol representing a logical product, when the original data selection signal DX1 is low, the data signal D1 is selected. When the signals SL1 and SL2 are selected when the original data selection signal DX1 is high and the data signal D2 is selected and when the test selection signal SCAN is high,
SL1 =! (SCAN +! SCAN ・! DX1)
SL2 =! (SCAN +! SCAN ・ DX1)
When these are constituted by CMOS circuits, at least 16 transistors are required.

On the other hand, in the flip-flop with a multiplexer function mixed scan shown in the present embodiment, when the test selection signal SCAN is at a high level, the signals SL1 and SL2 based on the data selection signal DX1 may have any value. ,
SL1 =! DX1
SL2 = DX1
Only one inverter circuit is required, and the selection signal generation circuit (selection signal generation unit) may have a configuration with two transistors as in SLC1. Therefore, if the circuit for generating the selection signal is included, the number of circuits can be reduced as compared with the conventional method.

  As described above, according to the present embodiment, the scan flip-flop shown in the third embodiment is used as the original scan flip-flop for converting the nMOS transistor N21 for inputting data into the nMOS logic block B. By using this, it is possible to minimize the number of series transistors on the data input side, and to reduce the number of series transistors, it is possible to adopt a configuration in which a simple selection signal generation circuit SL1 can be used. Therefore, the function of the flip-flop can be increased and the circuit area of the entire chip can be simultaneously reduced.

  Although not shown in the figure, the nMOS transistor N21 in FIGS. 1, 3 and 8 in the first, second and fourth embodiments may be replaced with the nMOS logic block B as in the present embodiment. Similar effects can be obtained.

  As described above, the flip-flop with scan according to the present invention operates at high speed and can reduce the number of MOS transistors, so that the latch circuit captures data in a period of a pulse width shorter than the clock cycle. It is useful for flip-flops for high-speed applications using

It is a figure of the flip-flop circuit with a scan in the 1st Embodiment of this invention. It is a time chart figure which shows the operation | movement of the flip-flop with a scan of FIG. It is a figure of the flip-flop circuit with a scan in the 2nd Embodiment of this invention. FIG. 4 is a time chart showing the operation of the flip-flop with scan in FIG. 3. It is a figure of the flip-flop circuit with a scan in the 3rd Embodiment of this invention. It is a figure which shows another example of the flip-flop circuit with a scan in the 3rd Embodiment of this invention. FIG. 5 is a time chart showing the operation of the flip-flop with scan in FIG. 4. It is a figure of the flip-flop circuit with a scan in the 4th Embodiment of this invention. It is a figure which shows another example of the flip-flop circuit with a scan in the 4th Embodiment of this invention. It is a flowchart figure which shows the manufacturing method of the semiconductor device in the 5th Embodiment of this invention. It is a figure of the flip-flop circuit with a scan of the prior art example 1. FIG. It is a figure of the flip-flop circuit with a scan of the prior art example 2. FIG. It is a figure of the flip-flop circuit with a scan in the 6th Embodiment of this invention. It is a figure which shows the detail of the flip-flop circuit with a scan in the 6th Embodiment of this invention. It is a figure of the flip-flop circuit with a scan of the prior art example 3. FIG.

11, 12 Input unit 21, 22, 23,
24 control unit 31, 32 output unit AOI AND-OR inverter circuit B nMOS logic block CK clock signal D data signal D1, D2 data signal (predetermined data signal in the data signal group)
DX1 Data selection signal GND GND potential INV Inverter circuit N nMOS transistor ND NAND circuit NQ Inverted output signal NR NOR circuit P pMOS transistor Q Output signal S Selector circuit SCAN Test selection signal SI Test input signal SLC0, SLC1 Selection signal generation circuit (selection signal) Generator)
VDD VDD power supply X node X1 first node

Claims (10)

A plurality of nMOS transistors are provided, and first logic information including a clock signal, a data signal, a test input signal, and a test selection signal is input, and second logic information based on the first logic information is output. An input unit to
An output unit that receives at least information based on the second logical information and outputs a signal based on the second logical information;
A control unit that inputs to the input unit a control signal for generating the second logical information from the first logical information by the input unit;
A flip-flop comprising: a first node that transmits the second logic information from the input unit to the output unit;
When the clock signal transits from a low level to a high level, the input unit validates either the data signal or the test input signal among the first logic information and outputs the second logic information. A selection unit that selects whether to generate based on the test selection signal, and when the clock signal is at a low level, outputs the second logic information as a high level signal to the first node;
In the input section, the number of the nMOS transistor in which the first node is included in the path through which a current flows when a transition from the high level to the low level, is more of when the data signal is selected, the test input A flip-flop with scan, characterized in that it is less than when the signal is selected. The flip-flop with scan according to claim 1,
The input unit is first connected to the control unit via first, second and third nodes, and secondly, when the clock signal is at a low level, the input unit is connected to the first node. Third, when the data signal is at a high level, the test selection signal is output from a first state in which the test selection signal is at a low level and the clock signal is at a low level. When the input state shifts to the second state where the clock signal is at the low level and the clock signal is at the high level, if the potential of the third node is at the high level, the first node is switched to within the predetermined time. While the potential is changed from the high level to the low level and the second state is maintained, the potential of the first node is held at the low level regardless of the levels of the data signal and the test input signal. Fourth, in the case where the data signal is at a low level, when the input state shifts from the first state to the second state, the potential of the first node is set to a high level state, and the predetermined state is set. If the potentials of the second and third nodes transition from a high level to a low level after a lapse of time or longer, the second signal is maintained regardless of the levels of the data signal and the test input signal while maintaining the second state. , Holding the potential of the first node at a high level, and fifth, when the test input signal is at a high level, the test selection signal is at a high level and the clock signal is at a low level. When a transition is made from the third state to the fourth state in which the test selection signal is at a high level and the clock signal is at a high level, the potential of the second node is high. If it is Bell, the potential of the first node is changed from the high level to the low level within the predetermined time and the fourth state is maintained, and the relation is related to the level of the data signal and the test input signal. The sixth node holds the potential of the first node at a low level, and sixthly, when the test input signal is at a low level, when the state shifts from the third state to the fourth state, If the potential of the third node is at a low level, the potential of the first node is set to a high level state, and if the potential of the second node transits from a high level to a low level after the predetermined time or more has elapsed. While maintaining the fourth state, the potential of the first node is held at a high level regardless of the level of the data signal and the test input signal,
When the control unit shifts from the first state to the second state when the data signal is at a low level, the control unit sets the potentials of the second and third nodes after the predetermined time or more has elapsed. When the transition from the high level to the low level is made, and when the test input signal is at the low level, the potential of the second node is changed to the predetermined time when the third state is shifted to the fourth state. After the above, the transition from the high level to the low level is performed, the potential of the third node is kept at the low level,
The output unit outputs, as an output signal, a signal obtained by inverting the signal appearing at the first node when the clock signal is at a high level, and further, the level of the previous signal when the clock signal is at a low level. A flip-flop with a scan, characterized by holding. The flip-flop with scan according to claim 1,
The input unit is first connected to the control unit via first, second and third nodes, and secondly, when the clock signal is at a low level, the input unit is connected to the first node. Third, when the data signal is at a high level, the test selection signal is output from a first state in which the test selection signal is at a low level and the clock signal is at a low level. If the third node is at a high level when the clock signal is shifted to a second state where the clock signal is at a high level, the potential of the first node is changed from a high level to a low level. While the second state is maintained, the potential of the first node is held at a low level regardless of the state of the data signal and the test input signal, and fourth, the data signal is In the case of -level, when the transition from the first state to the second state occurs, the potential of the first node is held at a high level, and fifth, when the test input signal is at a high level. From the third state in which the test selection signal is at a high level and the clock signal is at a low level, the test selection signal is at a high level and the fourth state in which the clock signal is at a high level. When the transition is made, if the second node is at a high level, the potential of the first node is changed from a high level to a low level, and the data signal and the test are maintained while the fourth state is maintained. Regardless of the potential of the input signal, the potential of the first node is held at a low level. Sixth, when the test input signal is at a low level, the third state When a transition to the fourth state from the third node if the low level, holding the potential of said first node to a high level,
The control unit firstly, when the data signal is at a high level, the potential of the first node that transitions from a high level to a low level when transitioning from the first state to the second state. In response to the change, the potentials of the second and third nodes are held at a high level, and second, when the data signal is at a low level, the first state is shifted to the second state. When the signal of the first node maintaining the high level is received, the potentials of the second and third nodes are changed from the high level to the low level, and thirdly, the test input signal is at the high level. In the case, when the state transitions from the third state to the fourth state, the potential of the second node is held at a high level in response to a potential change of the first node that transitions from a high level to a low level. , The potential of the third node is kept at a low level, and fourth, when the test input signal is at a low level, the high level is set when the third state is shifted to the fourth state. In response to the signal of the first node to be maintained, the potential of the second node is changed from a high level to a low level, and the potential of the third node is kept at a low level.
The output unit outputs, as an output signal, a signal obtained by inverting the signal appearing at the first node when the clock signal is at a high level, and further, the level of the previous signal when the clock signal is at a low level. A flip-flop with a scan, characterized by holding. The flip-flop with scan according to claim 1,
The input unit and the control unit are connected via first, second and third nodes,
The control unit and the output unit are connected via fourth and fifth nodes,
In addition, the input unit firstly outputs a high level to the first node when the clock signal is at a low level, and secondly, the test selection is performed when the data signal is at a high level. When a transition is made from the first state where the signal is low level and the clock signal is low level to the second state where the test selection signal is low level and the clock signal is high level, If the third node is at a high level, the potential of the data signal and the test input signal is maintained while the potential of the first node is changed from a high level to a low level and the second state is maintained. Regardless of whether the potential of the first node is held at a low level, and thirdly, when the data signal is at a low level, the first state is shifted to the second state. When the test input signal is at the high level, the test selection signal is at the high level and the clock signal is at the low level. If the second node is at a high level when the test selection signal is at a high level and the clock signal is at a high level from the third state, the second node is at a high level. While the potential of the first node is changed from the high level to the low level and the fourth state is maintained, the potential of the first node is set to the low level regardless of the potential of the data signal and the test input signal. Fifth, when the test input signal is at a low level, when the third state shifts to the fourth state, the third node becomes low level. If, holding the potential of said first node to a high level,
The control unit firstly, the signal of the first node that transitions from a high level to a low level when transitioning from the first state to the second state when the data signal is at a high level. In response, the potentials of the second and third nodes are held at a high level, the potential of the fourth node is held at a high level, and the potential of the fifth node is changed from a low level to a high level. And secondly, when the data signal is at a low level, when the transition from the first state to the second state is received, the signal of the first node maintaining the high level is received, and The potential of the second and third nodes is changed from high level to low level, the potential of the fourth node is changed from high level to low level, and the potential of the fifth node is maintained at low level. Thirdly, when the test input signal is at the high level, the signal of the first node that changes from the high level to the low level is received when the third state is shifted to the fourth state. The potential of the second node is held at a high level, the potential of the third node is kept at a low level, the potential of the fourth node is held at a high level, and the fifth node The potential of the node is changed from the low level to the high level. Fourth, when the test input signal is at the low level, the high level is maintained when the third state is shifted to the fourth state. The signal of the first node is received, the potential of the second node is changed from a high level to a low level, the potential of the third node is kept at a low level, and the second node The signal of the node to transition from a high level to a low level, holding the potential of the fifth node to the low level,
The output unit first outputs a high level output signal and a low level inverted output signal when receiving a high level signal from the fourth and fifth nodes, and secondly, the second level When a low level signal is received from the fourth and fifth nodes, a low level output signal and a high level inverted output signal are output, and thirdly, the high level is output to the fourth node. A flip-flop with scan, characterized in that when a low level signal is received at a node, the levels of the output signal and the inverted output signal are held at the previous level. The flip-flop with scan according to claim 1 ,
The number of nMOS transistors when the data signal is selected is three,
4. The flip-flop with scan, wherein the number of nMOS transistors when the test input signal is selected is four. The flip-flop with scan according to claim 1 ,
The number of nMOS transistors when the data signal is selected is two,
The flip-flop with scan, wherein the number of nMOS transistors when the test input signal is selected is three. In the flip-flop with a scan according to claim 2 or 3 ,
The control unit firstly, when the data signal is at a high level, the potential of the first node that transitions from a high level to a low level when transitioning from the first state to the second state. In response to the change, a high level signal is output to the fifth node, and secondly, when the data signal is at a low level, when the state shifts from the first state to the second state, In response to the signal of the first node maintaining the high level, a low level signal is output to the fifth node, and third, when the test input signal is at the high level, the third node When the state shifts from the state to the fourth state, in response to the potential change of the first node transitioning from the high level to the low level, a high level signal is output to the fifth node, and the fourth The test In the case where the power signal is at the low level, when the state shifts from the third state to the fourth state, the signal of the first node that maintains the high level is received and the low level signal is changed to the fifth level. A fifth node that outputs to the node, and fifthly, an inverted signal of the fourth node is propagated therein, and the sixth node is interposed between the sixth node and the second node. And an inverter circuit for propagating an inverted signal of the node 6 to the second node, and further, the signal of the sixth node and the test selection signal are input, and the result of the NOR logic operation is input to the third node. A flip-flop with scan, comprising: a 2-input NOR circuit that outputs to a node of The flip-flop with scan according to claim 7 ,
The two-input NOR circuit comprises a series connection of a series circuit of two pMOS transistors, one of which is connected to the power supply potential, and a parallel circuit of two nMOS transistors connected to the ground potential.
The inverter circuit is a CMOS inverter,
A flip-flop with a scan, wherein one pMOS transistor connected to a power supply potential of the two-input NOR circuit and the pMOS transistor of the CMOS transistor are shared as one pMOS transistor. The flip-flop with scan according to any one of claims 1 to 8 ,
A data signal generation circuit for generating the data signal to be input to the flip-flop with scan,
The semiconductor device, wherein the data signal generation circuit is arranged adjacent to the flip-flop with scan. A first step of arranging the flip-flop with scan according to any one of claims 1 to 9 ,
A second step of arranging a data signal generation circuit for generating a data signal of the flip-flop with scan adjacent to the flip-flop with scan;
A third step of arranging a circuit other than the data signal generation circuit;
And a fourth step of preferentially wiring the data signal of the flip-flop with scan. A method for manufacturing a semiconductor device, comprising:

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