JPH0468816A - Clock phase adjusting circuit - Google Patents

Abstract

PURPOSE:To accurately and easily adjust a clock phase by respectively selecting AND gates increasing the input numbers by a control signal. CONSTITUTION:When a control signal 42 is changed from an L level to an H level among control signals 42-48 and the other control signal 43-48 are turned to a state at the L level, the output of an AND gate 35 is at the L level in the case of setting a clock 49 at the H level, the outputs of other AND gates 36-41 are at the L level, and an output from an AND gate 52 is at the H level. When the clock 49 is turned to the L level, the output of the AND gate 35 is turned to the H level, and the output of the AND gate 52 is turned to the L level. Similarly when the control signal 43 is turned to the H level and the other control signals 42 and 44-48 are turned to a state at the L level, the AND gate 36 is selected. Similarly by changing the control signals 44-48, the AND gates 37-41 are selected.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a clock phase adjustment circuit using a DCFL circuit, and aims to provide a clock phase adjustment circuit that can accurately and easily adjust the clock phase. It is composed of an AND gate to which a signal is input, a plurality of AND gates to which a clock, a control signal, and a fixed signal that increases sequentially are input, and an AND gate to which the output of each of the AND gates is input.

[Industrial Application Field] The present invention relates to a clock phase adjustment circuit using a DCFL circuit.

As a method for operating a computer system such as a computer, there is a method of transmitting a clock to each circuit and operating them in synchronization.

However, when transmitting the clock, it is necessary to adjust the clock phase due to variations in LSI manufacturing.

Therefore, it is necessary to accurately and easily adjust the lock phase.

[Prior Art] Conventional methods of adjusting the clock phase include, for example, a method using the length of a wire as shown in FIG. 7, and a method of creating a delay using a circuit as shown in FIG. and so on.

In FIG. 7, 1 is an oscillator, and a plurality of inverters 2 to 8 are connected to the oscillator 1, respectively. In this circuit, the clock phase is adjusted by changing the lengths of wire 9 connected between inverter 3 and inverter 4 and wire 10 connected between inverter 6 and inverter 7.

Further, in FIG. 8, 11 is an AND gate into which the clock 12 and the control signal 13 are input, and 14 is an AND gate into which the output of the AND gate 11 and the control signal 19 are input. Further, the control signals 20 to 23 and the output of the AND gate on the upper side in the figure are sequentially input to the AND gates 15 to 18. The outputs of the AND gates 11, 14 to 18 are input to the AND gate 24.

Therefore, by selecting one of AND gates 11.14-18 using control signals 13.19-23, a delay is created depending on the number of gates, and the clock phase is adjusted.

[Problem to be Solved by the Invention] However, in the former case, in the conventional clock phase adjustment circuit, the length of the wire must be changed, so it is difficult to adjust the phase with many blacks. The problem was that it could not be done easily.

Further, in the latter case, the delay time of one gate is, for example, 100 PS, and there is a problem that the clock phase cannot be adjusted with high precision.

The present invention has been made in view of such conventional problems, and an object of the present invention is to provide a clock phase adjustment circuit that can accurately and easily adjust the clock phase.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

In FIG. 1, 35 is an AND gate to which the clock 49 and the control signal 42 are input, 36 and 37 are a plurality of AND gates to which the clock 49, control signals 43 and 44, and a fixed signal 51 which increases sequentially are input, and 52 is each of the above. This is an AND gate into which the outputs of AND gates 35 to 37 are input.

[Operation] It is known that in a DCFL circuit, increasing the number of inputs increases the delay time.

Generally, when the number of inputs increases by one, the gate 1 becomes like this, and a clock phase adjustment circuit is constructed using the characteristics of the CFL circuit.

In this clock phase adjustment circuit, by selecting each AND gate whose number of inputs is increased by a control signal, the clock phase can be adjusted accurately and easily.

[Example] Embodiments of the present invention will be described below based on the drawings.

An embodiment of the present invention is shown in FIGS. 2 to 6.

Figure 3 shows D CF L (Direct Couple
dFET Logic) circuit.

In FIG. 3, 31 is a depletion type transistor, and this depletion type transistor 31 has a gate G
1 has a drain D and a source S. 32 is an enhancement type transistor, and this enhancement type transistor 32 also has a gate G1, a drain D, and a source S. The depletion type transistor 31 and the enhancement type transistor 32 are directly coupled, as shown in FIG.
It constitutes an AND gate 33.

When a pulse signal A is input from the gate G of the enhanced transistor 31, an output of A is obtained after one hour. It is known that in such a CFL circuit, the time increases by one hour each time the number of inputs increases.

FIG. 6 shows an example in which the number of inputs is increased by one. In FIG. 6, when another input B (control signal) is increased with respect to pulse input A, A+B is obtained as an output. The AND gate 34 in this case is shown in FIG.

The time from input (A+B) to output (A+B) is T(1+i to 1+3), which is longer than when done by one person.

FIG. 2 shows a clock phase adjustment circuit constructed using the characteristic of the DCFL circuit that the delay time increases as the number of inputs increases.

In FIG. 2, 35 is an AND gate into which the clock 49 and the control signal 42 are input, and 36 is the L signal from the clock 49, the control signal 43, and the Nant gate 50.
An AND gate to which a level fixed signal 51 is input, 37 an AND gate to which a clock 49, a control signal 44 and two fixed signals 51 are input, and 38 an AND gate to which a clock 49, a control signal 45 and three fixed signals 51 are input. , 39 are the clock 49 and the control signal 4
6 and four fixed signals 51 are input, and gate 40
41 is an AND gate to which the clock 49, control signal 47, and five fixed signals 51 are input, and 41 is an AND gate to which the clock 49, control signal 48, and six fixed signals 51 are input.

Reference numeral 52 denotes an AND gate into which the outputs of the AND gates 35 to 41 are inverted and input, and a clock 53 is output from the AND gate 52.

Each control signal 42 to 48 is latched by a latch 55 according to an instruction from the MPU 54, and then decoded by a decoder 56 and output.

Therefore, for example, if the control signal 42 of the control signals 42 to 48 is changed from the L level to the H level and the other control signals 43 to 48 are set to the L level, when the clock 49 is at the H level, the AND gate 35 Output is L level, other AND gates 36 to 41
The output from the AND gate 52 is at the L level, and the output from the AND gate 52 is at the H level.
When the clock 49 becomes L level, the output of AND gate 52 becomes H level.
The output becomes L level. Similarly, control signal 43
is set to H level, and other control signals 42.44 to 4
8 is set to the L level, the AND gate 36 is selected. Similarly, AND gates 37-41 are selected by changing control signals 44-48.

Therefore, if the AND gate 38 is set to transmit a predetermined clock in the initial state, when the AND gate 37°36.35 is selected during phase adjustment, the clock will be adjusted to be faster, and Selecting gates 39, 40, 41 adjusts the clock to be slow.

In this embodiment, the delay time of one AND gate is 50 PS, compared to the conventional 100 PS.
Adjustments can be made with high precision.

Furthermore, since it is only necessary to increase the number of inputs, the clock phase can be easily adjusted.

[Effects of the Invention] In the present invention, the clock phase adjustment circuit is configured using a DCFL circuit, which increases the delay time as the number of inputs increases. Therefore, the clock phase can be adjusted accurately and easily. can be done.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a diagram showing an embodiment of the present invention, Fig. 3 is a diagram showing a DCFL circuit operated by one person, and Fig. 4 is a diagram showing an AND gate operated by one person. , Figure 5 shows a two-person DCFL.
6 is a diagram showing a two-man powered AND gate, FIG. 7 is a diagram showing a conventional example, and FIG. 8 is a diagram showing another conventional example. In the figure, 35-41.52...and gate, 42-48...
- Control signal, 49... Input clock, 50... Nantes gate, 51... Fixed signal, 53... Output clock, 54... MPU. 55...Latch, 56...Decoder.

Claims (1)

[Claims] An AND gate (35) to which the clock (49) and control signal (42) are input, and a fixed signal (5) which sequentially increases the clock (49) and control signal (43-44).
1) multiple AND gates (36), (37) input
and an AND gate (52) into which the outputs of the AND gates (35 to 37) are input.