JPS6042624B2 - Field effect switching element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a field effect switching device, and more particularly to a device having an improved structure with a high switching speed.

A field effect switching element has an opposite conductivity type gate formed in one conductivity type layer of a semiconductor substrate having a diode function, and a pair of electrodes (anode electrode and force sorting electrode) formed at both poles of the diode and the gate. This device has a gate electrode connected to the gate electrode.

FIG. 1 or 2 shows a typical example of a conventional field effect switching element. In Figure 1 or Figure 2,
The semiconductor substrate 1 includes a P+ type anode 11, an n1 type base formed adjacent to the anode 11, an n+ type cathode 13 formed adjacent to the base 12, and a base 122.
A gate 1 formed within the anode, a cathode, and an anode electrode 2 formed respectively on the exposed portions of the gate.
, a cathode electrode 3 and a gate electrode 4. This device turns on when the gate electrode is opened or kept at the same potential as the cathode electrode, and a voltage is applied between the anode and cathode electrodes to forward bias the diode, which is composed of a p+ anode, an n-base, and an n+ cathode. A diode forward current (O7 current) flows between the anode and cathode electrodes through the channel 15.

Furthermore, by applying a voltage between the cathode and gate electrodes so that the Pn junction between the cathode and the gate is reverse biased, a depletion layer is formed in the base layer, and this depletion layer pinches off the channel 15. It has the function of turning off the on-state current by quickly cutting off the on-state current. When transitioning from the on state to the off state (turn-off), the anode current that had been injected from the anode flows to the gate, and subsequently a depletion layer is formed at the Pn junction between the gate and the base.

Since the base has a lower concentration than the gate, the depletion layer is mainly formed in the base, and when the depletion layer completely blocks the channel 15, the on-current is cut off. Field-effect switching elements have better high-temperature characteristics than conventional Pnpn structure thyristors, do not cause current concentration during turn-off operation, are capable of high-speed switching operation, and have a large critical voltage rise rate. The device has the following characteristics.

However, conventional field effect switching elements have the following drawbacks. That is, in the device shown in FIG. 1, since the lateral resistance of the gate 14 formed in a grid shape is relatively large, a sufficient anode current cannot be drawn from the gate when the gate is turned, and a large current is cut off. It is difficult to do so. Even if it could be turned off, the time required to shift to the turn-off state, that is, the turn-off time, would be long, and high-speed switching would not be possible. In addition, in the device shown in FIG. 2, the lateral resistance of the gate 14 is smaller than that shown in FIG. 1, and it is possible to cut off a large current. It is difficult to narrow the width, and the gate-cathode voltage required to prevent a constant anode-cathode voltage becomes larger. Regarding the shearing characteristics, the large spacing between the gate regions is disadvantageous for shedding large currents, and as a result, the turn-off time cannot be shortened. The conventional structure shown in the figure has the above-mentioned drawbacks. A fundamental factor that increases the turn-off time is the influence of residual carriers accumulated in the base 12.

For example, when the device shown in FIG. 2 is turned off and on-current flows, holes are injected into the base 12 from the anode 11 and electrons are injected from the cathode 13. Then, the base 12 is filled with carriers, and the electrical conductivity here increases and the on-resistance during conduction decreases.Next, when a load pressure is applied to the gate electrode with respect to the cathode electrode, the current from the anode increases. At the same time, the minority carriers near the gate are drawn into the gate, and the carriers accumulated at the base are drawn out. The closer the carrier is to the gate, the more likely it is to be drawn out to the gate, while the further away the carrier is, the more difficult it is to be drawn out. That is, since it takes time for the minority carriers near the anode to flow into the gate, the anode current continues to flow even after the gate voltage is applied, which causes the turn-off time to increase. The thicker the base, the more carriers in the base accumulate, resulting in a longer turn-off. In order to reduce turn-off, a method can be used to reduce the carrier lifetime by diffusing a heavy metal such as gold into the base.

However, in an attempt to further reduce the turn-off time, a large amount of gold is diffused and the lifetime is reduced, which increases the on-voltage and increases heat loss in the on-state.
The drawback was that the leakage current in the off-state increased, resulting in poor high-temperature characteristics.

SUMMARY OF THE INVENTION An object of the present invention is to improve such drawbacks of conventional field effect switching elements and to provide a field effect switching element suitable for high frequency operation with a short turn-off time. In order to achieve this object, the present invention is characterized in that in a field effect switching element, an anode of one conductivity type is adjacent to the base of the other conductivity type and forms a Pn junction between the base and the base. The point is that a single crystal layer of the other conductivity type is used, which is generated by diffusion of an impurity imparting the other conductivity type into the base from a semiconductor polycrystalline layer of the other conductivity type formed adjacent to the semiconductor polycrystalline layer of the other conductivity type.

For example, if a p-type polycrystalline layer is formed on an n-type single crystal substrate, p
The p-type impurity in the type polycrystalline layer slightly diffuses into the n-type single-crystalline substrate, and the part of the n-type single-crystalline substrate in contact with the p-type polycrystalline layer is converted into a thin p-type single-crystalline layer, and the p-type A Pn junction is formed between the single crystal layer and the n-type single crystal substrate.

If the p-type single-crystal layer is formed by diffusion of impurities from the p-type polycrystalline layer in this way, the p-type single-crystal layer will be thin and the amount of impurities will be reduced, so carriers can be injected from the p-type single-crystal layer. For example, Japanese Patent Application Laid-Open No. 52-417,
It is disclosed in Japanese Patent Publication No. 52-90273. The present invention provides an improved field-effect switching device that achieves the above object by applying the above-described principle to the field-effect switching device. More specifically, a major reason for the long turn-off time of field effect switching elements is that residual carriers in the base flow into the gate even after the channel is pinched off by the depletion layer.

The carriers flowing into the gate become gate current, and approximately the same current also flows to the anode. The duration of this gate current (ie anode current) is very long compared to the time required to pinch off the channel. The present invention suppresses the current caused by the above-mentioned residual carriers by reducing the number of minority carriers injected from the anode to the base, thereby shortening the turn-off time. Examples of the present invention will be described below. FIG. 3 shows a device according to a first embodiment of the present invention, and the same parts as in FIG. 1 are designated by the same reference numerals.

In this embodiment, as the anode 11, a p-type single crystal silicon layer is used which is diffused into the n-type base 12 using the p-type polycrystalline silicon layer 16 as a diffusion source. The anode 11 is thin (approximately 0.0 mm) in order to keep the carrier injection efficiency low.
However, since the thick polycrystalline silicon layer 16 is interposed between the anode 11 and the anode electrode 2, the thin anode 11 is not destroyed by forming the anode electrode 2. According to the device of this example, the turn-off time was shorter than that of the conventional example shown in FIG.

FIG. 4 shows a device according to a second embodiment of the present invention, in which the same parts as in FIG. 2 are designated by the same reference numerals.

In this embodiment, a p-type single crystal silicon layer is used as the anode 11, which is diffused into an n-type base 12 using a p-type polycrystalline silicon layer 16 as a diffusion source. Anode 11
is kept thin (approximately 0) to keep the carrier injection efficiency low.
．． However, since the thick polycrystalline silicon layer 16 is interposed between the anode and the anode electrode 2, the thin anode 11 is not destroyed by forming the anode electrode 2. According to the device of this example, the turn-off time was shorter than that of the conventional example shown in FIG. FIG. 5 shows a third embodiment of the invention.

In the figure, a semiconductor substrate 1 includes an n-type base 52 and a p-type polycrystalline silicon layer 7 formed on one main surface of the base.
, a p-type anode 51 diffused into the base 51 using the polycrystalline silicon layer 7 as a diffusion source, a type-resistant cathode 53 formed at regular intervals inside the base in contact with the other main surface of the base, and the other main surface of the base. Regions 542 and 5 are formed alternately with the cathode 53 at regular intervals inside the base in contact with the main surface of the base, and extend perpendicularly thereto from the other main surface of the base.
42 and a region 541 extending towards the cathode 53 leaving channels 15 spaced apart from each other. polycrystalline silicon layer 7,
An anode electrode 2, a cathode electrode 3, and a gate electrode 4 are formed on the exposed surfaces of the cathode 53 and gate 547, respectively. In this embodiment, the gate 54 has a wide cathode portion and a narrow channel 15 width. This gate structure has the feature that the channel width can be made narrow without being restricted by the width of the cathode 53, and since the internal resistance of the gate is small, a large current can be easily cut off with a low gate voltage. In addition, the region where the gate region 541 extending horizontally in the base overlaps the cathode 53 in the vertical direction has a so-called thyristor structure with a Pn-Pnn+ structure in the vertical direction, and acts as a thyristor in the on state, so that the channel width can be narrowed. This has the advantage that the current-carrying area during conduction does not become narrower even when conducting. FIG. 6 shows a fourth embodiment of the present invention. The difference from the first embodiment is that an n layer 8 having a higher impurity concentration than the base is inserted between the base and the anode 11, and the n layer is made thinner. The n-layer 8 has the following effects. When applying a negative voltage with respect to the cathode 13 to the gate 14 of the field effect switching element and applying a positive voltage with respect to the cathode to the anode, if the gate voltage is large enough, the channel 15
The depletion layer expands from the gate, creating a pinch-off state and cutting off the current path between the anode and cathode. When the anode voltage is increased, the depletion layer extends from the gate layer toward the anode. If the base is not thick enough, the depletion layer will not reach the anode. However, making the base thicker increases the amount of accumulated carriers and increases the on-voltage as mentioned above, which is not desirable. However, if the n-layer 8 is inserted as shown in Figure 6, and the impurity concentration of the n-layer 8 is made higher than the base, and the impurity concentration of the base is made sufficiently low, the depletion layer extending from the gate will reach the n-layer 8, but no further. can prevent the depletion layer from expanding. Therefore, even if the base is made thinner, there is no problem of the depletion layer reaching the anode and punching through. As a result, a field effect switching element with a small O7 voltage and a short turn-off time can be easily manufactured. Furthermore, the gate voltage required to block the anode voltage is low when the electric field across the channel 15 is low. It is known that it can be kept as low as possible. In the structure shown in FIG. 6, the impurity concentration in the base can be made sufficiently low, so that the electric field in the channel portion can be made low. That is, it has the advantage that even if the gate voltage is lowered, a high anode voltage can be prevented. FIG. 7 shows a fifth embodiment of the present invention.

The differences from the second embodiment are similar to the differences between the fourth embodiment and the first embodiment. As mentioned earlier, this structure is advantageous in cutting off large currents, and has the advantage that the manufacturing method of the gate structure is simple4, as well as the above-mentioned n
This is a field effect switching element that has the feature of layer 8.

FIG. 8 shows a sixth embodiment of the present invention.

The differences from the third embodiment are similar to the differences between the fourth embodiment and the first embodiment. In such a structure, the effect of forming the anode by diffusion from p-type polycrystalline silicon is well exhibited.

Next, the manufacturing process of the embodiment shown in FIG. 8 of the present invention will be briefly explained based on FIG. 9.

First, an n-silicon substrate 1 is prepared as shown in FIG. 9a.

The resistivity is chosen to be 200Ω-α, for example. Next, as shown in b, a p-type diffusion layer 5 is formed from one surface by selective diffusion method.
41 are formed at regular intervals. This includes SlO. A method of diffusing boron using a film as a mask may be used. Subsequently, as shown in c, an n-type epitaxial growth layer 55 is formed on the surface side on which the p-type selective diffusion layer 541 is formed. Generally, the impurity concentration of this n-type layer 14 is set higher than that of the n-type layer 52,
During epitaxial growth, the resistivity of the channel portion 15 is prevented from changing due to autodoping from the p-type diffusion layer. For example, adjust the doping gas amount so that the resistance becomes 25Ω-0. Next, boron is selectively diffused from the surface to form a p-type coupling diffusion layer 542 that reaches the p-type buried diffusion layer 541.Similarly, Alternatively, after this step, phosphorus is diffused from the back surface of the substrate 1 to form an n-type layer 8.The impurity concentration of this layer is high to a certain extent so that the depletion layer does not extend to p-type polycrystalline silicon, which will be described later. It is selected so that the injection efficiency of holes from p-type polycrystalline silicon is not too low.For example, the average impurity concentration is 1 x 1016at.
Diffusion conditions are set so that it becomes 0 ms/CTfl. Next, as shown in e, a cathode emitter layer 53 is formed by a method such as selective diffusion of phosphorus. Subsequently, a p-type polycrystalline layer 7 is deposited on the n-type diffusion layer on the back surface, and an extremely thin p-type diffusion layer 51 is formed in the n-type diffusion layer 8 using this p-type polycrystalline layer as a diffusion source. Thickness 0.05μm to 1μm
When the thickness is approximately m, a p emitter layer with low hole injection efficiency is formed. The thin diffusion layer may be formed during the heat treatment for polycrystal growth, or may be formed by reheating after growth.
Polycrystalline silicon can be formed, for example, by heating trichlorosilane as a silicon raw material and diborane as a doping gas to 800 to 10,000 C in hydrogen. It is desirable that the thickness be sufficiently thick so that the bond between the anode and the base is not damaged due to the formation of the electrode on the anode side. For example, it is formed to have a thickness of 30 to 60 pm. Finally, the anode electrode 2, cathode electrode 3, and gate electrode 4 are attached to complete the device. As described above, by using polycrystalline silicon or silicon as the diffusion source for the anode layer and using an extremely thin p-type diffusion layer as the anode, a field effect switching element with a short return-off time can be obtained.

When an extremely thin p-type diffusion layer diffused from a polycrystalline silicon layer is used as an anode, the phenomenon that this anode has low injection efficiency and reduces accumulated carriers in the base, shortens the turn-off time of the device, is as follows. It is explained as follows.

The hole injection efficiency of an extremely thin p-type anode layer is approximately expressed by the following equation. Here, it is assumed that the carrier diffusion length in the base and n-layer 8 is sufficiently larger than the total thickness of the two layers, and that the cathode has a sufficiently high electron injection efficiency.

τ2: Lifetime of holes in the base and n-layer W: Total thickness of the base and n-layer Dn: Electron diffusion coefficient in the base and n-layer D″n: Diffusion coefficient of electrons in the p-type anode j: Current density q: Elementary quantity of electrons Q: Amount of p-type impurity per unit area in the p-type anode Since the conventional p-type anode layer is sufficiently thick, Q is very large, and the first term in equation (1) can be ignored. .

However, if an extremely thin p-type anode layer is used as in the structure of the present invention, Q can be made small, so the injection efficiency τ2 becomes small. In the third and sixth embodiments described above, when the cathode region and the flat portion 541 of the gate region are projected onto the main surface of the semiconductor substrate, the overlapping area (S1) is calculated from the projected area of the cathode region. It is preferable that the area (S2) excluding the portion be 30% or more.

In the third and sixth embodiments, the inventor has provided a flat portion 54.
The distance between one end is constant at 30 pm, and the ratio of S1 and S2 (
For many elements with different S1/S2), the current density is 1
The forward voltage drop characteristics of the device with 20 A/CTl were investigated. The results are shown in FIG. According to the figure, S1/
When the value of S2 is approximately 0.3, the value of S1/
The forward voltage drop value, which was approximately 1.35 cm at S2, decreases as S1/S2 increases. This trend shows that the current density is 120A/c! This also applies even if the distance between the ends of the flat portion 541 is other than 30 μm. Therefore, in the third and fourth embodiments of the present invention, setting S1 to 30% or more of S2 is effective in reducing the forward voltage drop value of the element.

It goes without saying that the effects of the present invention can also be obtained by replacing the conductivity type p (5n) in each of the above-mentioned embodiments.

Next, how much the return off time can be reduced by the present invention will be explained using specific numerical values.

For comparison with the third embodiment shown in FIG. 5, a device was fabricated in which the p-type anode 51 and the p-type polycrystalline silicon layer 7 were changed to the anode 11 as shown in FIG. 1.

The semiconductor substrate 1 is a square of 6.3Tn×6.3Tsn,
Seventy-four cathodes 53 each having a thickness of 4 μm, a width of 50 pm, and a length of 1200 pm are arranged with their longitudinal directions aligned. And the surface impurity concentration of the cathode 53 is 1X1019at0m
s/Cll.

The region 541 has a thickness of 40 μm and a surface impurity concentration of 5×10
7at0ms/C7l, channel 15 is cathode 5
The cathode 53 is located directly below the center of the cathode 53 and has a width of 7 μm along the longitudinal direction of the cathode 53 . Base 52 has a specific resistance of 50Ω
One cup, thickness 140μM. ．． The p-type anode 51 has a thickness of 0.
5μm1 surface impurity concentration is 1×1015at0ms/C
Tl. ．． The p-type polycrystalline silicon layer 7 has a thickness of 50 pm. On the other hand, the anode 11 of the comparative example element has a thickness of 40 μm.
The m1 surface impurity concentration was 1×10 19 at0 ms/Cm, and the other dimensions were the same as the above dimensions.

The turn-off time when the load current of 20 A was interrupted was 4 μS for the device of the present invention and 15 μs for the comparative example device. As described above in detail, the present invention is effective in obtaining a field effect switching element with a short turn-off time.

[Brief explanation of the drawing]

1 and 2 are views showing a conventional example of the present invention, FIG. 3 is a first example of the present invention, FIG. 4 is a second example, and FIG. 5 is a third example of the present invention.
Fig. 6 is a diagram showing the fourth embodiment, Fig. 7 is a fifth embodiment, and Fig. 8 is a diagram showing the sixth embodiment, respectively. Fig. 9 is a diagram for explaining the manufacturing process of the embodiment shown in Fig. 8. , FIG. 10 is a diagram showing the relationship between S1/S2 and forward voltage drop value in the embodiment shown in FIG. 5 or FIG. 8. 11,51...Anode, 12,52...
・Base, 13,53...Cathode, 14,5
4...Gate, 2...Anode electrode, 3
...Cathode electrode, 4...Gate electrode.

Claims (1)

[Scope of Claims] 1. A semiconductor single crystal substrate of one conductivity type having a pair of main surfaces, and a first semiconductor single crystal substrate of one conductivity type formed inside the substrate in contact with one main surface of the substrate and having an impurity concentration higher than that of the substrate. between the semiconductor region of the substrate, the semiconductor polycrystalline layer of the other conductivity type formed on the other main surface of the substrate, and the substrate caused by diffusion of impurities that determine the conductivity type of this polycrystalline layer into the substrate. a semiconductor layer of the other conductivity type that is extremely thinner than the semiconductor polycrystalline layer forming a pn junction therein; and a pair of main electrodes formed on the exposed surfaces of the first semiconductor region and the semiconductor polycrystalline layer, respectively. , formed inside the substrate and comprising a first semiconductor region of one conductivity type, a semiconductor single crystal substrate of one conductivity type, a semiconductor layer of the other conductivity type, a semiconductor polycrystalline laminate of the other conductivity type, and a pair of main electrodes. a second semiconductor region of the other conductivity type which has the function of pinching off the forward current of the diode formed in the semiconductor single crystal substrate; A field-effect switching element comprising: a control electrode that causes the pinch-off by applying a predetermined voltage between the electrode and the control electrode. 2. In claim 1, the first semiconductor region is formed intermittently in contact with one main surface, and the second semiconductor region is formed in contact with one main surface and alternately with the first semiconductor region. a first portion that is formed and is formed deeper than the first semiconductor region from one main surface to the other main surface;
From the bottom of this first part, parallel to one main surface, a first
and a second portion that extends until a portion of the semiconductor region overlaps the projected portion when projected onto the other main surface.