JPH0982986A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a leakage current while improving on-state voltage and the trade-off of switching loss. SOLUTION: A high-concentration n-type semiconductor substrate is used as an n<+> buffer layer 2, an n<-> layer 1 is formed on the surface of the buffer layer 2, a p<-> layer 5 is shaped onto the surface layer of the n<-> layer 1, trench grooves 10 reaching the n<-> layer 1 are formed to the surface of the layer 5, boron is diffused to the side walls and bases of the trench grooves 10 in a vapor phase, p<+> regions 6 are formed, and a surface electrode 3 is formed onto the p<+> layers 5 and the p<+> regions 6 and a rear electrode 4 onto the n<+> buffer layer 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a diode used in a power conversion device.

[0002]

2. Description of the Related Art A diode used in a power converter is required to have a low on-voltage and high speed. In a low withstand voltage element of several tens of volts, a Schottky diode has this characteristic as well. However, when the withstand voltage is increased, the on-voltage (also called forward voltage drop) is greatly increased due to the increase in silicon thickness, and the Schottky junction Therefore, the leakage current is significantly increased. Therefore, the Schottky diode is not generally used as a high breakdown voltage element. As a high breakdown voltage element, conductivity modulation (reducing the conductivity of a semiconductor by injecting holes and electrons) is used to reduce the on-voltage.
N-diodes (pn ^- n ⁺ in structure) are well known.

FIG. 8 shows a pin diode (conventional example (1)).
A state in which a voltage is applied is shown in the element cross-sectional view of FIG.
Shows the diagram when forward biased, and (b) shows the diagram when reverse biased.
Show. This pin diode has ap layer 8, n^-Layer 1, n⁺
The buffer layer 2 is composed of three layers, on the p layer 8 and the n layer.⁺Buff
A front surface electrode 3 and a back surface electrode 4 are formed on the upper layer 2. Same figure
In (a), forward bias the pin diode
From the p layer 8 to holes, n ⁺Electrons from the buffer layer 2^-
It is injected into the layer 1 and the current indicated by the arrow flows. This on
N in the state^-In layer 1, carriers in thermal equilibrium (with holes and
More than the amount of electrons), so-called conductivity modulation occurs,
Lower the on-voltage. But accumulated in the on state
Due to the large amount of carrier, a large reverse recovery voltage is generated during the reverse recovery process.
The flow flows. In order to suppress this
A lifetime killer is introduced in the ode. Only
However, the introduction of lifetime killer increases the on-voltage.
You. In this way, in the pin diode,
There is a trade-off between recovery current and
Since the switching loss depends on the reverse recovery current, the on-voltage and the switching
The ching loss also has a trade-off relationship. In the figure (b)
When the pin diode is reverse biased,^-layer
The depletion layer spreads to 1. Depletion layer edge is n⁺Reach buffer layer 2
Then the depletion layer is n⁺Hardly spreads in the buffer layer 2
Therefore, n⁺By providing the buffer layer 2, n^-Layer 1 thickness
This helps reduce the on-voltage. Also, p layer
Since the concentration of 8 is relatively high, the expansion of the depletion layer in the p-layer 8
Is small.

In order to improve the trade-off between the ON voltage and the switching loss, the p-layer 8 of the pin diode is used.
Concentration reduce the positive hole the n ^- suppressed from being injected into the layer 1, by reducing the degree of conductivity modulation, p layer 8 and the n ^-
The carrier concentration near the pn junction, which is the junction of the layer 1, is reduced. In addition, by not introducing the lifetime killer positively, the lifetime of the carrier is kept long and the on-voltage is not increased. By establishing both of these, the p ^- in diode is designed to reduce the reverse recovery current without increasing the on-voltage and to realize soft recovery (the reverse recovery current smoothly decreases) and low switching loss. Is being developed.

[0005]

However, this p ^- in
In the diode, the depletion layer spreads to the p ⁻ layer at the time of reverse bias, and the depletion layer reaches the surface electrode, so that the high breakdown voltage is limited by the so-called punch-through phenomenon. In order to improve this, a p ^- in diode provided with a p ⁺ well 9 has been developed.

FIG. 9 shows a state in which a voltage is applied to a device cross-sectional view of a p ^- in diode (conventional example (2)) provided with a p ⁺ well 9, and FIG. 9 (a) is a diagram at the time of forward bias, Figure (b) shows a diagram at the time of reverse bias. In this p ^- in diode, a layer corresponding to the p-layer 8 of the pin diode in FIG. 8 is formed by a p ^- layer 5 and an island-shaped p ⁺ well 9. The structure in which a p ⁺ well 9, is at the time of the forward bias as shown in FIG. (a) p ^- holes from the layer 5, n ⁺ electron from the buffer layer 2 is injected, the current p ^- n ⁺ buffer from layer 5 Flows towards layer 2. At this time, the p-well voltage of the pn junction in the p ⁺ well 9 and the n ⁻ layer 1 (voltage at which current starts flowing) is larger than the pir junction voltage of the pn junction in the p ⁻ layer 5 and the n ⁻ layer 1, so that p ^{+ There} is no injection of holes from the well 9. The current also flows laterally under the p ⁺ well 9, and when the voltage determined by the product of the lateral resistance and the current becomes larger than the engraved layer voltage,
Injection of holes also occurs from the p ⁺ well 9. Since the lateral resistance is large in this structure, holes are also injected from the p ⁺ well 9 with a relatively small current, resulting in a large switching loss. Further, as shown in FIG. 7B, at the time of reverse bias, the depletion layer of the n ⁻ layer sandwiched by the p ⁺ wells 9 expands, and the n ⁻ layer is pinched off.
^- spread greatly in the layer side, p ^- punch-through phenomenon in the layer can be prevented, a high breakdown voltage is maintained. This p ⁺
The depth of the well 9 is required to be about 15 μm or more, but at this depth, the lateral width of the p ⁺ well 9 is wide, the lateral resistance is large, and even if the injection of holes from the p ⁺ well 9 is small, Occurs. Further, in the state where holes are not injected from the p ⁺ well 9, the conduction area decreases and the on-voltage increases.
As a matter of course, if this depth is made shallow, a punch-through phenomenon easily occurs in the p ⁻ layer, which causes a problem that the breakdown voltage is lowered.

The object of the present invention is to solve the above problems,
It is an object of the present invention to provide a semiconductor device which has a small leakage current and can reduce both the on-voltage and the switching loss.

[0008]

In order to achieve the above object, a low-concentration first conductivity type semiconductor layer is formed on a high-concentration first conductivity type semiconductor layer to form a low-concentration first conductivity type semiconductor layer. A low-concentration second conductivity type semiconductor layer is formed on the surface layer, and a plurality of trench grooves reaching the low-concentration first conductivity type semiconductor layer from the surface of the low-concentration second semiconductor layer are selectively formed. A high concentration second conductivity type semiconductor region may be formed in the layer.
The planar shape of the trench groove may be stripe-shaped or cell-shaped.

A low concentration first conductivity type semiconductor layer is formed on the high concentration first conductivity type semiconductor layer, and a low concentration second conductivity type semiconductor layer is formed on the surface layer of the low concentration first conductivity type semiconductor layer. ,
A plurality of high-concentration second-conductivity-type semiconductor regions embedded in the low-concentration first-conductivity-type semiconductor layer near the low-concentration second-conductivity-type semiconductor layer may be selectively formed. By forming a high-concentration second conductivity type semiconductor region in the trench groove or by burying it to form a high-concentration second conductivity type semiconductor region, the low-concentration first conductivity type sandwiched between the high-concentration second conductivity type semiconductor regions is formed. The depletion layer extending to the semiconductor layer can be pinched off even at a low voltage. By doing so, a so-called punch-through phenomenon in which the depletion layer spreading in the low-concentration second conductivity type semiconductor layer reaches the surface electrode is suppressed, and a high breakdown voltage can be achieved. Further, by reducing the carrier concentration during conduction without introducing a lifetime killer, both low on-voltage and low switching loss can be achieved.

[0010]

1 is a sectional view of an element according to a first embodiment of the present invention. The high-concentration n-type semiconductor substrate is used as the n ⁺ buffer layer 2, the n ⁻ layer 1 is formed on this surface by epitaxial growth or the like, and the p ⁻ layer 5 is formed on the surface layer of the n ⁻ layer 1 by ion implantation or epitaxial growth. A trench groove 10 reaching the n ⁻ layer 1 is formed on this surface, and boron is vapor-phase diffused to the side wall and the bottom surface of the trench groove 10 to form ap ⁺ region 6. The diffusion depth of the p ⁺ region 6 is within several μm to suppress an increase in the area ratio of the p ⁺ region 6 to the active region. The surface electrodes 3, n on the p ⁻ layer 5 and the p ⁺ region 6
^{+ A} back electrode 4 is formed on the buffer layer 2. As these electrode materials, those which make ohmic contact are selected. By forming the p ⁺ region 6 to the trench 10, p provided p ⁺ well is a conventional element ^- an in diode p
⁺ As compared to the well, the width of the bottom of the p ⁺ region 6 (p ⁺ corresponding to the width of the well) small and, (corresponding to the depth of the p ⁺ well) distance from the surface of the p ⁺ region 6 to the bottom Can be increased. Therefore, the resistance in the lateral direction at the bottom of the p ⁺ region 6 is small, and the pinch-off in the n ⁻ layer 1 sandwiched between the p ⁺ regions 6 can surely occur at a low voltage.
The low-concentration n-type semiconductor substrate may be the n ⁻ layer 1, the p ⁻ layer 5 may be formed on one main surface, and the n ⁺ buffer layer 2 may be formed on the other main surface by diffusion or the like.

FIG. 2 is a plan view of the element of the first embodiment.
(A) is a stripe pattern diagram, (b) is a cell
The pattern figure of the shape is shown. In any case, the trench groove 10
Around p⁺Region 6 is formed. In the case of cellular
The cells are arranged in a triangle in this figure, but in a square
There are also arrangements such as shapes and hexagons. FIG. 3 shows the device of the first embodiment.
In the figure where voltage is applied, the figure (a) is the figure at the time of forward bias,
FIG. 7B shows a diagram when the reverse bias is applied. As shown in FIG.
The surface pattern of the trench groove is striped or
Is a cell shape (island shape). In the case of stripes, the groove width
If it is too narrow, p at the tip of the groove pattern not shown⁺
The curvature of the area 6 becomes tight and the withstand voltage decreases, and conversely it is too wide.
And p due to the voltage drop due to the current directly below the groove ⁺Region 6 to n^-
Since the injection of holes into the layer 1 occurs, the groove width is 1 to 15 μm.
Expected to be around. The depth of the trench groove 10 is too shallow
And p⁺N sandwiched between regions 6^-Pinch-off occurs sufficiently in layer 1
Without increasing, the leakage current increases. Therefore, p⁺Area 6 depth
The required length is about 3 μm or more. Also p⁺Sandwiched by region 6
P^-The width of the layer 5 varies depending on the setting of withstand voltage and ON voltage,
n^-Compared with the elongation of the depletion layer, which depends on the resistivity of layer 1,
If the width of the
The flow will increase. In addition, p in the trench groove 10⁺Territory
By forming the area 6, the current is p^-Layer 5
And n^-It flows at the junction of layer 1, and the impurity concentration in both layers is low.
To be a career without introducing a lifetime killer
Injection is suppressed. Therefore, the reverse recovery current is small.
Nonetheless, I didn't introduce Lifetime Killer
Therefore, low on-voltage can be achieved.

FIG. 4 is a sectional view of the element in the second embodiment of the present invention. The difference from FIG. 1 is that the trench groove 10 in the surface layer
Instead of forming the p ⁺ region 6 in the n ⁻ layer 1, a buried p ⁺ region 7 is formed in the n ⁻ layer 1. The embedded p ⁺ region 7 is not connected to the p ⁻ layer 5 and is in an electrically floating state. 5A and 5B are diagrams in which a voltage is applied to the element of the second embodiment. FIG. 5A shows a diagram when forward biased, and FIG. 5B shows a diagram when reverse biased. The buried p ⁺ region 7 is p ⁻
Injecting holes from the p ⁺ region 7 basically does not occur because it is in an electrically floating state without being connected to the layer 5. Since a voltage drop when current flows around the p ⁺ region 7 even when electrically connected small example, injection of holes from the p ⁺ region 7 does not occur. When reverse biased, the p ⁺ region 7 is p ⁻
Since it is close to the layer 5, the depletion layer extending to the n ⁻ layer 1 is almost equal to the anode potential, and the n ⁻ layer 1 sandwiched between the p ⁺ regions 7 is pinched off at a low voltage and can maintain a high breakdown voltage. . The diode having the buried p ⁺ region 7 has the same effect as that of the diode having the trench groove 10.

FIG. 6 shows reverse recovery current waveform diagrams of the conventional diode and the diode of the present invention. The diode (trench groove type embodiment (1) and buried type embodiment (2)) of the present invention has a small reverse recovery current I _rr , and the conventional diode (conventional example (1) pin type conventional example (1 ), P ⁺ well type conventional example (2)), the reverse recovery current reduction rate di
/ Dt is small and low switching loss results in soft recovery. This soft recovery waveform means that the surge voltage in the circuit generated by the product of the inductance of the circuit wiring and di / dt is small, which means that the device is less likely to be damaged by the surge voltage and is easy to use. Means that.

FIG. 7 shows a conventional diode and the diode of the present invention.
A voltage-current curve diagram for the reverse bias of the card is shown. Reverse buy
At the time of ass, p of the conventional example (2)⁺Well type diode
Compared with trench groove type (Example (1)) and filling
N in a diode of the type (Example (2))^-Layer 1 is in a pinch
It is easy to turn off, and the leakage current level is p of the conventional example (2). ⁺
It is smaller than the well type diode and has a pi of the conventional example (1).
It can be made as small as an n diode.

[0015]

According to the present invention, in the trench groove type or buried type diode, in the ON state, the current flows in the pn junction of the p ⁻ layer and the n ⁻ layer, and the lifetime killer is not introduced. In addition, since the carrier injection is suppressed, the ON voltage can be reduced because the lifetime is long even though the degree of conductivity modulation is relatively small. Further, in the reverse recovery process, the injected carriers are suppressed, so that the amount of accumulated carriers is small, and therefore the reverse recovery current and the reduction rate di / dt of the reverse recovery current can be reduced.
Therefore, a switching loss is small and a soft recovery element can be obtained. On the other hand, at the time of reverse bias, pinch-off is certainly generated as compared with the conventional diode having ap ⁺ well, so that the leakage current can be made as small as a pin diode.

[Brief description of drawings]

FIG. 1 is a sectional view of an element according to a first embodiment of the present invention.

FIG. 2 is a plan view of the first embodiment, in which (a) is a stripe pattern diagram and (b) is a cell pattern diagram.

FIG. 3 is a diagram in which a voltage is applied to the device of the first embodiment,
(A) is a diagram with forward bias, (b) is a diagram with reverse bias

FIG. 4 is a sectional view of an element according to a second embodiment of the present invention.

FIG. 5 is a diagram in which a voltage is applied to the device of the second embodiment,
(A) is a diagram with forward bias, (b) is a diagram with reverse bias

FIG. 6 is a reverse recovery current waveform diagram of a conventional diode and a diode of the present invention.

FIG. 7 is a voltage-current curve diagram of a conventional diode and a diode of the present invention when reverse biased.

FIG. 8 shows a state in which a voltage is applied to the element cross-sectional view of a pin diode (conventional example (1)), where FIG. 8A is a diagram when forward biased and FIG. 8B is a diagram when reverse biased.

FIG. 9 shows a state in which a voltage is applied to a device cross-sectional view of a p ^- in diode (conventional example (2)) having a p ⁺ well,
The figure (a) is a figure when forward biased, and the figure (b) is a figure when reverse biased.

[Explanation of symbols]

1 n ⁻ Layer 2 n ⁺ Buffer Layer 3 Front Electrode 4 Back Surface Electrode 5 p ⁻ Layer 6 p ⁺ Region 7 p ⁺ Region (Embedded) 8 p Layer 9 p ⁺ Well 10 Trench Groove A Anode K Cathode

Claims (3)

[Claims] 1. A low concentration first conductivity type semiconductor layer is formed on a high concentration first conductivity type semiconductor layer, and a low concentration second conductivity type semiconductor layer is formed on a surface layer of the low concentration first conductivity type semiconductor layer. A plurality of trench grooves reaching the low concentration first conductivity type semiconductor layer from the surface of the low concentration second conductivity type semiconductor layer are selectively formed, and a high concentration second conductivity type semiconductor region is formed in the surface layer of the trench groove. A semiconductor device characterized by being formed. 2. The semiconductor device according to claim 1, wherein the planar shape of the trench groove is a stripe shape or a cell shape. 3. A low concentration first conductivity type semiconductor layer is formed on a high concentration first conductivity type semiconductor layer, and a low concentration second conductivity type semiconductor layer is formed on a surface layer of the low concentration first conductivity type semiconductor layer. A plurality of embedded high-concentration second-conductivity-type semiconductor regions are selectively formed in the low-concentration first-conductivity-type semiconductor layer in the vicinity of the low-concentration second-conductivity-type semiconductor layer. Semiconductor device.