JPH04355966A - Electrostatic induction type semiconductor element and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable an electrostatic induction type semiconductor element to be enhanced in ON-OFF characteristics by a method wherein a prescribed high resistive layer generated at a boundary between a p base layer and an epitaxial growth n layer and a high resistive layer of a channel section are used together with micro-processing executed on a cathode side. CONSTITUTION:An n<-> epitaxial growth layer 12 is formed on an n<-> substrate 7, and a mesa etching process is carried out to take out an Al gate electrode 2. A p base layer 6 is doped with boron as impurities and the n emitter layer 4 is doped with phosphorus as impurities, an epitaxial growth layer of high resistance turned into an i layer sandwiched between the layers 6 and 4 is formed as thick as 1-2mum or so in thickness li to constitute a p-i-n structure. Therefore, a channel region becomes high in resistance, and most of the channel region turned into an i layer made to extend from the vicinity of the p base layer 6 to the n emitter layer 4, and the channel region and the n emitter layer 4 are small in resistance, and a device of this design is close to a surface gate type element in structure.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to electrostatic induction thyristors and electrostatic induction transistors, which are high-speed and highly efficient switching semiconductor devices compatible with high frequencies.
The present invention relates to an electrostatic induction type semiconductor element that configures the vicinity of the gate and channel without impairing both high-speed switching performance and gate breakdown voltage performance.

0002

[Prior Art] A cross-sectional view of a unit segment of a conventional static induction thyristor (also called SI thyristor) or static induction transistor (also called SI transistor) is shown in FIG.
Shown in a), (b), and (c). In FIG. 1, 1 is the cathode electrode (source electrode), 2 is the gate electrode, 3 is the anode electrode (drain electrode), 4 is the n emitter (source) of the n+ diffusion layer, 5 is the n- layer in the epitaxial growth layer, and 6 is the n- layer in the epitaxial growth layer. 7 is the p base of the p+ diffusion layer, 7 is the n- type or i type substrate, 8 is the p emitter (drain) of the p+ diffusion layer, 9 is the insulating layer of silicon dioxide (SiO2), 10 is the n channel, 11 is by etching Deletion region, 12 is epitaxial growth layer, 13 is capacitance near the gate, 14
is the resistance rs between the p base and n emitter, and the name in parentheses indicates the name of the static induction transistor. In the following description, in order to simplify the explanation, a case of an electrostatic induction thyristor will be explained.

[0003] The following references were used for FIGS. 1(a), (b), and (c). Figure 1(a) “Characteristics of 1600V, 300ASI thyristor” by Muraoka et al.
Institute of Electrical Engineers of Japan materials EDD-88-56, SPC-88-54
, 67 (1988) Tatsuta et al. "Characteristics of high frequency power SIT" Institute of Electrical Engineers of Japan materials EDD-87-68, SPC-87-52
, 61 (1987) Figure 1(b) H. Gruening. et. al. "Field
Controlled Thyristors aN
ew Family of PowerSemicon
ductors with Advanced Cir
``cutry'' Conf. Rec. PESC '88, 1311
(1988) Special Publication Showa 56-2614
Publication No. 8 No. 1, 2, 3, 6 (c) Map Special Publication 1984-4
Publication No. 1165 Figures 14 and 16 Special Publication Showa 62-21
Publication No. 275, Figure 7(a) J. Nishizawa
．． et. al. IEEE Trans. Electr
on Devices ED-22, pp185-1
95 (1975)Fig. 28 Figure 1(c) Tadano et al. “Switching characteristics of short-circuit structure SI thyristor”
Institute of Electrical Engineers of Japan materials EDD-90-59, SPC-90-58
(1990)

The advantages and disadvantages of conventional electrostatic induction thyristors will be explained as follows, focusing on the structure of the cathode electrode.

FIG. 1(a) is called a "buried gate type" in which an n- epitaxial layer 12 is grown on the cathode side, and a portion 11 marked with an "X" is removed by etching. As an advantage, since the epitaxial layer 12 between the cathode and the gate can be made thicker, the gate-cathode withstand voltage can be increased (70 to 200 V), so the manufacturing yield is high.
It is also possible to press the cathode and incorporate it into the seal.
One example is that it can be used as a high-power switching element. However, as a disadvantage, this type increases the thickness of the epitaxial layer 12 for power, but during epitaxial growth, outdiffusion from the p base layer 6 and substrate 7 forms a stable n- layer 5 with high resistance. is difficult, and usually NB = 1 to 4 x 1015 cm-
It is formed in about 3. Therefore, the capacitance Cg formed between the gate and cathode
(In case of step joint), Cg = {(qε0 εs NB ) /2(Vb
i-V)}1/2 ■,
Here, ε0 is the permittivity of vacuum, εs is silicon (Si)
NB is the n-type impurity concentration in the epitaxial layer, Vbi is the built-in potential, and V is the reverse bias (minus). This capacitance ideally increases the resistance of the n- layer, i.e., the i-layer (for example, NB≦1×1013
cm-3). That is, when turning on the electrostatic induction thyristor, the charging time (time constant) τ=Cg×rs that limits the electrostatic induction effect is large. Here, rs represents the resistance when current is applied between the n emitter 4 and the p base 6. The current flowing in the RC circuit system is i
=(V0/rs)exp(-t/ε), where V0 is the charging voltage and t is the time. Therefore, in this type, as the thickness of the epitaxial layer 12 becomes thicker, the turn-on time increases significantly, resulting in a slower device. Furthermore, by increasing the thickness of the epitaxial layer 12, it becomes difficult to miniaturize the cathode, and since a large number of channels 10, which are current conducting regions, are required, a central region of the unit segment is created, where there is a delay in drawing current from the gate electrode 2. . In other words, the turn-off performance is also limited, so although it is suitable for power devices because of the epitaxial layer 12, high-speed performance cannot be expected.

FIG. 1(b) is called the "cut gate type", and the n- substrate 7 is cut by dry etching to form a vertically long channel 10 (~25 μm).
m). This type can increase the speed by performing microfabrication, but since the channel is long in the vertical direction, it is disadvantageous for the on-characteristics.
The reason is that the channel width cannot be maintained even though the device is turned off by the gate reverse bias (
For example, 5 μm or more), the p base layer 6 and the n emitter layer 4 must be placed close to each other, and their respective high impurity concentrations come into contact, resulting in a large impurity concentration gradient.
+p+ junction, so planar junction cathode
The gate reverse breakdown voltage can only be about 7 to 15V. This is a problem unique to the planar type, and is a common problem with Figure 2(c).Due to manufacturing, it is difficult to obtain a uniformly stable cathode and gate breakdown voltage, and due to the low breakdown voltage, spikes may occur when installing the device. The disadvantage is that it is easy to destroy.

FIG. 1(c) is called a "planar type" in which a cathode electrode 1 and a gate electrode 2 are provided on substantially the same plane. As an advantage, the electrostatic capacitance Cg formed between the gate and the cathode is small, and the on-state performance is the best. Generally, to improve the off-performance of a thyristor, the anode short-circuit rate is increased or lifetime control is used, but this reduces the on-performance. However, even if the off-performance of a device with excellent on-performance is improved, the change in on-performance will be small or negligible. "
The "planar type" allows the cathode side to be minimized, has a large current-carrying area, and has a high area utilization rate. Additionally, the gate electrode can be placed right next to the channel, resulting in low current extraction resistance to the gate electrode and excellent turn-off performance. However, as a disadvantage, as in Fig. 1(b),
Since the n emitter layer 4 and the p base layer 6 have a planar connection with a large impurity concentration gradient, the cathode electrode 1
, the breakdown voltage between the gate electrodes 2 is only about 15V at most. Therefore, as before, there are problems in terms of yield and the fact that it is easy to break during use.

[0008]

SUMMARY OF THE INVENTION The present invention aims to obtain a static induction thyristor with good performance by taking advantage of the advantages of each type of conventional static induction thyristor and reducing the drawbacks thereof. It is something.

That is, in the "buried gate type" shown in FIG. 1(a), the distance between the gate and the cathode is p+ n- n+
Because it is a type, it is thick and limits the electrostatic induction effect during switching.
By providing 2, the reverse breakdown voltage between the gate and the cathode can be increased, and the advantage of being suitable for power devices can be utilized.

[0010] Also, the "notch gate type" shown in Fig. 1(b)
In this case, the reverse breakdown voltage between the gate and the cathode is about ~15V because the channel is long and the on-performance is disadvantageous, and the junction with the p base 6 is formed on the same plane as the n emitter 4 surface (planar junction). In other words, we will improve the problems that can only be achieved through manufacturing processes, such as instability in manufacturing and susceptibility to breakage in application.

Furthermore, in the "planar type" shown in FIG. 1(c),
Because the n-emitter 4 and p-base 6 form a planar junction with a large impurity concentration gradient, the reverse breakdown voltage between the gate and cathode can only be about 15V.
improve the same shortcomings. However, on the contrary, the capacitance Cg between the gate and cathode and the resistance rs during conduction between the n emitter 4 and the p base 6 are minimized, resulting in excellent on performance, and the channel is connected via the p base layer when turned off. It takes advantage of the fact that it is effective in off-performance, which makes it easy to draw current, and that the cathode side can have a minimized structure, making effective use of area.

0012

[Means for Solving the Problems] In the electrostatic induction type semiconductor device according to the present invention, the dimension on the short width side of the unit segment of the buried gate type device is limited by the gate diffusion depth, the size of the gate, the cathode electrode, etc. The area between the impurity diffusion layer of the main electrode closest to the gate electrode diffusion layer and the surface of the gate electrode diffusion layer facing it is
2 μm, and an i-type high resistance layer in which p-type and n-type impurities are mixed in almost equal amounts is provided between them, and the peak position (true A high-resistance layer similar to the i-type high-resistance layer is also provided in the channel region near the gate, and the channel region is provided in stripes along the longitudinal direction of the unit segment, as in the surface gate type, and the gate is drawn out. It is characterized in that the electrodes are placed as close as possible on both sides. In the method for manufacturing a static induction type semiconductor device according to the present invention as described above, the impurity diffusion layer of the main electrode closest to the diffusion layer for the gate electrode is placed between the surfaces of the diffusion layer for the gate electrode opposite thereto in an equivalent and opposite manner. formed by epitaxial growth so as to be in contact with a conductive impurity concentration of
An impurity opposite to the impurity of the gate electrode diffusion layer is diffused to form an i-type high resistance layer with a thickness of 1 to 2 μm in which p-type and n-type impurities are mixed in almost equal amounts on the contact surface. When forming the channel region from the potential peak position (true gate) generated in the semiconductor substrate by the gate electrode diffusion layer to the nearest main electrode diffusion layer, the gate is formed during epitaxial growth. This method is characterized in that a high-resistance layer equivalent to the i-type high-resistance layer is provided by also utilizing p-type or n-type impurities outdiffused from the surface of the electrode diffusion layer. Moreover, if the central part of the boundary facing the channel region of the diffusion layer of the main electrode closest to the channel region is formed deeply toward the true gate side, a more effective electrostatic induction type semiconductor element can be obtained.

The features of the method for manufacturing an electrostatic induction type semiconductor device according to the present invention as described above can be listed in detail as follows. In particular, in order to improve turn-on performance, a time constant τ=C corresponding to the charging time between gate and cathode
In order to reduce g × rs , capacitance Cg must be suppressed without including almost any resistance rs such as in a ``planar type'' or ``buried gate type''. In order to improve both turn-off performance and turn-on performance, the resistance between the channel, that is, the p-base layer and the gate electrode is lowered to improve gate current control performance. For this reason, the diffusion depth of the p base layer, which is as thin as that of the "planar type", is used to finely structure the arrangement of the cathode and gate. For power devices, in order to ensure a stable reverse breakdown voltage between the gate and cathode, which is several steps higher than that of the planar type, a striped channel is embedded using epitaxial growth, similar to the planar type. This results in a "buried gate type", but in order to reduce the capacitance generated between the p base layer and the n emitter layer, the vicinity of the channel is made into an i layer during this buried epitaxial growth, and the p base layer has an impurity concentration gradient. By bringing the N emitter layer and the N emitter layer into contact with each other at an impurity concentration of 1015 cm-3 or less, a high resistance I layer can be realized at the junction.

[0014] In this way, the advantages of the "planar type" and the "buried gate type" are combined to realize a "planar-like stripe type electrostatic induction device" having a junction formation that offsets the disadvantages. In addition, when forming the p base layer, silicon dioxide (S) is added before epitaxial growth.
p+ impurities (for example, boron) are diffused using a selective mask (iO2), but the thickness can be made thinner than in the conventional buried gate method, and if the amount of diffusion is the same, when the depth is determined by later diffusion, In this method, the average concentration of the p base layer can be increased, so that the capacitance Cg is further reduced.

[0015] Furthermore, the formula (■), Cg = {(qε0 εs N
B) /2(Vbi-V)}1/2, Vb
i=(kT/q)ln{NB×NPB/ni2}, where ni is the intrinsic carrier concentration at room temperature, which is 1.45×1010 cm−3, and NPB is the p-based impurity concentration. , NPB rises, so Vbi rises, and in formula (2), Cg conversely falls.

[0016]

[Operation] The electrostatic induction type semiconductor device according to the present invention will be explained based on FIGS. 2 to 5 while comparing it with a conventional electrostatic induction type semiconductor device. Each reference numeral in the figure indicates the same part as the reference numeral in FIG. 1, and 5' is an epitaxially grown layer formed into an i-layer. (A) in FIGS. 2 to 5 is a cross-sectional view of the cathode side focusing on a single channel, and (B) is a resistance value (SR value). There is an inversely proportional relationship between the resistance value R and the effective impurity concentration, and as R increases, the i-layer, that is, int
When a rinsic layer is formed and a potential is applied, the depletion layer tends to expand, and the potential is also applied almost uniformly, resulting in a decrease in the capacitance of the depletion layer.

FIG. 2 is a model showing only one channel portion of a conventional "buried gate type". Conventionally, with this type, heat application during epitaxial growth, etc.
Since the impurities in the p base layer 6 may be thermally diffused into the epitaxial growth layer, the thickness of the p base layer 6 is approximately 10 to 20 mm.
The thickness is several μm, which is thicker than the approximately 5 μm thickness of the front gate shown in FIG. In addition, in order to ensure reverse breakdown voltage between the gate and cathode (70 to 200 V), a thick n layer (resistivity: 1 to 5 Ω-cm) of epitaxial growth layer is provided between the p base layer 6 and the n emitter layer. ing. As shown in FIG. 1(a), this type usually uses a method of increasing area efficiency by arranging a large number of channels. Usually in this type, the surface on which each impurity is diffused is exposed during epitaxial growth, so it is very difficult to uniformly grow the high-resistance i-layer epitaxial layer. This type of depth spreading resistance (S
R) When looking at the distribution, it is noticed that two regions of high resistance appear at the ends of the p base layer (P1 and P2). Here, the p-type impurity in the p-base layer and the n-type impurity in the n-layer of the substrate or epitaxial growth layer are present in almost the same amount.
The influence of p-type or n-type impurities is weakened, and the int
This is an area that has become rinsic.

If the i-layer can be formed between the p-emitter layer 6 and the n-base layer 4 with the dimensional structure shown in FIG. 2 as shown in FIG. It should be possible to realize a high-speed device with a small time constant τ by just having a small resistance rs between the n emitter and the p base, which is equivalent to the resistance rs that exists in the high resistance i It is extremely difficult, even impossible, to grow epitaxial layers uniformly. In reality, the thinner the i-layer is, the smaller the resistance rs is, so that better characteristics can be obtained. In addition, when creating a "buried gate type", the region formed at the initial stage of epitaxial growth in the channel region from the side of the true gate to the n emitter 4 is
In reality, this is an autodoping phenomenon in which p-type impurities jump out of the epitaxial growth target during epitaxial growth and are incorporated into the epitaxial growth layer.In order to suppress the epitaxial layer from inverting to p-type, compensation is performed with n-type impurities. It is still in the i-tier.

In the present invention, a high resistance layer of 1 to 2 μm generated at the boundary between the p base layer 6 and the epitaxially grown n layer and a high resistance layer in the channel region are actively formed together with microfabrication on the cathode side. As shown in the "planar type" shown in Figure 4, it is possible to obtain a sufficient voltage resistance between the gate and cathode of 50 to 70 V while maintaining excellent performance in both on and off characteristics. The present invention provides a structure of an electrostatic induction type semiconductor element that enables the following. In other words, the structure shown in FIG. 5 is the structure of one embodiment of the electrostatic induction thyristor according to the present invention, and compared to the conventional "buried gate type" shown in FIG. (less than gate type), p base layer 6 and n emitter layer 4
Since it is formed of a high resistance layer 5' using diffusion and epitaxial growth with a gap of several μm, the capacitance Cg is small and the resistance rs is so small that it can be ignored, so turn-on is as fast as the "surface gate type". Since the gate electrode 2 is close to the channel, both turn-on and turn-off are fast, and the structure is suitable for high frequency operation of power devices.

The p base layer 6 and the n emitter layer 4 are thin i
Since the pin structure is formed through the layers, carriers enter the channel from the n emitter layer at high speed, and it is considered that the current I ideally flows at high speed until it passes the channel, as shown in the following equation. I=q(kT/2πmn)1/2nk exp{-
(φ-qVG(0))/kT} where k is Boltzmann's constant, T is absolute temperature, φ is diffusion potential, nk is free electron density in the cathode region, q is the amount of charge, mn is the effective mass of electrons, VG(0) indicates the true gate potential.

The manufacturing method surrounding the epitaxial growth step, which is the key to the present invention, will be explained with reference to FIG. Figure 1
1(a) to (e) sequentially show cross sections at each step from epitaxial growth to mesa etching processing, and (c') and (c'') and (d') and (d'') respectively ( The impurity concentration N (cm3) and resistance value rs in the x1 and x2 directions in c) and (d) are shown.

(a) shows a p+ base diffusion layer 6 with a peak boron concentration of 2×10 19 (cm −3 ), selectively excluding the channel portion 10 and provided by diffusion.

In (b), hydrogen chloride (
HCl) gas was also introduced to clean the surface, and hydrogen (H2) gas was used as a carrier gas to clean the surface.
l4), n- epitaxial growth with a resistivity of 4 Ω-cm was performed at 1180°C at a growth rate of 0.18 μm/min according to the epitaxial growth method using phosphine (PH3).
Perform μm. During this growth, boron particles are out-diffused from the p-base layer 6 of the substrate to prevent p-inversion of the epitaxially grown layer.
PH3) Introduce gas.

That is, at the point (c) when the epitaxial growth is completed, as shown in FIG.
1 profile is formed so that boron (B) and phosphorus (P) are present in approximately equal amounts near the true gate shown by arrow A, and a high-resistance layer is formed as shown in figure (c''). At this time, not only the x1 position but also the portion epitaxially grown on the p base layer becomes a high resistance layer.

Furthermore, in (d), the cathode surface n emitter layer 4
(peak phosphorus concentration 1 x 1020 cm-3)
) 1.2 μm by diffusion. Thus, figure (d′
), approximately 1.2 μm of boron (B) and phosphorus (P) are deposited between the p base layer 6 grown approximately 1.4 μm from the epitaxial growth surface. The region with equal amounts is formed as a high resistance layer with resistivity ≧100 Ω-cm, as shown in figure (d″), and the n emitter layer on the channel is additionally diffused to reduce the resistance rs. I try to do that.

In (e), finishing is performed by mesa etching.

As described above, by controlling boron and phosphorus during epitaxial growth, and due to the adjacency effect between the p base layer 6 and the n emitter layer 4, the channel resistance is reduced and the gap between the p base layer and the n emitter layer is reduced. By increasing the resistance, the structure of the electrostatic induction type semiconductor element of the present invention can be realized.

6 to 8 show embodiments of the electrostatic induction thyristor of the present invention. FIG. 6 shows a basic embodiment, where n-
An n- epitaxial growth layer 12 of 5 Ω-cm and a thickness le of 4 μm is formed on the substrate 7, and aluminum (Al
) Mesa etching is performed to take out the gate electrode 2. The arrangement pitch lp of unit segments is p
Base layer 4 thickness lPB≒4μm, channel width lC
Although it varies depending on the shape such as H≒4 μm, segment width lk≈10 μm, and their processing accuracy, in this embodiment, lP = 22 μm, and microfabrication that is different from the usual "buried gate type" is realized.

In the above explanation, boron was used as impurities for the p base layer 6 and phosphorus was used for the n emitter layer 4. It is sufficient that the thickness li is approximately 1 to 2 μm to form a pin structure. By the way, since the epitaxial growth method mentioned above is used, the channel region also has a high resistance, so there are many i-layer regions from around the p base layer 6 to the n emitter layer 4, and from the channel to the n emitter layer 4. The resistance rs up to the emitter layer is extremely small, and the device has a structural concept similar to that of a surface gate type.

As is well known, when gate excavation etching is performed deeply, variations increase, but the etching depth of the present invention can be as shallow as 3.5 .mu.m, so that variation is less likely to occur, which is an advantage.

Furthermore, FIGS. 7 and 8 show an example in which the slight resistance rs, which can be said to be parallel to the capacitance Cg from the channel to the n-emitter layer, is further reduced. In reality, it is difficult to make the entire area from the true gate to the n emitter layer into an i layer, and the area near the n emitter layer in the channel part is made into an n- layer.
This is because the resistance rs can be reduced by layering.

FIG. 7 shows a structure in which the n-emitter layer in the center of the segment facing the channel is additionally diffused to deepen the layer 4' by about 1.5 μm toward the true gate.

In FIG. 8, in order to obtain a similar effect with only one n emitter diffusion, a 1.5 μm in the center of the segment is shown.
After forming a groove 15, n-emitter diffusion is performed, and an n-emitter layer is formed in accordance with the shape of the groove 15, thereby forming an n-emitter layer that is approximately 1.5 μm deep only in the channel portion.

Although the above explanation has been made regarding an n-channel device, it goes without saying that a p-channel device can also be constructed in the same manner.

[0035]

[Embodiment] FIG. 12 is a diagram showing an embodiment of the electrostatic induction thyristor according to the present invention, in which (a) is a top view of the cathode surface, and (b) is a cross-sectional view along the line x to x'. Show the diagram.

In the cathode side structure of FIG. 8, between the aluminum gate electrode 2 on the p+ p base diffusion layer 6 and the aluminum cathode electrode 1 on the n emitter layer 4,
A polyimide insulating film 17 is provided, and a cathode electrode 1' for wiring is further formed over the aluminum cathode electrode 1, thereby reducing wiring resistance.

Furthermore, on the anode side, p emitter diffusion layers 8 and anode short n+ diffusion layers 16 are alternately provided to form an anode short structure.

[0038]

Effects of the Invention FIG. 9 shows the turn-on times shown by broken lines and solid lines, respectively, for a conventional "buried gate type" electrostatic induction thyristor and a "planar-like stripe type" electrostatic induction thyristor according to the present invention. tg
It is a graph showing the correlation between t (μs) and turn-off time tgq (μs). The structure of this device is 6 mm square, with an n base layer thickness of 250 μm, and a short hole in the n+ layer is locally provided on the anode side, so that the ratio of the width of the n+ layer to the width of the p emitter layer is The turn-off time tgq was adjusted by changing the expressed anode short rate. FIG. 9 is a graph showing the results of these various adjustments.

The measurement conditions were as shown in FIG. 10, with applied voltage VD = 300 V, cut-off current IT = 10 A, and room temperature measurement with resistance added. The turn-on signal for the gate is 1.0 with a peak value IgON = 0.3A.
μs flow, turn-off signal is peak value Igp≒IT
It becomes.

As is clear from FIG. 9, compared to the conventional electrostatic induction thyristor, the electrostatic induction thyristor according to the present invention can improve the trade-off relationship between turn-on and turn-off, and reduce switching loss. As a feature of the device according to the present invention, even if the turn-off time tgq is reduced, the turn-on time tgt hardly increases. This is as reported for the "planar type" (
“Performance improvement of SI thyristor by proton irradiation” by Abe et al.; Institute of Electrical Engineers of Japan material EDD-89-49 (198
9)). In addition, the reverse breakdown voltage between the gate and cathode of the device according to the present invention is 50 to 60V, which is 1 of the “planar type”.
It was found that the power device has a voltage that greatly exceeds 0 to 15 V, has excellent stability during manufacture and use, and operates on the safe side even against spike voltages generated between the gate and cathode due to its high speed. This is because, as mentioned earlier, the pin structure is such that a thin i-layer is sandwiched between the gate and cathode.

[Brief explanation of drawings]

[Figure 1] Figures 1 (a), (b), and (c) are cross sections comparing the structures of conventional electrostatic induction thyristors of "buried gate type,""cut gate type," and "planar type," respectively. The figure shows.

[Figure 2] Figure 2 (A) is a cross-sectional view of the cathode and gate vicinity showing the structure of one segment of a conventional "buried gate type" electrostatic induction thyristor, and Figure 2 (B) shows the spreading resistance with respect to its depth. It is a distribution map.

FIG. 3(A) is a cross-sectional view near the cathode and gate showing the structure of one segment assuming that the epitaxial growth layer of a conventional "buried gate type" electrostatic induction thyristor is composed of an i-layer; FIG. 3(A) is a spreading resistance distribution diagram with respect to the depth.

FIG. 4(A) is a cross-sectional view of the cathode and gate vicinity showing the structure of one segment assuming that the n-channel part of a conventional "planar type" electrostatic induction thyristor is composed of an i-layer; FIG. 4(A) is a spreading resistance distribution diagram with respect to the depth.

FIG. 5(a) is a cross-sectional view of the cathode and gate vicinity showing the structure of one segment of the "planar-like stripe type" electrostatic induction thyristor according to the present invention, and FIG. FIG.

FIG. 2 is a cross-sectional perspective view of the vicinity of the cathode and gate of an embodiment of the electrostatic induction thyristor according to the present invention.

FIG. 7 is a cross-sectional perspective view of the cathode and gate vicinity of another embodiment of the electrostatic induction thyristor according to the present invention.

FIG. 8 is a cross-sectional perspective view of the cathode and gate vicinity of still another embodiment of the electrostatic induction thyristor according to the present invention.

FIG. 9 is a graph showing the correlation between turn-on time and turn-off time, comparing the electrostatic induction thyristor according to the present invention and a conventional electrostatic induction thyristor.

FIG. 10 is a switching waveform diagram of an electrostatic induction thyristor.

11(a) to 11(e) sequentially show cross sections of the electrostatic induction thyristor of the present invention at each step from epitaxial growth to mesa etching processing,
Further, (c') and (c'') and (d' and (d'')) indicate the impurity concentration N (cm3) and the resistance value rs in the x1 and x2 directions in (c) and (d), respectively.

FIG. 12 is a diagram showing an embodiment of the electrostatic induction thyristor according to the present invention, in which (a) is a top view of the cathode surface, and (b) is a cross-sectional view along the line x to x'. Show the diagram.

[Explanation of symbols]

1 Cathode electrode 1' Cathode electrode 2 for wiring Gate electrode 3 Anode electrode 4 N emitter layer 5 N- layer in epitaxial growth layer 5'i epitaxial growth layer 6 P base layer 7 N- type or i type substrate 8 P Emitter layer 9 Insulating layer of silicon dioxide 10 N-channel 11 Etched region 12 Epitaxial growth layer 13 Capacitance near the gate 14 Resistance between the p-base layer and the n-emitter layer 15
Groove 16 Anode short n+ Diffusion layer 17 Polyimide insulation layer

Claims (1)

[Scope of Claims] [Claim 1] Among electrostatic induction thyristors and electrostatic induction transistors, a buried gate type electrostatic transistor in which the main electrode surface closest to the gate electrode surface appearing on the semiconductor substrate surface is formed higher. In an inductive type semiconductor device, the short width side dimension of the unit segment of the buried gate type device is miniaturized to the minimum width limited by the gate diffusion depth and the size of the gate and cathode electrode, and the gate electrode diffusion layer is The impurity diffusion layer of the main electrode closest to the main electrode and the surface of the diffusion layer for the gate electrode opposite to this are placed close to each other by 1 to 2 μm, and an i-type height layer is formed in which almost equal amounts of p-type and n-type impurities are mixed between them. A resistance layer is provided, and a high resistance layer equivalent to the i-type high resistance layer is also provided in the channel region near the peak position (true gate) of the potential generated in the semiconductor substrate by the gate electrode diffusion layer, and An electrostatic induction type semiconductor device characterized in that a channel region is provided in a stripe shape along the longitudinal direction of a unit segment, such as a surface gate type, and gate lead-out electrodes are provided as close as possible on both sides of the channel region. 2. The method of manufacturing a static induction type semiconductor element according to claim 1, wherein the impurity diffusion layer of the main electrode closest to the gate electrode diffusion layer is formed between the surfaces of the gate electrode diffusion layer opposite thereto. Formed by epitaxial growth so that they are in contact with impurity concentrations of equal and opposite conductivity, and an i-type high-resistance layer with a thickness of 1 to 2 μm is formed at the contact surface with approximately equal amounts of p-type and n-type impurities. In this way, an impurity opposite to that of the gate electrode diffusion layer is diffused, and this causes the potential generated in the gate electrode diffusion layer to spread from the peak position (true gate) in the semiconductor substrate to the nearest main electrode diffusion layer. When forming the channel region by the gate buried epitaxial growth, the p-type or n-type impurity out-diffused from the surface of the gate electrode diffusion layer during the epitaxial growth is also used to form the channel region of the i.
A method for manufacturing an electrostatic induction type semiconductor element, characterized by providing a high resistance layer equivalent to a mold high resistance layer. 3. The electrostatic induction type semiconductor device according to claim 1, wherein the central part of the boundary facing the channel region of the diffusion layer of the main electrode closest to the channel region is formed deeply toward the true gate side.