JP2020027815A - Power semiconductor device and manufacturing method of the same - Google Patents

Abstract

To provide a power semiconductor device which can secure a gate pressure and has a high breakdown voltage and a high speed turn-on switching performance.SOLUTION: A power semiconductor device 1 comprises: a cathode region 12; a channel region 13 which can be conducted by a carrier implanted from the cathode region; a gate region 16 that nips the channel region 13, and can control a potential of the channel region 13 by an electrostatic induction field effect; a first cathode emitter region 14 arranged onto an upper part of the channel region 13 and the gate region 16; and a second cathode emitter region 15 arranged between the first cathode emitter region and the cathode region 12. An n-type impurity concentration of the first cathode emitter region 14 has concentration higher than that of a p-type impurity concentration to be auto-doped from the gate region 16, and the n-type impurity concentration of the second cathode emitter region 15 has concentration thinner than that of the n-type impurity concentration which becomes a poor pressure between the gate region 16 and the cathode region 12 which are required for a turn-off state.SELECTED DRAWING: Figure 1

Description

  The present embodiment relates to a power semiconductor device and a method for manufacturing the same.

  The static induction semiconductor devices include a static induction transistor (SIT) and a static induction thyristor (SIThy).

  The electrostatic induction type semiconductor device can perform high-speed switching because the current flowing through the channel can be controlled by the electrostatic induction electric field effect. In addition, a large current can be achieved by using a multi-channel structure.

JP-A-1997-246524 JP 2003-110117 A

Naohiro Shimizu: "Study on high-speed operation characteristics of electrostatic induction thyristor and its application", Doctoral dissertation, Tohoku University, November 2010, 3rd edition, Doctoral (engineering) degree awarded date, March 2011 March 9.

  In order to increase the withstand voltage of the power semiconductor device, a region for maintaining the withstand voltage is formed thick or the resistance is increased. For this reason, in the high breakdown voltage power semiconductor device, the on-resistance in the conductive state is likely to increase.

  In forming an electrostatic induction thyristor having a buried pn junction gate structure, providing a gradient concentration profile from the cathode region to the channel region is effective in achieving high carrier injection from the cathode region to the channel region. However, it is difficult to gradually increase the impurity concentration of the epitaxial layer from the gate to the cathode while forming the epitaxial layer. This is because monitor management during the process is difficult, and it is difficult to achieve high-accuracy concentration on a hardware surface such as a mass flow controller. Also, there is auto doping from the gate.

  The present inventors have demonstrated that in an electrostatic induction type power semiconductor device, high-speed turn-on performance is achieved by high carrier injection from the cathode region, on-resistance is reduced in a conductive state, and high gate breakdown voltage is ensured. A structure capable of withstanding pressure was found.

  The present embodiment provides a power semiconductor device which secures a gate breakdown voltage, has a high breakdown voltage, and has a high turn-on switching performance, and a method for manufacturing the same.

  According to one aspect of the present embodiment, the cathode region, a channel region through which carriers injected from the cathode region can conduct, and the channel region interposed therebetween, and the potential of the channel region is controlled by an electrostatic induction field effect. A possible gate region, a first cathode emitter region located above the channel region and the gate region, and a second cathode emitter region located between the first cathode emitter region and the cathode region. A first conductivity type impurity concentration of the first cathode emitter region is higher than a second conductivity type impurity concentration auto-doped from the gate region, and a first conductivity type impurity of the second cathode emitter region is provided. The concentration is lower than the first conductivity type impurity concentration required for the turn-off state, which is the breakdown voltage between the gate region and the cathode region. There, the power semiconductor device is provided.

  According to another aspect of the present embodiment, after forming an insulating layer on the high-resistance layer, patterning, forming a gate region with respect to the patterned opening window, forming the insulating layer After removal, a step of forming a first epitaxial layer on the exposed surface of the high-resistance layer, a step of forming a second epitaxial layer on the first epitaxial layer, and a step of forming a second epitaxial layer on the surface of the second epitaxial layer. Forming a cathode region, wherein the impurity concentration of the first conductivity type of the first epitaxial layer is higher than the impurity concentration of the second conductivity type which is auto-doped from the gate region to the first epitaxial layer. The impurity concentration of the first conductivity type of the second epitaxial layer is high, and the impurity concentration of the first conductivity type, which is a withstand voltage between the gate region and the cathode region necessary for a turn-off state, is low. Thinner than the object density, the method for manufacturing the power semiconductor device is provided.

  According to the present embodiment, it is possible to provide a power semiconductor device which ensures a gate breakdown voltage, has a high breakdown voltage, and has a high-speed turn-on switching performance, and a method for manufacturing the same.

FIG. 3 is a schematic plan pattern configuration diagram of a power semiconductor device according to an embodiment to which the present technology is applied. FIG. 2 is a schematic cross-sectional structural view taken along line II of FIG. 1. Operation | movement explanatory drawing of the turn-on state of the power semiconductor device which concerns on one Embodiment to which this technique is applied. Operation | movement explanatory drawing of the turn-off state of the power semiconductor device which concerns on one Embodiment to which this technique is applied. FIG. 2 is a schematic explanatory view near a gate of a power semiconductor device according to an embodiment to which the present technology is applied. FIG. 4 is a schematic explanatory diagram of an impurity concentration profile near the gate along the X _C axis when the auto doping concentration is high. FIG. 9 is a schematic explanatory view of an impurity concentration profile near the gate along the X _C axis when the auto doping concentration is low. Schematic illustration of the impurity concentration profile near the gate along the X _G axis when auto-doping concentration is dark. It is a manufacturing method of a power semiconductor device according to an embodiment to which the present technology is applied, wherein (a) a gate patterning process diagram, (b) a gate diffusion process diagram, (c) a first epitaxial layer forming process diagram, d) Process chart for forming the second epitaxial layer. FIG. 13 is a schematic cross-sectional structure diagram of a power semiconductor device according to another embodiment to which the present technology is applied.

  Next, the present embodiment will be described with reference to the drawings. In the drawings described below, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the plane size of each component is different from the actual one. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. In addition, it is needless to say that the drawings include portions having different dimensional relationships and ratios.

  Further, the embodiments described below exemplify an apparatus and a method for embodying the technical idea, but do not specify the material, shape, structure, arrangement, and the like of each component. This embodiment can add various changes within the scope of the claims.

  A schematic plane pattern configuration of a power semiconductor device 1 according to an embodiment to which the present technology is applied is represented as illustrated in FIG. 1, and a schematic cross-sectional structure along a line II in FIG. 1 is illustrated in FIG. 2. It is represented as shown.

  A power semiconductor device 1 according to an embodiment to which the present technology is applied includes an electrostatic induction thyristor structure having a single gate (SG) structure, as shown in FIGS.

  As shown in FIGS. 1 and 2, a power semiconductor device 1 according to an embodiment to which the present technology is applied includes a cathode region 12, a channel region 13 through which carriers injected from the cathode region 12 can conduct, A gate region 16 that can control the potential of the channel region 13 by the electrostatic induction field effect with the region 13 interposed therebetween; a first cathode emitter region 14 disposed above the channel region 13 and the gate region 16; A second cathode emitter region disposed between the region and the cathode region;

  Here, the impurity concentration of the first conductivity type of the first cathode emitter region 14 is set to be higher than the impurity concentration of the second conductivity type which is auto-doped from the gate region 16. Further, the impurity concentration of the first conductivity type of the second cathode emitter region 15 is set to be lower than the impurity concentration of the first conductivity type which is required to be turned off and which is the breakdown voltage between the gate region 16 and the cathode region 12.

  The first cathode emitter region 14 has a first epitaxial layer grown at a first constant impurity concentration, and the second cathode emitter region 15 has a second epitaxial layer grown at a second constant impurity concentration. Prepare.

The first epitaxial layer has a thickness such that the autodoping concentration from the gate region 16 to the first epitaxial layer is 1 × 10 ¹⁴ (cm ⁻³ ) or less.

  The second epitaxial layer has a thickness such that a depletion layer spreading around the gate region 16 does not reach the cathode region 12 when a reverse bias voltage is applied between the gate region 16 and the cathode region 12 to turn off the gate region 16.

  Further, as shown in FIGS. 1 and 2, an anode region 22 having a conductivity type opposite to that of the cathode region 12 and a second conductivity type carrier having a conductivity type opposite to the first conductivity type injected from the anode region 22 are used. It may include a buffer region 20 to be controlled, and a high resistance layer 18 disposed between the buffer region 20 and the gate region 16 and the channel region 13.

  The cathode region 12 is formed of an n-type semiconductor and functions as a SIThy cathode having an SG structure.

  The first conductivity type carriers correspond to electrons.

  Gate region 16 is formed of a p-type semiconductor and functions as a main current control region.

  As shown in FIGS. 1 and 2, the channel region 13 is sandwiched between adjacent gate regions 16 and functions as a region in which conduction of main current can be controlled.

  The cathode emitter regions (14, 15) are arranged between the cathode region 12 and the gate region 16, and convert the first conductivity type carriers injected from the cathode region 12 from the cathode region 12 to the channel region 13 to improve the efficiency. Sufficient withstand voltage can be secured when applying a reverse bias voltage between the gate region 16 and the cathode region 12 to turn off while appropriately conducting and diffusing and appropriately suppressing auto doping from the gate region 16. Function as an important area.

  The anode region 22 is formed of a p-type semiconductor, and functions as a SITHy anode having an SG structure.

  The second conductivity type carriers correspond to holes.

  The buffer region 20 is formed of an n-type semiconductor, controls the conduction of the second conductivity type carrier injected from the anode region 22, and the first conductivity type carrier injected from the cathode region 12 and conducts through the channel region 13. Function as a storage area.

  The high-resistance layer 18 is formed of a high-resistance n-type semiconductor or a p-type semiconductor capable of ensuring a high breakdown voltage between the anode and the cathode and between the gate and the anode.

  Further, as shown in FIGS. 1 and 2, the cathode electrode 10 disposed on the cathode region 12, the gate electrode 26 disposed on the gate region 16, and the anode electrode 24 disposed on the anode region 22 Is provided.

  The power semiconductor device 1 shown in FIGS. 1 and 2 includes a plurality of cathode electrodes 10 (cathode regions 12) divided into segments. In each segment unit, a multi-channel structure including a plurality of channel regions 13 that can control the conduction of the main current is formed between adjacent gate regions 16.

  The example in which the gate region 16 has a pn junction gate structure is shown, but may have another gate structure. For example, a Schottky gate structure, an insulated gate structure, a heterojunction gate structure, or the like may be provided. In a gate structure other than the pn junction gate structure, it is not necessary to consider auto-doping from the gate region, but it is disposed between the cathode region, the gate region, and the channel region, and at least the first cathode emitter region and the second cathode emitter region And the emitter region having the following. Further, the impurity concentration of the first cathode emitter region is higher than the impurity concentration of the second conductivity type, and the impurity concentration of the second cathode emitter region is such that the breakdown voltage between the gate region and the cathode region required for the turn-off state is obtained. The same applies to the setting of a smaller thickness.

  Further, the forward characteristic may include any of a normally-off characteristic, a semi-normally-off characteristic, and a normally-on characteristic.

  The normally-off characteristic is a characteristic in which a voltage between the gate and the cathode is zero volt and a withstand voltage between the anode and the cathode can be ensured.

  The normally-on characteristic means that when the gate-cathode voltage is zero volts, a conduction current flows through the anode-cathode to form an ON state, and a sufficient reverse bias (for example, from about -1 V to- By applying (approximately 20 V), a non-conductive state is established between the anode and the cathode, an off state is formed, and a characteristic that a withstand voltage between the anode and the cathode can be secured.

  The semi-normally-off characteristic is an intermediate characteristic between the normally-off characteristic and the normally-on characteristic. When the gate-cathode voltage is zero volts, the anode-cathode breakdown voltage can be ensured, and the anode-cathode breakdown voltage and the anode-gate This refers to the characteristic that the breakdown voltage is equal.

  Since the power semiconductor device 1 according to the embodiment to which the present technology is applied has a buried gate structure, a sufficient breakdown voltage can be secured between the gate and the cathode, and a normally-off characteristic, a semi-normally-off characteristic, or a normally-on characteristic. At least one of the characteristics selected from the group

  Further, as shown in FIGS. 1 and 2, a bevel region 34 is provided around each segment of the cathode electrode 10 and the gate electrode 26, and a sufficient withstand voltage can be secured between the gate terminal G and the cathode terminal K. It is.

  Here, a sufficient withstand voltage that can be secured between the gate and the cathode means that the forward characteristic is a withstand voltage level at which any of the normally-off characteristic, semi-normally-off characteristic, or normally-on characteristic can be adopted and the main current can be turned off by the gate. say.

  The power semiconductor device 1 according to one embodiment to which the present technology is applied uses an epitaxial layer having a constant concentration. The reason why the impurity concentration has a slope near the gate is to control carriers injected from the cathode region toward the channel region by the electrostatic induction effect. The vicinity of the cathode is formed with an appropriate constant impurity concentration.

  The power semiconductor device 1 according to an embodiment to which the present technology is applied uses a first epitaxial layer and a second epitaxial layer. Therefore, monitor management during the manufacturing process is easy. In addition, it is easy to increase the concentration with high accuracy on a hardware surface such as a mass flow controller. Further, the autodoping from the gate region 16 to the first epitaxial layer can be stably compensated.

  Therefore, the first-stage first epitaxial layer exhibits a desirable gradient concentration distribution including auto-doping, and the second-stage second epitaxial layer can be optimized in both film thickness and concentration.

(Turn-on state)
In the power semiconductor device according to the present embodiment, as shown in FIG. 3, in the turn-on state, a forward bias is applied between the gate region 16 and the cathode region 12, and the channel region 13 between the adjacent gate regions 16 is closed. The potential barrier decreases. As a result, as indicated by an arrow, an electron current is conducted from the cathode region 12 to the high resistance layer 18 via the second cathode emitter region 15 and the first cathode emitter region 14. The electrons injected into the high-resistance layer 18 accumulate in the buffer region 20 and the potential barrier to the hole distribution existing in the anode region 22 decreases. As a result, although not shown, a hole current is conducted from the anode region 22 to the high-resistance layer 18 via the buffer region 20. The holes injected into the high-resistance layer 18 are accumulated in the gate region 16, and the potential barrier of the channel region 13 between the adjacent gate regions 16 is further reduced. As a result, the state shifts to the latch-up state, and the power semiconductor device shifts to the ON state.

  In the power semiconductor device according to the present embodiment, resistance of second cathode emitter region 15 is reduced. As a result, high-speed turn-on performance is obtained by high injection of carriers (electrons) from the cathode region 12 to the high-resistance layer 18 via the second cathode emitter region 15 and the first cathode emitter region 14 through the second cathode emitter region 15. Can be.

(Turn off state)
In the power semiconductor device according to the present embodiment, as shown in FIG. 4, in the turn-off state, a reverse bias is applied between the gate region 16 and the cathode region 12 so that the channel region 13 between the adjacent gate regions 16 is closed. The potential barrier rises. As a result, a depletion layer 54 is formed around gate region 16, and electron current from cathode region 12 is cut off by depletion layer 54 between adjacent gate regions 16.

  That is, an electron current conducted from the cathode region 12 to the high resistance layer 18 via the second cathode emitter region 15 and the first cathode emitter region 14 is cut off, and electrons injected into the high resistance layer 18 are cut off. You. As a result, the potential barrier for the hole distribution existing in the anode region 22 increases. As a result, a hole current conducted from the anode region 22 to the high-resistance layer 18 via the buffer region 20 is cut off. As a result, the state shifts to the non-latch-up state, and the power semiconductor device shifts to the off state.

  In the power semiconductor device according to the present embodiment, the impurity concentration of second cathode emitter region 15 is lower than the impurity concentration required to turn off gate region 16 and cathode region 12, which is the breakdown voltage. That is, both the thickness and the impurity concentration of the second cathode emitter region 15 can be optimized, and as a result, a high breakdown voltage between the gate region 16 and the cathode region 12 can be realized.

  Further, in the power semiconductor device according to the present embodiment, the impurity concentration of first cathode emitter region 14 is higher than the impurity concentration of auto-doping from gate region 16. That is, both the film thickness and the concentration of the first cathode emitter region 14 can be optimized. As a result, the distance between the gate region 16 and the cathode region 12 is smaller than the thickness of the second cathode emitter region 15 and the first cathode emitter region 14. Therefore, a reduction in capacitance between the gate region 16 and the cathode region 12 can be realized. As a result, high-speed turn-off performance can be obtained.

  In the power semiconductor device having the SG structure to which the present technology is applied, high-speed turn-on performance can be obtained by high carrier injection from the cathode region. Further, it is possible to reduce the on-resistance in the conductive state and realize high withstand voltage and high-speed switching performance while sufficiently securing the gate withstand voltage. Further, a power semiconductor device having normally-off characteristics, semi-normally-off characteristics, and normally-on characteristics in forward characteristics can be easily realized.

(Epitaxial growth layer requirements)
In the power semiconductor device according to the embodiment to which the present technology is applied, the cathode emitter regions (14, 15) having a relatively low concentration are formed as a two-layer epitaxial growth structure. That is, it has a two-layer structure of a first cathode emitter region 14 having a first epitaxial layer and a second cathode emitter region 15 having a second epitaxial layer. The n-type impurity concentration of the first epitaxial layer and the second epitaxial growth layer has a range of, for example, about 1 × 10 ¹³ (cm ⁻³ ) to 1 × 10 ¹⁸ (cm ⁻³ ).

-Requirements for the first epitaxial layer-
The first cathode emitter region 14 including the first epitaxial layer is set to a high concentration such that it does not invert to the p-type by auto doping from the p ⁺ gate region 16, but the capacitance between the gate and the emitter is reduced (at the time of turn-off). Therefore, it is desirable to set the density as low as possible.

  In addition, since the first cathode emitter region 14 is formed using an epitaxial growth technique with a constant impurity concentration, it is possible to simplify the manufacturing method and stabilize the impurity concentration by monitor management.

As a result, a stable channel width can be secured between adjacent p ⁺ gate regions 16. In addition, by reducing the capacitance between the gate region 16 and the cathode region 12, high-speed turn-off performance can be achieved. Further, it is possible to reduce the concentration (i-layer) between adjacent p ⁺ gate regions 16 to such an extent that normally-off is realized.

  In addition, since the first cathode emitter region 14 is formed by using the epitaxial growth technique with a constant impurity concentration, the manufacturing method can be simplified and stabilized.

The first cathode emitter region 14 including the first epitaxial layer is preferably set to a thickness such that the auto doping from the p ⁺ gate region 16 is 1 × 10 ¹⁴ (cm ⁻³ ) or less. If the concentration of the autodoping falls within this level, the influence on the setting of the impurity concentration of the first cathode emitter region 14 including the second epitaxial layer can be suppressed. Here, the thickness of the first cathode emitter region 14 has a range of, for example, about 0.5 μm to 1.5 μm.

Further, since the impurity concentration of the second cathode emitter region 15 having the second epitaxial layer formed on the first cathode emitter region 14 having the first epitaxial layer is controlled by the epitaxial growth technique, the impurity concentration can be stabilized. However, since the p ⁺ gate region 16 actually spreads due to thermal diffusion during the formation of the first epitaxial growth layer and the second epitaxial layer, the distance between the p ⁺ gate regions 16 and the The thickness and impurity concentration of the first epitaxial growth layer and the thickness and impurity concentration of the second epitaxial growth layer are set.

  The first cathode emitter region 14 is preferably formed in a single step by epitaxial growth with a constant impurity concentration, but may be formed by a plurality of epitaxial growths with a stepwise impurity concentration.

-Requirements for the second epitaxial layer-
The second cathode emitter region 15 including the second epitaxial layer is set to a low concentration such that when turned off, a withstand voltage based on a necessary depletion layer width between the p ⁺ gate region 16 and the cathode region 12 is obtained. In order to reduce the resistance at the time of turn-on, it is desirable to set the concentration as high as possible.

  As a result, the second cathode emitter region 15 can contribute to a large driving current due to a low resistance at the time of turn-on.

In addition, since the second cathode emitter region 15 is formed using an epitaxial growth technique with a constant impurity concentration, the manufacturing method can be simplified and the impurity concentration can be stabilized by monitoring and managing. When a sufficient reverse bias (for example, about -1 V to -20 V) is applied to turn off the gate-cathode voltage, a depletion layer spreading between the p ⁺ gate region 16 and the cathode region 12 becomes an upper layer. It is preferable to set the film thickness as thin as possible so as not to contact the cathode region 12 in the above. Here, the impurity concentration of the cathode region 12 is, for example, about 1 × 10 ²⁰ (cm ⁻³ ) or more, and the impurity concentration of the second cathode emitter region 15 is, for example, about 1 × 10 ¹⁸ (cm ⁻³ ). As described above, the thickness of the second cathode emitter region 15 may have a range of, for example, about 1.0 μm to 3.0 μm. Actually, there is also diffusion from the n ⁺ layer having a high impurity concentration from the cathode region 12 due to thermal diffusion. Therefore, taking this diffusion depth into consideration, the film thickness / impurity concentration of the second epitaxial layer and the impurity concentration of the cathode region 12・ Set the diffusion depth.

  The second cathode emitter region 15 is preferably formed by a single step of epitaxial growth with a constant impurity concentration, but may be formed by a plurality of epitaxial growths having a stepwise impurity concentration.

A schematic explanatory diagram near the gate of the power semiconductor device according to the present embodiment is represented as shown in FIG. That is, as shown in FIG. 5, X _G axis, the cathode region 12 through the cathode emitter region (15, 14) gate regions 16, shows a straight line leading to the high-resistance layer 18. On the other hand, the X _C axis indicates a straight line extending from the cathode region 12 to the high resistance layer 18 through the center of the channel region 13.

In FIG. 5, X _K represents the junction depth of cathode region 12, and X _Gi represents the distance from the surface of cathode region 12 to the center of channel region 13. The value of X _Gi is substantially equal to the distance from the surface of the cathode region 12 to the center of the gate region 16.

In FIG. 5, X _E is equal to the distance from the surface of cathode region 12 to the interface between second cathode emitter region 15 and first cathode emitter region 14.

(Impurity concentration profile when auto-doping concentration is high)
FIG. 6 shows an impurity concentration profile near the gate along the X _C axis when the auto-doping concentration is high. In FIG. 6, N _K represents the impurity concentration of the cathode region 12. N ₁ represents the impurity concentration of the first cathode emitter region 14 including the first epitaxial layer. N ₂ represents the impurity concentration of the second cathode emitter region 15 including the second epitaxial layer. N _i represents the impurity concentration of the high resistance layer 18. Curve PA represents the autodoping concentration profile from gate region 16 into the first epitaxial layer (first cathode emitter region 14) when the autodoping concentration is high. A curve NP represents an impurity concentration profile as a total of the n-type impurity concentration profile and the p-type impurity concentration profile when the auto-doping concentration is high. As shown in FIG. 6, when the autodoping concentration is high, the impurity concentration N ₁ of the first epitaxial layer (first cathode emitter region 14) depends on the impurity concentration of the second epitaxial layer (second cathode emitter region 15). equal to N _2, or dark is set.

(Impurity profile when autodoping is thin)
Impurity concentration profile near the gate along the X _C axis when auto-doping concentration is thin, is expressed as shown in FIG. Similarly, in FIG. 7, N _K represents the impurity concentration of the cathode region 12. N ₁ represents the impurity concentration of the first epitaxial layer (first cathode emitter region 14). N ₂ represents the impurity concentration of the second epitaxial layer (second cathode emitter region 15). N _i represents the impurity concentration of the high resistance layer 18. Curve PA represents the autodoping concentration profile from gate region 16 into the first epitaxial layer (first cathode emitter region 14) when the autodoping concentration is low. A curve NP represents an impurity concentration profile as a total of the n-type impurity concentration profile and the p-type impurity concentration profile when the auto-doping concentration is low. As shown in FIG. 7, when the auto-doping concentration is thin, the impurity concentration N ₁ of the first epitaxial layer (first cathode emitter region 14), the impurity concentration of the second epitaxial layer (second cathode emitter region 15) equal to N _2, or thin set.

(Impurity concentration profile of gate)
Impurity concentration profile near the gate along the X _G axis gate portion is expressed as shown in FIG. FIG. 8 shows a case where the auto dope is deep as an example. The case where the auto dope is thin can be similarly expressed. Similarly, in FIG. 8, N _K represents the impurity concentration of the cathode region 12. N ₁ represents the impurity concentration of the first epitaxial layer (first cathode emitter region 14). N ₂ represents the impurity concentration of the second epitaxial layer (second cathode emitter region 15). N _i represents the impurity concentration of the high resistance layer 18. A curve PG represents an impurity concentration profile of the gate region 16 when the autodoping concentration is high. As shown in FIG. 8, the impurity concentration profile of the gate region 16 has both a diffusion concentration profile into the first epitaxial layer (first cathode emitter region 14) and a diffusion concentration profile into the high resistance layer 18. Is shown. A curve NP represents an impurity concentration profile as a total of the n-type impurity concentration profile and the p-type impurity concentration profile when the auto-doping concentration is high.

(Turn-on operation simulation)
In the power semiconductor device according to the present embodiment, the turn-on operation simulation shows that the anode-cathode voltage V _AK = 5000 V and the anode current density I _A = 5000 _A / cm ² can be turned on at high speed in about 100 ns. Have been.

(Forward yield characteristics)
In the power semiconductor device according to the present embodiment, in the operation simulation result of the forward breakdown characteristic, the voltage between the anode and the cathode (withstand voltage) can be held up to about 6000 V, and the turnover characteristic is obtained at about 6800 V. .

(Production method)
In the method for manufacturing a power semiconductor device according to the present embodiment, after forming gate region 16 for high-resistance layer 18, first epitaxial layer is formed on high-resistance layer 18 and gate region 16 so as to bury gate region 16. The first cathode emitter region 14 is provided. In the manufacturing process for burying the gate region 16, a gate diffusion impurity and an impurity control method of the first epitaxial growth are used. Further, after the first cathode emitter region 14 is formed by the first epitaxial growth, the second cathode emitter region 15 is formed on the first cathode emitter region 14 by the second epitaxial growth. Further, the cathode region 12 is formed for the second cathode emitter region 15.

  In the method for manufacturing a power semiconductor device according to an embodiment to which the present technology is applied, a gate patterning step is represented as shown in FIG. 9A, and a gate diffusion step is shown in FIG. 9B. The formation process of the first epitaxial layer is expressed as shown in FIG. 9C, and the formation process of the second epitaxial layer is expressed as shown in FIG. 9D.

  (A) First, as shown in FIG. 9A, after an insulating layer 44 is formed on the high-resistance layer 18, the insulating layer 44 is patterned to form an opening window for gate diffusion.

(B) Next, as shown in FIG. 9B, a gate region 16P is formed in the patterned opening window by using a diffusion technique. As the impurity, for example, boron (B) is applied. The surface impurity concentration of the gate region 16P has a range of, for example, about 1 × 10 ²⁰ (cm ⁻³ ) to 10 ²² (cm ⁻³ ).

  (C) Next, as shown in FIG. 9C, after removing the insulating layer 44, a first epitaxial growth (growth temperature of about 1000 ° C.) is performed on the exposed surfaces of the high-resistance layer 18 and the gate region 16P by the first epitaxial growth. The cathode emitter region 14 is formed. In the first epitaxial growth, the first cathode emitter region 14 is formed by adding, for example, phosphorus (P) as an impurity while compensating for auto-doping due to vaporization of boron from the gate region 16P. As a result, a gate region 16D is formed in the first cathode emitter region 14 by diffusion from the gate region 16P, and the gate region 16 (16P, 16D) is formed in the high resistance layer 18 and the first cathode emitter region 14. It is buried and formed.

  Here, the impurity concentration (phosphorus) of the first cathode emitter region 14 is set to be higher than the impurity concentration (boron) that is auto-doped from the gate region 16P to the first cathode emitter region 14.

  (D) Next, as shown in FIG. 9D, a second cathode emitter region 15 is further formed on the first cathode emitter region 14 by second epitaxial growth. In the second epitaxial growth, for example, phosphorus (P) is added as an impurity.

  Here, the impurity concentration of the second cathode emitter region 15 is set to be lower than the impurity concentration required for turning off the gate region 16 and the cathode region 12 so as to withstand voltage.

  Further, although not shown, after forming the cathode region 12 on the surface of the second cathode emitter region 15, the bevel region 34 is formed, and the cathode electrode 10 and the anode electrode 24 are formed. Note that the buffer region 20 and the anode region 22 may be formed at a timing before and after the formation of the cathode region 12 after the formation of the second cathode emitter region 15.

(Double gate structure)
The power semiconductor device 1 shown in FIG. 10 has an electrostatic induction thyristor structure having a double gate (DG) structure.

  As shown in FIG. 10, a power semiconductor device 1 according to an embodiment to which the present technology is applied has a cathode region 12 and a first channel region 13 through which first conductivity type carriers injected from the cathode region 12 can conduct. A first gate region 16 capable of controlling the potential of the first channel region 13 by the electrostatic induction field effect; and a first gate region 16 disposed between the cathode region 12 and the first gate region 16 and the first channel region 13. A cathode emitter region (14, 15) having a cathode emitter region 14 and a second cathode emitter region 15, an anode region 22, and a second conductivity type carrier of a conductivity type opposite to the first conductivity type injected from the anode region 22; A second channel region 33 that can conduct electricity, a second gate region 28 that can control the potential of the second channel region 33 by the electrostatic induction field effect, An anode emitter region (30, 31) disposed between the gate region 22 and the second gate region 28 and the second channel region 33 and having at least a first anode emitter region 30 and a second anode emitter region 31. .

  Here, the impurity concentration of the first conductivity type of the first cathode emitter region 14 is set higher than the impurity concentration of the second conductivity type which is auto-doped from the first gate region 16. Further, the impurity concentration of the first conductivity type of the second cathode emitter region 15 is set to be lower than the impurity concentration of the first conductivity type required for the turn-off state, which is the withstand voltage between the first gate region 16 and the cathode region 12.

  In addition, the second conductive type impurity concentration of the first anode emitter region 30 is set to be higher than the first conductive type impurity concentration that is auto-doped from the second gate region 28. Further, the impurity concentration of the second conductivity type of the second anode emitter region 31 is set to be lower than the impurity concentration of the second conductivity type required for the turn-off state, which is the withstand voltage between the second gate region 28 and the anode region 22.

  The cathode emitter regions (14, 15) were epitaxially grown with at least two levels of impurity concentration.

  The first cathode emitter region 14 includes a first epitaxial layer, and the second cathode emitter region 15 includes a second epitaxial layer.

  The first epitaxial layer grows at the first stage, and the second epitaxial layer grows at the second stage.

The first epitaxial layer has a thickness such that the autodoping concentration from the first gate region 16 to the first epitaxial layer is 1 × 10 ¹⁴ (cm ⁻³ ) or less.

  When the second epitaxial layer is turned off by applying a reverse bias voltage between the first gate region 16 and the cathode region 12, a depletion layer spreading around the first gate region 16 does not reach the cathode region 12. With thickness.

  The anode emitter regions (30, 31) were epitaxially grown with at least two levels of impurity concentration.

  The first anode emitter region 30 includes a third epitaxial layer, and the second anode emitter region 31 includes a fourth epitaxial layer.

  The third epitaxial layer grows at the third stage, and the fourth epitaxial layer grows at the fourth stage.

The third epitaxial layer has a thickness such that the auto-doping concentration from the second gate region 28 to the third epitaxial layer is 1 × 10 ¹⁴ (cm ⁻³ ) or less.

  The fourth epitaxial layer is a film in which when a reverse bias voltage is applied between the second gate region 28 and the anode region 22 to be turned off, a depletion layer spreading around the second gate region 28 does not reach the anode region 22. With thickness.

  Cathode region 12 is formed of an n-type semiconductor and functions as a first carrier injection region.

  The first conductivity type carriers correspond to electrons.

  The first gate region 16 is formed of a p-type semiconductor and functions as a main current control region.

  The first channel region 13 is sandwiched between adjacent first gate regions 16 and functions as a region in which conduction of a main current can be controlled.

  The cathode emitter regions (14, 15) are arranged between the cathode region 12 and the gate region 16, and convert the first conductivity type carriers injected from the cathode region 12 from the cathode region 12 to the channel region 13 to improve the efficiency. A region capable of securing sufficient withstand voltage when applying a reverse bias voltage between the gate region 16 and the cathode region 12 to turn off while appropriately diffusing and appropriately suppressing auto doping from the gate region 16. Function as

  The anode region 22 is formed of a p-type semiconductor and functions as an anode of a DG static induction thyristor.

  The second conductivity type carriers correspond to holes.

  The second gate region 28 is formed of an n-type semiconductor and functions as a main current control region.

  The second channel region 33 is sandwiched between the adjacent second gate regions 28 and functions as a region in which conduction of a main current can be controlled.

  The anode emitter regions (30, 31) are disposed between the anode region 22 and the gate region 28, and transfer the second conductivity type carriers injected from the anode region 22 from the anode region 22 to the channel region 33 to improve the efficiency. A region capable of securing sufficient withstand voltage when applying a reverse bias voltage between the gate region 28 and the anode region 22 to turn off while appropriately diffusing and appropriately suppressing auto doping from the gate region 28. Function as

  The high-resistance layer 18 is formed of a high-resistance n-type semiconductor or a p-type semiconductor that can ensure a high breakdown voltage between the anode and the cathode and between the first gate and the second gate.

  Further, as shown in FIG. 10, a cathode electrode 10 disposed on the cathode region 12, a first gate electrode 26 disposed on the first gate region 16, and an anode electrode 24 disposed on the anode region 22. And a second gate electrode 32 disposed on the second gate region 28.

  The power semiconductor device 1 shown in FIG. 10 includes a plurality of cathode electrodes 10 (cathode regions 12) divided into segments, as in FIG. In each cathode segment unit, a multi-channel structure including a plurality of channel regions 13 sandwiched between adjacent first gate regions 16 and capable of controlling conduction of a main current is formed.

  Similarly, the power semiconductor device 1 shown in FIG. 10 includes a plurality of anode electrodes 24 (anode regions 22) divided into segment units. In each anode segment unit, a multi-channel structure including a plurality of channel regions 33 sandwiched between adjacent second gate regions 28 and capable of controlling conduction of a main current is formed.

  As shown in FIG. 10, the first gate region 16 and the second gate region 28 are shown as having a pn junction gate structure, but may have other gate structures. For example, a Schottky gate structure, an insulated gate structure, a heterojunction gate structure, or the like may be provided.

  Further, the forward characteristics of the power semiconductor device 1 shown in FIG. 10 may include any of a normally-off characteristic, a semi-normally-off characteristic, and a normally-on characteristic.

  Further, as shown in FIG. 10, a bevel region 34 is provided around each cathode segment between the cathode electrode 10 and the first gate electrode 26, and a sufficient withstand voltage is provided between the first gate terminal G1 and the cathode terminal K. Can be secured. Similarly, a bevel region 36 is provided around each anode segment between the anode electrode 24 and the second gate electrode 32, and a sufficient breakdown voltage can be secured between the anode terminal A and the second gate terminal G2. Although the bevel region 36 is formed around each anode segment between the anode electrode 24 and the second gate electrode 32, other structures may be adopted. For example, the bevel region 36 may be formed between the cathode electrode 10 and the second gate electrode 32.

  Here, a sufficient withstand voltage that can be secured between the anode terminal A and the second gate terminal G2 means that the forward characteristic can be any of a normally-off characteristic, a semi-normally-off characteristic, or a normally-on characteristic, and a gate of the main current. It refers to the withstand voltage level that can be turned off.

  A power semiconductor device having a DG structure to which the present technology is applied can obtain high-speed turn-on performance by high carrier injection from a cathode emitter region and an anode emitter region.

  A power semiconductor device having a DG structure to which the present technology is applied can reduce on-resistance in a conductive state and realize high withstand voltage and high-speed switching performance while sufficiently securing a gate withstand voltage. In addition, the power semiconductor device having the DG structure to which the present technology is applied can easily realize a power semiconductor device having each of a normally-off characteristic, a semi-normally-off characteristic, and a normally-on characteristic in a forward characteristic.

  The power semiconductor device 1 according to one embodiment to which the present technology is applied uses an epitaxial layer having a constant concentration.

  A power semiconductor device 1 according to an embodiment to which the present technology is applied uses a first epitaxial layer and a second epitaxial layer, and a third epitaxial layer and a fourth epitaxial layer. Therefore, monitor management during the manufacturing process is easy. In addition, it is easy to increase the concentration with high accuracy on a hardware surface such as a mass flow controller. In addition, auto-doping from the gate regions 16 and 28 to the first and third epitaxial layers can be stably compensated.

  Therefore, the first-stage first epitaxial layer exhibits a desirable gradient concentration distribution including auto-doping, and the second-stage second epitaxial layer can be optimized in both film thickness and concentration. In addition, the third epitaxial layer in the third stage also exhibits a desirable gradient concentration distribution including autodoping, and the fourth epitaxial layer in the fourth stage can be optimized in both film thickness and concentration.

  The power semiconductor device according to the present embodiment is not limited to SGSIThy and DGSIThy, and can be similarly applied to SIT. In this case, the present invention can be similarly applied to the n-channel SITT and the p-channel SIT.

  Further, the power semiconductor device according to the present embodiment is formed using at least one or a plurality of materials selected from the group consisting of a group IV element semiconductor, a group III-V compound semiconductor, and a group II-VI compound semiconductor. May be.

  Further, the power semiconductor device according to the present embodiment may be formed using at least one or a plurality of materials selected from the group consisting of silicon carbide, gallium nitride, silicon, aluminum nitride, and gallium oxide.

  The power semiconductor device according to the present embodiment has at least one or a plurality of types of SIT or SI thyristors selected from the group consisting of SiC, Si, GaN, AlN, and gallium oxide. Is also good.

  Further, the power semiconductor device according to the present embodiment may include at least one selected from the group consisting of a pn junction gate structure, a Schottky gate structure, an insulated gate structure, and a hetero junction gate structure.

  Further, the power semiconductor device according to an embodiment to which the present technology is applied may have a module configuration for a pulse power supply.

[Other embodiments]
While the embodiments have been described above, the discussion and drawings that form a part of the disclosure are illustrative and should not be construed as limiting. From this disclosure, various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art.

  As described above, this embodiment includes various embodiments and the like not described herein.

  The power semiconductor device of the present embodiment can be used for various power semiconductor devices such as Si, SiC, GaN, AlN, and gallium oxide, and is applicable to a wide range of application fields such as a pulse power supply and an inverter circuit.

DESCRIPTION OF SYMBOLS 1 ... Power semiconductor device 10 ... Cathode electrode 12 ... Cathode region 13, 33 ... Channel region 14 ... First cathode emitter region 15 ... Second cathode emitter region 16, 28 ... Gate region 18 ... High resistance layer 20 ... Buffer region 22 ... Anode region 24 Anode electrodes 26 and 32 Gate electrode 30 First anode emitter region 31 Second anode emitter regions 34 and 36 Bevel regions G, G1, G2 Gate terminal A Anode terminal K Cathode terminal

Claims (8)

A cathode region;
A channel region through which carriers injected from the cathode region can conduct,
A gate region sandwiching the channel region, the gate region being capable of controlling the potential of the channel region by an electrostatic induction electric field effect;
A first cathode emitter region disposed above the channel region and the gate region;
A second cathode emitter region disposed between the first cathode emitter region and the cathode region;
A first conductive type impurity concentration of the first cathode emitter region is higher than a second conductive type impurity concentration that is auto-doped from the gate region;
The power semiconductor device according to claim 1, wherein a concentration of the first conductivity type impurity in the second cathode emitter region is lower than a concentration of the first conductivity type impurity required for a turn-off state between the gate region and the cathode region. The first cathode emitter region includes a first epitaxial layer grown at a first constant impurity concentration;
2. The power semiconductor device according to claim 1, wherein said second cathode emitter region includes a second epitaxial layer grown at a second constant impurity concentration. 3. The power semiconductor device according to claim 2, wherein the first epitaxial layer has a thickness such that an auto-doping concentration from the gate region to the first epitaxial layer is 1 × 10 ¹⁴ (cm ⁻³ ) or less. 4.   The second epitaxial layer has a thickness such that a depletion layer extending around the gate region does not reach the cathode region when a reverse bias voltage is applied between the gate region and the cathode region to turn off the gate region. The power semiconductor device according to claim 2. An anode region having a conductivity type opposite to that of the cathode region,
A buffer region for controlling a second conductivity type carrier of a conductivity type opposite to the first conductivity type injected from the anode region;
The power semiconductor device according to claim 1, further comprising: a high resistance layer disposed between the buffer region, the gate region, and the channel region.   The power semiconductor device according to claim 1, wherein the forward characteristic includes at least one type selected from a group of a normally-off characteristic, a semi-normally-off characteristic, and a normally-on characteristic.   The power semiconductor device according to claim 1, comprising at least one or more materials selected from the group consisting of silicon carbide, gallium nitride, silicon, aluminum nitride, and gallium oxide. After forming an insulating layer on the high resistance layer, a step of patterning,
Forming a gate region for the patterned opening window;
Forming a first epitaxial layer on the exposed surface of the high resistance layer after removing the insulating layer;
Forming a second epitaxial layer further on the first epitaxial layer;
Forming a cathode region on the surface of the second epitaxial layer;
A first conductivity type impurity concentration of the first epitaxial layer is higher than a second conductivity type impurity concentration which is auto-doped from the gate region to the first epitaxial layer;
The method of manufacturing a power semiconductor device, wherein the first conductive type impurity concentration of the second epitaxial layer is lower than the first conductive type impurity concentration required for a turn-off state between the gate region and the cathode region.

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