JPS604218A - Coating method of resist material on semiconductor wafer - Google Patents
Coating method of resist material on semiconductor waferInfo
- Publication number
- JPS604218A JPS604218A JP11305683A JP11305683A JPS604218A JP S604218 A JPS604218 A JP S604218A JP 11305683 A JP11305683 A JP 11305683A JP 11305683 A JP11305683 A JP 11305683A JP S604218 A JPS604218 A JP S604218A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor wafer
- resist material
- chamber
- resist
- atmosphere
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/16—Coating processes; Apparatus therefor
- G03F7/167—Coating processes; Apparatus therefor from the gas phase, by plasma deposition
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Plasma & Fusion (AREA)
- General Physics & Mathematics (AREA)
- Application Of Or Painting With Fluid Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は半導体ウェーハ上にパターンを形成するため
に用いるレジスト材の塗布方法の改良に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement in a method for applying a resist material used to form a pattern on a semiconductor wafer.
第1図は従来の塗布装置の一例を示す正面図で、fi+
は半導体ウェーハ(2)を真空吸着してこれを回転させ
る真空チャック、(3)は半導体ウェーハ(2)の上ニ
レジスト材を滴下するためのノズル、(4)はノズル(
3)から滴下されるレジスト材である。FIG. 1 is a front view showing an example of a conventional coating device.
(3) is a nozzle for dropping resist material onto the semiconductor wafer (2); (4) is a nozzle (
3) is the resist material dropped from step 3).
この従来装置による塗布方法では、半導体ウェーハ(2
)を真空チャックil+の上に載せ、真空吸着する。そ
して、半導体ウェーハ(2)の上にノズル(3)から導
かれたレジスト材(4)を破線矢印で示すように滴下す
る。適量滴下した後、所望膜厚を得る回転数で半導体ウ
ェーハ(2)を回転させて塗布する。In this coating method using conventional equipment, semiconductor wafers (2
) is placed on the vacuum chuck il+ and vacuum-adsorbed. Then, the resist material (4) guided from the nozzle (3) is dropped onto the semiconductor wafer (2) as shown by the broken line arrow. After dropping an appropriate amount, the semiconductor wafer (2) is rotated at a rotation speed to obtain the desired film thickness.
しかし、この従来の方法では、膜厚が小さくなるに従っ
て面内での膜厚の均一性が悪くなり、ピンホールなどの
欠陥か発生ずるおそれかあった。However, in this conventional method, as the film thickness becomes smaller, the uniformity of the film thickness within the surface deteriorates, and there is a risk that defects such as pinholes may occur.
この発明は以上のような点に鑑みてなされたもので、レ
ジスト材を真空中で気化し、その気化状態の雰囲気中に
半導体ウェーハを置くことによって、膜厚が小さく、ウ
ェーハ表面内で均一性がよく欠陥の発生密度が小さくな
るようなレジスト材の塗布方法を提供するものである。This invention was made in view of the above points. By vaporizing the resist material in a vacuum and placing the semiconductor wafer in the vaporized atmosphere, the film thickness is small and the film is uniform on the wafer surface. The purpose of the present invention is to provide a method for applying a resist material that has a high defect density and a low defect density.
第2図はこの発明の実施状況の一例を示す断面図で、(
6)はチャンバー、(6)は半導体ウェーハ(2)を図
示のように保持するウェーハガイド、(7)はチャンバ
ー(5)内を真空にするための排気口、(8)は真空に
されたチャンバー(5)内に破線矢印で示すようにレジ
スト114rを注入するためのレジスト注入口、(9)
は半導体ウェーハ(2)へ板本するレジスト膜の膜厚を
制御するためのシャッターである。FIG. 2 is a sectional view showing an example of the implementation status of this invention.
6) is a chamber, (6) is a wafer guide that holds the semiconductor wafer (2) as shown, (7) is an exhaust port for evacuating the chamber (5), and (8) is a vacuum chamber. a resist injection port (9) for injecting the resist 114r into the chamber (5) as shown by the dashed arrow;
is a shutter for controlling the thickness of the resist film applied to the semiconductor wafer (2).
この実施例の方法では、ウェーハガイド(6)に保持さ
れた半導体ウェーハ(2)をチャンバー(5)内の図示
の位置に配置する。次いで、排気口(7)からチャンバ
ー(5)内を排気する。チャンバー(5)内の圧力が適
圧になった後に、レジスト注入口(8)から破線矢印に
示すようにレジスト材(4)を注入する。注入されたレ
ジスト材(4)は気化して、チャンバー(5)内がその
気化状態の雰囲気となる。そして、その雰囲気のチャン
バー(5)内に配置された半導体ウェーハ(2)にはレ
ジスト材(4)が付着する。チャンバー(5)が極端に
小さい場合はともかく、適当な大きさを有するものであ
れば、気化レジスト雰囲気の均一性は良好であるので、
ウェーハ(2;上の付着の面内均一性は膜厚の大小を問
わずすぐれたものとなる。In the method of this embodiment, a semiconductor wafer (2) held by a wafer guide (6) is placed at the position shown in the chamber (5). Next, the inside of the chamber (5) is evacuated from the exhaust port (7). After the pressure in the chamber (5) reaches a suitable level, the resist material (4) is injected from the resist injection port (8) as shown by the broken line arrow. The injected resist material (4) is vaporized, and the inside of the chamber (5) becomes an atmosphere in the vaporized state. Then, a resist material (4) is attached to the semiconductor wafer (2) placed in the chamber (5) in that atmosphere. Even if the chamber (5) is extremely small, if it has an appropriate size, the uniformity of the vaporized resist atmosphere will be good.
The in-plane uniformity of the deposition on the wafer (2) is excellent regardless of the film thickness.
また、レジスト材(4)も気化状態のものを用いるので
、ピンホールなどの欠陥の発生密度をきわめて小さくで
きる。次に、膜厚のコントロールは、チャンバー f5
i内に設置されたシャッター(9)の開閉によって容易
に行うことができる。勿論、この発明の方法ではレジス
ト材としては気化しても成分分離の生じないものを用い
る必要がある。Furthermore, since the resist material (4) is also in a vaporized state, the density of defects such as pinholes can be extremely reduced. Next, the film thickness is controlled using chamber f5.
This can be easily done by opening and closing the shutter (9) installed inside i. Of course, in the method of the present invention, it is necessary to use a resist material that does not cause component separation even when vaporized.
なお、上記実施例では半導体ウェハー1枚の場合を示し
たが、多数枚同時に収容処理するようにしてもよい。ま
た、上記実用例では真空状態を作るために普通のチャン
バーを用いたが、真空状態になし得るものならばどんな
ものでもよく、例えばクリーンオーブンのようなもので
もよく、この場合は塗布完了後、雰囲気を変化させて連
続的にプリベークをも行なうことができる。In addition, although the case of one semiconductor wafer was shown in the above embodiment, a large number of semiconductor wafers may be accommodated and processed at the same time. In addition, in the above practical example, an ordinary chamber was used to create a vacuum state, but any device that can create a vacuum state may be used, such as a clean oven. In this case, after coating is completed, Prebaking can also be performed continuously by changing the atmosphere.
以上説明したように、この発明ではレジスト材を気化さ
せた雰囲気中に半導体ウェーハを置き、この半導体ウェ
ーハ表面にレジスト利を被着させるようにしたので、膜
厚の均一なビンポールなどの欠陥の発生密度の小さいレ
ジスト膜が得られる。As explained above, in this invention, the semiconductor wafer is placed in an atmosphere in which the resist material is vaporized, and the resist film is deposited on the surface of the semiconductor wafer. A resist film with low density is obtained.
第1図は従来の塗布装置の一例を示す正面図。
第2図はこの発明の実施状況の一例を示す断面図である
。
図において、(2)は半導体ウェーハ、(4)はレジス
ト材、(5)はチャンバー、(6)はウェーハガイド、
(7)は排気口、(8)はレジスト注入口である。
なお、図中同一符号は同−寸たけ相当部分を示す。
代理人 大岩増雄
第1図
第2図
2FIG. 1 is a front view showing an example of a conventional coating device. FIG. 2 is a sectional view showing an example of the state of implementation of the present invention. In the figure, (2) is a semiconductor wafer, (4) is a resist material, (5) is a chamber, (6) is a wafer guide,
(7) is an exhaust port, and (8) is a resist injection port. In addition, the same reference numerals in the figures indicate parts corresponding to the same dimensions. Agent Masuo Oiwa Figure 1 Figure 2 Figure 2
Claims (2)
後にレジスト材を注入気化させることによって、上記レ
ジスト材を上記半導体ウェーハ上に上記レジスト材を被
着させることを特徴とする半導体ウェーハへのレジスト
材の塗布方法。(1) A resist for a semiconductor wafer, characterized in that the resist material is deposited on the semiconductor wafer by injecting and vaporizing the resist material after evacuating the inside of a container containing the semiconductor wafer. How to apply the material.
ターを設けこのシャッターの開閉によって被着レジスト
材の膜厚を制御することを特徴とする特許請求の範囲第
1項記載の半導体ウェーハへのレジスト材の塗布方法。(2) A method for semiconductor wafers according to claim 1, characterized in that a shutter is provided opposite the surface of the semiconductor wafer in the container, and the film thickness of the deposited resist material is controlled by opening and closing the shutter. How to apply resist material.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11305683A JPS604218A (en) | 1983-06-21 | 1983-06-21 | Coating method of resist material on semiconductor wafer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11305683A JPS604218A (en) | 1983-06-21 | 1983-06-21 | Coating method of resist material on semiconductor wafer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS604218A true JPS604218A (en) | 1985-01-10 |
Family
ID=14602377
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11305683A Pending JPS604218A (en) | 1983-06-21 | 1983-06-21 | Coating method of resist material on semiconductor wafer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS604218A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63240551A (en) * | 1987-03-27 | 1988-10-06 | Res Dev Corp Of Japan | Thin organic film resist and perfect dry lithography |
-
1983
- 1983-06-21 JP JP11305683A patent/JPS604218A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63240551A (en) * | 1987-03-27 | 1988-10-06 | Res Dev Corp Of Japan | Thin organic film resist and perfect dry lithography |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4533624A (en) | Method of forming a low temperature multilayer photoresist lift-off pattern | |
US4405710A (en) | Ion beam exposure of (g-Gex -Se1-x) inorganic resists | |
JPH1070071A (en) | Coater having controllable compression chamber for semiconductor processing | |
US3934060A (en) | Method for forming a deposited silicon dioxide layer on a semiconductor wafer | |
JPH0358530B2 (en) | ||
US4842989A (en) | Resist layer and process for forming resist pattern thereon | |
CA1093216A (en) | Silicon device with uniformly thick polysilicon | |
JPS604218A (en) | Coating method of resist material on semiconductor wafer | |
JPH04336426A (en) | Manufacture of semiconductor device | |
JPS63119531A (en) | Photoresist coater in manufacture of semiconductor | |
JP3224548B2 (en) | Apparatus and method for minimizing deposition stress of tungsten silicide film | |
JPH06275533A (en) | Vertical cvd device | |
JPH02119226A (en) | Spin coating of organic solution | |
KR19990073223A (en) | Thin film deposition system and process for fabrication of organic light-emitting devices | |
JPS591385B2 (en) | Spin coating method and device | |
JPH04314863A (en) | Plasma reaction device | |
JPS6228461B2 (en) | ||
JPS6235264B2 (en) | ||
JPS5769737A (en) | Coating method and device for resist on both side surfaces of wafer | |
JPS63160223A (en) | Resist coating apparatus | |
JPH04113615A (en) | Manufacture of semiconductor device | |
JPH01111351A (en) | Processing method | |
KR100366367B1 (en) | Photoresist coating apparatus and method for forming photoresist film using the same | |
JPH076944A (en) | Chemical treatment and device | |
JPS5952526A (en) | Method for sputtering metal oxide film |