JPS6041863B2 - Package for semiconductor devices - Google Patents
Package for semiconductor devicesInfo
- Publication number
- JPS6041863B2 JPS6041863B2 JP5974980A JP5974980A JPS6041863B2 JP S6041863 B2 JPS6041863 B2 JP S6041863B2 JP 5974980 A JP5974980 A JP 5974980A JP 5974980 A JP5974980 A JP 5974980A JP S6041863 B2 JPS6041863 B2 JP S6041863B2
- Authority
- JP
- Japan
- Prior art keywords
- frame
- semiconductor device
- package body
- package
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、外形寸法を標準化した主パッケージ本体と
、この主パッケージ本体の半導体装置マウント部に、半
導体装置の種類に応じて最少限の変更可能な要素をもつ
枠状部材を嵌入させて一体化したパッケージ本体を備え
た半導体装置用パッケージに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a main package body with standardized external dimensions, and a frame-shaped semiconductor device mounting portion of the main package body that has a minimum number of elements that can be changed depending on the type of semiconductor device. The present invention relates to a semiconductor device package including a package body into which members are fitted and integrated.
半導体装置用パッケージの価格は、材料面からみると
セラミックパッケージ、次いでサーデツプであり、モー
ルドタイプが最も安価である。In terms of materials, ceramic packages are the second most expensive packages for semiconductor devices, followed by ceramic packages, with the mold type being the cheapest.
それはまた、パッケージの構造の複雑さに比例する一面
を持つており、構造面からは積層構造の気密封止型パッ
ケージが最も高価である。しかしながら、積層構造の気
密封止型パッケージが最も信頼性が高い。 このように
、積層構造に限らず気密封止型のパッケージは一般的に
高価であり、何んらかの合理化、例えば外形諸寸法を統
一化した標準的な構造として大量生産を促し、価格を下
げることが望まれている。It is also proportional to the complexity of the package structure, with laminated hermetically sealed packages being the most expensive from a structural standpoint. However, hermetically sealed packages with laminated structures are the most reliable. In this way, not only laminated structures but also hermetically sealed packages are generally expensive, and some form of rationalization, for example, standard structures with standardized external dimensions to promote mass production, is needed to reduce prices. It is hoped that it will be lowered.
しカルながら、半導体装置用パッケージの組立における
要求は必ずしも上記の標準化の方向に沿うものではなく
、むしろそれに逆行し、各半導体装置毎に適合した多種
類のパッケージを要求する傾向にある。例えば、半導体
装置に設けられた接地電位とすれは電極の如き特定の電
極の位置が各半導体装置によつて異なつており、それに
合わせてパッケージ側の前記接地電極に対応するピン(
以下GNDピンと称する)を有するパッケージを用意し
なければならないことになる。また、大きな外形を有す
る半導体装置を搭載するパッケージのマウント部の外形
寸法が、前記半導体装置のそれより小さければ物理的に
搭載することが不可能なのは勿論、この逆の場合におい
ても、ボンディングワイヤー等があまり長くなりすぎて
熱エージング等の熱処理によつてこのボンディングワイ
ヤーの成形形状が変化し、いわゆるエッジタッチと称す
る電気的短絡を生ずる欠点があつた。 本発明の目的は
、多くの種類の半導体装置に対しボンディングワイヤの
エッジタッチなどが生ずることなしに共通に適用でき、
よつて、半導体装置の種類毎に異なつたパッケージを用
意することを不必要とした経済的な半導体装置用パッケ
ージを提供することである。However, the requirements for assembling packages for semiconductor devices do not necessarily follow the above-mentioned standardization direction, but rather go against it and tend to require a wide variety of packages suitable for each semiconductor device. For example, the position of a specific electrode such as a ground potential electrode provided on a semiconductor device differs depending on the semiconductor device, and the position of a pin corresponding to the ground electrode on the package side is adjusted accordingly.
This means that a package with a GND pin (hereinafter referred to as a GND pin) must be prepared. Furthermore, if the outer dimensions of the mounting portion of a package on which a semiconductor device with a large outer diameter is mounted are smaller than those of the semiconductor device, it is of course impossible to physically mount it, and even in the reverse case, bonding wires, etc. When the bonding wire becomes too long, the shape of the bonding wire changes due to heat treatment such as thermal aging, resulting in an electrical short circuit called edge touch. An object of the present invention is to be commonly applicable to many types of semiconductor devices without causing bonding wire edge touching, etc.
Therefore, it is an object of the present invention to provide an economical package for a semiconductor device that makes it unnecessary to prepare a different package for each type of semiconductor device.
本発明の半導体装置用パッケージは、絶縁物からなる
基体に内部配線が設けられかつ中央部に半導体装置マウ
ント用の凹み空間が設けられた主パッケージ本体と、前
記内部配線に接続される金属部を有しかつ前記凹み空間
に嵌合され前記主パッケージ本体と一体化された枠状部
材とを含んだ構 −成を有する。The semiconductor device package of the present invention includes a main package body in which internal wiring is provided on a base made of an insulating material and a recessed space for mounting the semiconductor device in the center, and a metal portion connected to the internal wiring. and a frame-like member that is fitted into the recessed space and integrated with the main package body.
つぎに本発明を実施例により説明する。Next, the present invention will be explained by examples.
第1図は本発明の一実施例の分解斜視図である。FIG. 1 is an exploded perspective view of one embodiment of the present invention.
第1図において、主パッケージ本体1は、セラミックな
どの絶縁基板の積層により形成され、その中央部に、半
導体装置をマウントするための凹み空間、すなわちマウ
ント部2を有しており、さらに内部配線3,3・・・・
・・が設けられ、この配線端は側面のリードフレーム接
続端子3aに導き出されている。In FIG. 1, a main package body 1 is formed by laminating insulating substrates such as ceramics, and has a recessed space, that is, a mount part 2, for mounting a semiconductor device in the center thereof, and further includes internal wiring. 3, 3...
... are provided, and the wiring ends are led out to the lead frame connection terminal 3a on the side surface.
枠状部材5は、積層構造のセラミックパッケージに適用
する場合であれば、後において、主パッケージ本体1の
マウント部に嵌合させるところから、パッケージの製造
段階たる一層を構成するセラミツクスラリーを固形化し
たゴム状板材を打抜き加工する際の打抜かれた部分で構
成することもでき、材料面での節約となるとともに、焼
成後の寸法変化も同一であるところから、本発明に係る
パッケージに使用する場合に大きな利点となる。また、
標準化した主パッケージ本体1のマウント部の外形寸法
は所定の枠状部材5が嵌合できる寸法であることは勿論
であり、その内部配線3については、標準化された主パ
ッケージ本体1として単独においても使用可能であるよ
う、ボンディング可能な内部リード長さを有しているよ
うにしておいてもよいし、また、枠状部材5との組合せ
においてはじめてパッケージとしての機能を有するよう
主パッケージ本体1側にろう付可能な一定の長さの内部
配線のみを設けておき、主要な内部配線は枠状部材5側
の配線金属部6として設けておいてもよい。これは要求
される半導体装置の外形、GNDピンの位置の異なる品
種の多寡によつて決定される。第2図は、第1図の主パ
ッケージ本体1と枠状部材5を一体化した組合せ部の部
分断面図てある。If the frame-shaped member 5 is applied to a ceramic package with a laminated structure, the ceramic slurry constituting one layer will be solidified in the manufacturing stage of the package. It can also be constructed from a punched part when punching a rubber-like plate material, which saves money in terms of materials, and the dimensional change after firing is the same, so it can be used in the package according to the present invention. This is a big advantage in some cases. Also,
Needless to say, the external dimensions of the mount portion of the standardized main package body 1 are such that the predetermined frame-like member 5 can be fitted therein, and the internal wiring 3 of the standardized main package body 1 can be used alone. In order to make it usable, the main package main body 1 side may have a length of internal leads that can be bonded. Only internal wiring of a certain length that can be brazed may be provided, and the main internal wiring may be provided as the wiring metal part 6 on the frame member 5 side. This is determined by the required external shape of the semiconductor device and the number of types with different GND pin positions. FIG. 2 is a partial cross-sectional view of a combined part in which the main package body 1 and the frame member 5 of FIG. 1 are integrated.
標準化された主パッケージ本体1に設けられた内部配線
3と、枠状部材5の上面に設けられたそれに対応すべき
配線金属部6とをろう付10によソー体とし、電気的導
通をとることにより全体内部リード7を構成するものて
ある。The internal wiring 3 provided on the standardized main package body 1 and the corresponding wiring metal part 6 provided on the upper surface of the frame-shaped member 5 are connected to each other by brazing 10 to establish electrical continuity. This constitutes the entire internal lead 7.
枠状部材5の主パッケージ本体1への固定は、枠状部材
5の下面に設けられた金属部8と主パッケージ本体1の
マウント部2の金属面4とをろう付して行う。この場合
の搭載し得る半導体装置の外形は枠状部材の内側外形寸
法によつて規制されることになる。第3図は本発明の第
2実施例の主パッケージ本体1と枠状部材5の組合せ部
の部分断面である。第2図の例では、マウント部と特定
の内部リードとの電気的導通をとることのない構造であ
つたのに対し、本例では特定の内部配線、例えばGND
ピンとの電気的導通をとるべく、枠状部材5の側面に、
底面にまでおよぶ配線金属部9を設けておくことに特徴
がある。このようにすれば、特定ピンの位置に合わせて
枠状部材のみを用意しておけばGNDピンの位置の異な
るパッケージを構成することができる。枠状部材5は標
準化された主パッケージ本体1よりも安価に製造できの
は、その構造から明らかであり、多品種少量生産となる
ところを大量生産の方向へ促すことになり大幅な価格低
減を果すことができるものである。The frame member 5 is fixed to the main package body 1 by brazing the metal portion 8 provided on the lower surface of the frame member 5 to the metal surface 4 of the mount portion 2 of the main package body 1. In this case, the outer shape of the semiconductor device that can be mounted is restricted by the inner outer dimensions of the frame-like member. FIG. 3 is a partial cross-section of a combined portion of the main package body 1 and the frame member 5 according to the second embodiment of the present invention. In the example shown in Fig. 2, the structure was such that there was no electrical continuity between the mount part and specific internal leads, whereas in this example, specific internal wiring, such as GND
In order to establish electrical continuity with the pin, on the side surface of the frame member 5,
A feature is that a wiring metal part 9 is provided that extends to the bottom surface. In this way, packages with different GND pin positions can be constructed by preparing only frame-like members in accordance with the positions of specific pins. It is clear from its structure that the frame member 5 can be manufactured at a lower cost than the standardized main package body 1, and it promotes mass production instead of high-mix, low-volume production, resulting in a significant price reduction. It is something that can be achieved.
第4図は、本発明の第3実施例の主パッケージ本体1と
枠状部材5との組合せ部の他の例の部分断面図である。FIG. 4 is a partial sectional view of another example of the combination of the main package body 1 and the frame member 5 according to the third embodiment of the present invention.
本例は、第2図、第3図の例において、主パッケージ本
体1の内部配線3と枠状部材の上面に設けられたそれに
対応すべき配線金属部6をろう付して一体とし、電気的
導通をとることにしていたのに対し、そのろう付一体と
せず、枠状部材5上には独立した配線金属部を有するこ
とに特徴がある。本例は半導体装置の電極の多い場合に
特に効果のあるものである。即ち、半導体装置側の電極
配列は通常の一列に配列するか又は″千鳥状に二列又は
それ以上の列に配列しておき、それに対応するように主
パッケージ本体側、枠状部材側の配線位置を相互にずら
しておくことが有効である。この点は第2、第3図の例
において、両者の配線は電気的導通をとる必要から両者
の配線位置が連続となるように配置されており異なると
ころである。そして、半導体装置11とのワイヤボンデ
ィングにおいては主パッケージ本体側、枠状部材側の配
線と交互に結線すればよい。その枠状部材における配線
金属部はパッケージの積層”内の内部配線13によつて
外部リードへと導出されている。また、この内部配線は
そのまま外部リードへ導出されるばかりてなく、標準化
された主パッケージ本体の各積層間におけるスルーホー
ル等の手段により電気的導通させ、パッケージの導通抵
抗を下げることなども当然にできることになる。第5図
A,bは面一杯な金属部をもつ枠状部材の斜視図である
。In this example, in the examples shown in FIGS. 2 and 3, the internal wiring 3 of the main package body 1 and the corresponding wiring metal part 6 provided on the upper surface of the frame member are integrated by brazing, and the electrical However, it is characterized by having an independent wiring metal part on the frame-shaped member 5 instead of integrally brazing it. This example is particularly effective when the semiconductor device has many electrodes. In other words, the electrodes on the semiconductor device side are arranged in a regular row or in two or more rows in a staggered manner, and the wiring on the main package body side and the frame member side is arranged in a staggered manner. It is effective to shift their positions from each other.In this respect, in the examples shown in Figures 2 and 3, both wirings are arranged so that they are continuous because it is necessary to maintain electrical continuity. In wire bonding with the semiconductor device 11, it is sufficient to alternately connect the wiring on the main package body side and the frame-shaped member side.The wiring metal part in the frame-shaped member is connected to The internal wiring 13 leads to an external lead. In addition, this internal wiring is not only led out to the external lead as it is, but it is also natural to lower the conduction resistance of the package by making it electrically conductive by means such as through holes between each layer of the standardized main package body. It will be possible. FIGS. 5A and 5B are perspective views of a frame-like member having a full metal portion.
第2図ないし第4図において枠状部材が配線金属部とし
て内部リード形状を有していたのに対し上下面に一杯な
金属部を設け側面で導通させているものである。すなわ
ち、同図aでは、内周に沿つて帯状の金属部14が形成
され、側面の連結帯14″により下面の金属部と導通が
とられている。同図bでは、上下面全面に金属部15が
形成され側面の連結帯15″により上下面が導通されて
いる。このようにすると、前記第3図を用いて説明した
ように、特定のピンを指定することなく、任意の位置の
ピンをGNDピンとすることができる。以上にあげた実
施例においては、積層構造の気密封止型パッケージを用
いて説明したが、本発明はかかる積層構造に限定される
ことはなく気密封止型パッケージならば何にでも適用で
き、例えば外部リードをもたない形式のパッケージであ
つてもよいのは勿論である。In contrast to the frame member having an internal lead shape as a wiring metal portion in FIGS. 2 to 4, full metal portions are provided on the upper and lower surfaces and conduction is provided on the side surfaces. That is, in the figure a, a band-shaped metal part 14 is formed along the inner periphery, and conduction is established with the metal part on the lower surface by the connecting band 14'' on the side surface. In the figure b, the metal part 14 is formed on the entire upper and lower surfaces. A portion 15 is formed, and the upper and lower surfaces are electrically connected by a connecting band 15'' on the side surface. In this way, as explained using FIG. 3, a pin at an arbitrary position can be set as a GND pin without specifying a specific pin. In the above-mentioned embodiments, explanations have been made using a hermetically sealed package with a laminated structure, but the present invention is not limited to such a laminated structure and can be applied to any hermetically sealed package. For example, it is of course possible to use a package without external leads.
【図面の簡単な説明】
第1図は本発明の一実施例の分解斜視図、第2図、第3
図および第4図は本発明の第1実施例、第2実施例およ
び第3実施例における主パッケージ本体と枠状部材との
嵌合部の部分断面図、第5図A,bは本発明に係る上下
面一杯な金属部をもつ枠状部材の斜視図である。
1・・・・・・主パッケージ本体、2・・・・・・半導
体装置マウント用凹み空間、3・・・・・・主パッケー
ジ本体の内部配線、4・・・・・・マウント部金属面、
5・・・・・・枠状部材、6・・・・・・配線金属部、
7・・・・・・全体の配線、8・・・・・・枠状部材の
下面金属部、9・・・・・・枠状部材の側面の配線金属
部、10・・・・・・ろう材、11・・・・・・半導体
装置、12・・・・・・ボンディングワイヤ、14・・
・・・・枠状部材上下面帯状金属部、15・・・・・・
枠状部材上下全面金属部。[Brief Description of the Drawings] Figure 1 is an exploded perspective view of one embodiment of the present invention, Figures 2 and 3 are
4 and 4 are partial cross-sectional views of the fitting portion between the main package body and the frame member in the first, second and third embodiments of the present invention, and FIGS. FIG. 3 is a perspective view of a frame-like member having a metal portion that covers the entire upper and lower surfaces. 1...Main package body, 2...Recessed space for mounting semiconductor device, 3...Internal wiring of main package body, 4...Metal surface of mount part ,
5... Frame-shaped member, 6... Wiring metal part,
7... Entire wiring, 8... Bottom metal part of frame-shaped member, 9... Wiring metal part on side surface of frame-shaped member, 10... Brazing metal, 11... Semiconductor device, 12... Bonding wire, 14...
...Frame-shaped member upper and lower surface band-shaped metal parts, 15...
Frame-shaped member top and bottom all-metal parts.
Claims (1)
央部に半導体装置マウント用凹み空間が設けられた主パ
ッケージ本体と、前記内部配線に電気的導通をとり得る
金属部を有しかつ前記凹み空間に嵌合され前記主パッケ
ージ本体と一体化された枠状部材とを含むことを特徴と
する半導体装置用パッケージ。1. A main package body having internal wiring provided on a base made of an insulating material and a recessed space for mounting a semiconductor device in the center, and a metal part capable of establishing electrical continuity with the internal wiring and the recessed part. A package for a semiconductor device, comprising a frame-like member that fits into a space and is integrated with the main package body.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5974980A JPS6041863B2 (en) | 1980-05-06 | 1980-05-06 | Package for semiconductor devices |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5974980A JPS6041863B2 (en) | 1980-05-06 | 1980-05-06 | Package for semiconductor devices |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56155553A JPS56155553A (en) | 1981-12-01 |
JPS6041863B2 true JPS6041863B2 (en) | 1985-09-19 |
Family
ID=13122192
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5974980A Expired JPS6041863B2 (en) | 1980-05-06 | 1980-05-06 | Package for semiconductor devices |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6041863B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57112057A (en) * | 1980-12-29 | 1982-07-12 | Fujitsu Ltd | Semiconductor device |
JP2577201Y2 (en) * | 1993-12-24 | 1998-07-23 | ホシデン株式会社 | headphone |
-
1980
- 1980-05-06 JP JP5974980A patent/JPS6041863B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS56155553A (en) | 1981-12-01 |
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