JPS6039247U - Measuring jig for chips with superconducting integrated circuits - Google Patents

Measuring jig for chips with superconducting integrated circuits

Info

Publication number
JPS6039247U
JPS6039247U JP1983131377U JP13137783U JPS6039247U JP S6039247 U JPS6039247 U JP S6039247U JP 1983131377 U JP1983131377 U JP 1983131377U JP 13137783 U JP13137783 U JP 13137783U JP S6039247 U JPS6039247 U JP S6039247U
Authority
JP
Japan
Prior art keywords
chip
superconducting integrated
recess
integrated circuit
pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1983131377U
Other languages
Japanese (ja)
Inventor
勇 小高
吉清 治夫
Original Assignee
日本電信電話株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電信電話株式会社 filed Critical 日本電信電話株式会社
Priority to JP1983131377U priority Critical patent/JPS6039247U/en
Publication of JPS6039247U publication Critical patent/JPS6039247U/en
Pending legal-status Critical Current

Links

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のチップテスト装置を示す分解斜視図、第
2図は本考案の一実施例を示す断面図である。 1・・・基台、2・・・配線基板、3・・・位置合せ板
、4・・・入出カフラットケーブル、5・・・バネ容器
、6・・・被測定チップ、7・・・チップ押え板、8・
・・チップ押えネジ、9・・・チップ位置合せ板、10
・・・加圧ブロック、11・・・止め具、12・・・バ
ネ接触子。
FIG. 1 is an exploded perspective view of a conventional chip test device, and FIG. 2 is a sectional view of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Base, 2... Wiring board, 3... Positioning plate, 4... Input/output flat cable, 5... Spring container, 6... Chip to be measured, 7... Chip holding plate, 8.
...Chip holding screw, 9...Chip positioning plate, 10
... Pressure block, 11 ... Stopper, 12 ... Spring contactor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 超伝導集積回路とこの回路の電気信号取り出し一用端子
としてのパッドが複数個同一主面上に形成されたチップ
を装着し、上記超伝導集積回路が動作する温度に冷却し
、上記チップに電気信号を送受せしめ上記チップの良否
を判別する超伝導集積回路搭載チップ用測定治具におい
て、底面形状が上記チップの主面筋状にほぼ等しく、か
つ上記チップかよりわずかに大きい凹部を有し、この凹
部の底面に上記チップ上のパッドの配列間隔に等しい間
隔で、バネ接触子が植設され、上記被測定チップを、上
記凹部に、パッドを有する上記主面が上記バネ接触子と
対向して接触する向きに装着し、上記バットと上記バネ
接触子とを密着せしめるための下面形状が上記被測定チ
ップの裏面形状にほぼ等しくかつ下面周囲が切欠された
加圧ブロックを上記凹部に、上記チップに重畳させて挿
入した状態で、上記凹部の側面に設けられた上記加圧ブ
ロックの固定手段により、上記チップ及び上記加圧ブロ
ックを固定することを特徴とする超伝導集積回路搭載チ
ップ用測定治具。
A superconducting integrated circuit and a chip having a plurality of pads as terminals for taking out electrical signals from this circuit formed on the same main surface are mounted, the superconducting integrated circuit is cooled to a temperature at which it operates, and an electrical signal is applied to the chip. A measuring jig for a chip equipped with a superconducting integrated circuit that transmits and receives signals to determine the quality of the chip, has a concave portion whose bottom surface is approximately equal to the striped shape of the main surface of the chip, and which is slightly larger than the chip. Spring contacts are implanted in the bottom surface of the recess at intervals equal to the array spacing of the pads on the chip, and the chip to be measured is placed in the recess with the main surface having the pads facing the spring contacts. A pressurizing block, which is attached in the direction of contact and whose lower surface shape is approximately equal to the back surface shape of the chip to be measured and has a notch around the lower surface, is placed in the recess to bring the bat and the spring contact into close contact with each other. A measuring device for a chip equipped with a superconducting integrated circuit, characterized in that the chip and the pressure block are fixed by means of fixing means for the pressure block provided on the side surface of the recess when the chip and the pressure block are inserted so as to overlap with each other. Ingredients.
JP1983131377U 1983-08-25 1983-08-25 Measuring jig for chips with superconducting integrated circuits Pending JPS6039247U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983131377U JPS6039247U (en) 1983-08-25 1983-08-25 Measuring jig for chips with superconducting integrated circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983131377U JPS6039247U (en) 1983-08-25 1983-08-25 Measuring jig for chips with superconducting integrated circuits

Publications (1)

Publication Number Publication Date
JPS6039247U true JPS6039247U (en) 1985-03-19

Family

ID=30297028

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983131377U Pending JPS6039247U (en) 1983-08-25 1983-08-25 Measuring jig for chips with superconducting integrated circuits

Country Status (1)

Country Link
JP (1) JPS6039247U (en)

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