JPS6038853A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To form a capacitor having excellent performance by a simple process, and to improve the degree of a function or specifications by forming the capacitor by utilizing a region shaped for forming an active element to a semiconductor base body. CONSTITUTION:Thick field oxide films 18 formed by LOCOS (localized oxidation) and surface oxide films 20 are shaped on the surface of an epitaxial layer 12. The epitaxial layer 12 is isolated into insular regions a1, a2 by p<+> type isolation layers 16. A p type conductive impurity is diffused selectively in each region a1, a2. An n type conductive impurity is each diffused selectively to one part in a p type diffusion layer 22 and one part of the n<-> type epitaxial layer 12 in high concentration. An oxide film 20a is shaped thinly on the surface of the p type diffusion layer 22 in the region a1, and polycrystalline silicon 30 is attached selectively onto the oxide film 20a. The p type conductive impurity is diffused selectively to one part of the p type diffusion layer 22 in the region al in high concentration to form a p<+> type diffusion layer 32. An electrode by an aluminum wiring 40 and a wiring are formed.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technology that is particularly effective when applied to semiconductor integrated circuit devices in semiconductor technology, for example, when a bipolar transistor and an MO8 field effect transistor are formed together. The present invention relates to techniques that are effective for forming capacitors in semiconductor integrated circuit devices.

[Background technology]

Generally, in a circuit configured in a semiconductor integrated circuit device, the number of passive elements such as capacitors is minimized. (Passive elements are being replaced with active elements as much as possible. This means that forming passive elements such as capacitors in a semiconductor integrated circuit device is possible using bipolar transistors or MO8
'! This is because it is more difficult than forming active elements such as field effect transistors.

However, if the functions or specifications of a semiconductor integrated circuit device are to be improved, many passive components such as capacitors must be used in the semiconductor integrated circuit device. For example, in order to make a semiconductor integrated circuit device easy to use, it is first necessary to reduce the number of external components as much as possible. However, in order to reduce the number of external components, the functions of the external components must be provided inside the semiconductor integrated circuit device. Most of these external components are passive elements such as capacitors. Therefore, passive components such as capacitors must be formed as elements inside the semiconductor integrated circuit device.

However, as mentioned above, forming passive elements such as capacitors, especially passive elements with excellent performance, inside a semiconductor integrated circuit device is much more difficult than forming active elements such as transistors. Ta. and,
This has been one of the major factors hindering the advancement of the functions and specifications of semiconductor integrated circuit devices.

The above-mentioned problems have been made clear by the inventor.

[Purpose of the invention]

An object of the present invention is to enable passive elements, especially capacitors with excellent performance, to be relatively easily formed inside a semiconductor integrated circuit device fβ, thereby making it possible to improve functions and specifications, and to provide T7 semiconductor technology. There is a particular thing.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Overview of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, by forming a capacitor using the area that can be formed for forming an active element on a semiconductor substrate, a capacitor with excellent performance can be formed in a simple process. The objective is to reduce the number of parts and improve functionality or specifications.

〔Example〕

Hereinafter, typical embodiments of the present invention will be described with reference to the drawings.

In addition, the same or corresponding parts are indicated by the same reference numerals in the drawings.

FIG. 1 to FIG. 7 sequentially show the bag portion of the forming process of a semiconductor integrated circuit device according to the present invention.

First, the outline of the semiconductor integrated circuit device formed in the steps shown in FIGS. 1 to 7 is as follows.

In other words, a capacitor is formed by a p-type conductive region formed in an island shape on an n-type conductive semiconductor substrate, an insulating film formed on the surface of this region, and an electrode formed on this insulating film. ing. Here, for example, polycrystalline silicon is used as the electrode.

Further, the outline of the steps shown in FIGS. 1 to 7 is as follows.

That is, it is a semiconductor color 11 circuit device in which both a bipolar transistor and a MUS field effect transistor are formed. A capacitor is formed in this region by a step of forming an electrode via an insulating film, and the p-type conductive region is formed simultaneously with the base region of the bipolar transistor. Here, the electrode is formed simultaneously with the gate electrode of the MO8 field effect transistor.

A detailed explanation will be given below based on FIGS. 1 to 7.

FIG. 1 shows a portion of a semiconductor integrated circuit substrate that has been preprocessed to form a semiconductor integrated circuit device according to an embodiment of the present invention. The semiconductor substrate used is one in which an epitaxial layer 12 doped with a low concentration of n-type conductive impurities is formed on a p-type semiconductor substrate 10 doped with a low concentration of p-type conductive impurities. . The epitaxial layer 12 has a thick field oxide film 18 and a surface oxide film 20 formed by LOCOS (partial oxidation) on its surface. Further, the epitaxial layer 12 is separated into island regions al and a2 by a p+ type N layer 16. p
The + type separation layer 16 is formed by selectively diffusing p type conductive impurities from below the field oxide film 18 to the substrate 10 at a high concentration.

Next, as shown in FIG. 2, pW conductive impurities are selectively diffused into each region al and a2. This p-type diffusion layer 22 is diffused to a medium concentration so that its surface concentration is about 2 to 310" atm/cml in order to become a base region of a bipolar transistor. This increases the sheet resistance near the surface. It becomes as low as about 200Ω/mouth.

In the region a1, the p-type diffusion layer 22 covers almost the entire region.
Further, the region a2f is formed in a part thereof.

Subsequently, as shown in FIG. 3, in region a2, n-type conductive impurities are selectively diffused into a portion of the p-type diffusion layer 22 and a portion of the n-type epitaxial layer 12 at a high concentration. The emitter region and collector lead-out diffusion layer of the npn5 bipolar transistor Q2 are formed in the region a2 of the n+ type scattering layer 24 selectively diffused in this manner.

Next, as shown in FIG. 4, the p-type diffusion layer 22 in the region a1 is
A thin oxide film 20a is formed on the surface of the oxide film 20a, and polycrystalline silicon 30 is selectively deposited on the oxide film 20a. As a result, a capacitor Om is formed between the polycrystalline silicon 30 and the p-type diffusion layer 22 with the oxide film 20a interposed therebetween.

After this, as shown in FIG. 5, the p-type diffusion layer 2 in the region a1 is
By selectively diffusing p-type conductive impurities into a part of 2 at a high concentration, p
+ type scattering layer 32 is formed.

Then, as shown in FIG. 6, electrodes and wiring using aluminum wiring 40 are provided. As a result, area a1
From area a2 is the electrode of capacitor Cm, and from area a2 is n
Collector 0. of pn type bipolar transistor Q2. Base B and emitter E electrodes are taken out.

FIG. 7 shows a plan view of a portion where the capacitor Cm is formed.

In the embodiment shown in FIGS. 1-7, capacitor Om is formed together with bipolar transistor Q2.

By the way, what should be noted here is that the p-type diffusion layer 22 forming one electrode region of the capacitor Om is the same as the p-type diffusion layer 22 forming the base region of the bipolar transistor Q2.
It means that it is the same thing. Thereby, one electrode region of the capacitor Om does not require any special process to form it, and can be formed simultaneously with the process for forming the base region of the bipolar transistor Q2. This greatly simplifies the formation of the capacitor ○m within the semiconductor integrated circuit device1.

At the same time, since one electrode region of the capacitor Om is composed of the p-type diffusion layer 22 of the same medium concentration as the base region of the high voltage transistor Q2, the resistance within the electrode region is, for example, about 20θΩ/gate, the same as the base. It can be set to a value as low as . As a result, a capacitor Cm with low series resistance loss, so-called a capacitor Cm with a large Q value and excellent performance, is formed inside the semiconductor bond circuit device. Therefore, for example, by incorporating a capacitor that has been conventionally attached externally, it becomes possible to easily increase the functionality or specifications of a semiconductor integrated circuit device.

Furthermore, as shown in FIG. 9, not only the bipolar transistor Q2 but also MO8i field effect transistors Qp and Qn can be formed simultaneously in the semiconductor integrated circuit device of the above-described embodiment.

In the semiconductor integrated circuit device whose embodiment is shown in FIG.
A region a3 for forming a MoS field effect transistor Q p +Qn is also provided.

This region a3 is formed in an island region separated by a high concentration p+ type separation layer 16.

An n++ buried layer 14 is formed in the region a3. Furthermore, p-type wells 36 are partially formed by selectively diffusing p-type conductive impurities at a low concentration. In this well 36, an n++ diffused layer 34°34 formed by selectively diffusing n-type conductive impurities at a high concentration is formed.
．． Reference numerals 34 are the source Sn region and drain Dn region of the n-channel MOS N valve effect transistor Qn.

Then, a thin oxide film 20a forming a gate insulating film is formed in a portion sandwiched between the source Sn region and drain Dn region, and polycrystalline silicon 30 forming a gate electrode is deposited on top of the oxide film 20a. ing.

On the other hand, p-type conductive impurities are selectively diffused to a high concentration in the region a3 where the well 36 is not formed.
A diffusion layer 32.32 is formed, and this diffusion layer 32.32 becomes the source Sp region and drain Dp region of the p-channel MO8t field effect transistor Qp. Then, a thin oxide film 20a serving as a gate insulating film is formed in a portion sandwiched between the source Sp region and the drain Dp region.
Polycrystalline silicon 3, which forms the gate Gp electrode, is placed on the soil.
0 is attached to the bag.

The electrodes of each Mo8t field effect transistor Qp, Qn are taken out and wired using the aluminum wiring 40. In this case, the gates GI) and Gn of the p-channel MO8t field-effect transistor Qp and the n-channel Mo8t field-effect transistor Qn are commonly connected, and the source Sp of the p-channel Mo5t field-effect transistor Qp and the n-channel Mo3t field-effect transistor Qn
By connecting the drain Dn of the field effect transistors Qp, Q, and n, the field effect transistors Qp, Q, and n mutually constitute a 0-M2S (complementary MO8) type logic inverter.

Although not shown, the drain Dp of the p-channel MO8 field effect transistor Qp is connected to the epitaxial layer 1.
2, also an n-channel Mo5t field effect transistor Q
Sources Sn of n are connected to the wells 36, respectively.

Here, the Mo5t field effect transistor Q p tQ
In the capacitor Om formed together with n, the polycrystalline silicon 30 forming the other electrode is deposited at the same time as the polycrystalline silicon 30 forming the electrodes of the Mo8t field effect transistors Qp and Qn. Also, a p+ type scattering layer 32 serving as an outlet for one of the electrode regions, and a p+ type diffusion layer 3 forming the source Sp region and drain Dp region of the p channel MOSt field effect transistor Qp, respectively.
2 can be formed simultaneously. Further, the oxide film 12 serving as the dielectric layer is an extremely thin oxide film formed by a MOSFET gate conversion process, and the process is also common here. Due to this.

The capacitor Cm can be formed by the Mo8t field effect transistor Q without any special process operation.
The transistors Qp and Qn can be formed simultaneously using the process for forming the transistors Qp and Qn as they are.

Furthermore, in a semiconductor integrated circuit device in which Mo8t field effect transistors Qp, Qn and the bipolar transistor Q2 are formed together on the same semiconductor substrate, one electrode region of the capacitor Om is connected to the bipolar transistor Q2, as described above. The capacitor Cm can be formed simultaneously with the step of forming the base B region, and as a result, the capacitor Cm can be easily formed without increasing the number of steps.

FIG. 9 shows another embodiment of the invention.

In the embodiment shown in the figure, one electrode region of the capacitor Om is formed at the same time as the p-type A/36 formed to form the n-channel Mo3t field effect transistor Qn. In this example as well, the capacitor Om
can be easily formed without increasing the number of steps by using the process for forming the complementary MO8 as is.

〔effect〕

(1) One electrode region of the capacitor is formed by the same selective diffusion layer as the base region of the bipolar transistor, so that the electrode region is formed at the same time as the step of forming the base region of the bipolar transistor;
This provides the effect that a capacitor can be easily formed inside a semiconductor integrated circuit device without increasing the number of steps in the process.

(2) By forming the above capacitor together with a bipolar transistor and an MO8 field effect transistor, the other electrode of the capacitor can also be formed at the same time in the process for forming the bipolar transistor and the MO8 field effect transistor. This provides the advantage that a capacitor can be formed more easily inside a semiconductor integrated circuit device without increasing the complexity of the process.

(3) By forming one electrode region of the capacitor with the same selective diffusion layer as the bibolar transistor base region, the resistance of the electrode region can be lowered;
This provides the effect that a capacitor with a high Q value and excellent performance can be formed inside a semiconductor integrated circuit device.

The above (1) to (3) provide a synergistic effect in that the number of external parts of a semiconductor integrated circuit device can be reduced and its functions or specifications can be improved.

Although the invention realized by the present inventor has been specifically explained based on examples, this invention is not limited to the above-mentioned examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say. For example, the semiconductor substrate and the epitaxial layer described above may have conductivity types in which p and n are opposite to each other. Furthermore, an aluminum electrode film or metal silicide may be used instead of the polycrystalline silicon. The p-type spreading layer, which becomes one electrode of the capacitor, is the base of the bipolar transistor or the source of the p-channel MO8FET.
Needless to say, it is not necessary to form the drain layer and the drain layer at the same time, and a higher concentration diffusion layer may be formed separately.

[Application field]

The above description will mainly focus on the field of application of the invention made by the present inventor, which is the formation of capacitors inside a semiconductor integrated circuit device in which bipolar elements and 0-MO3 elements are formed together. Although we have explained the case where it is applied to technology, it is not limited to that, for example,
The invention can also be applied to capacitor formation techniques in semiconductor integrated circuit devices in which only bipolar elements are formed or in semiconductor integrated circuit devices in which only MO3 elements are formed. It can be applied at least to conditions in which impurities of a conductivity type opposite to that of the semiconductor substrate are selectively diffused.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a part of a semiconductor substrate that has been preprocessed for use in the process of forming a semiconductor integrated circuit device according to the present invention, and FIG. 3 is a cross-sectional view showing a state in which one electrode region of a capacitor is formed; FIG. 3 is a cross-sectional view showing a state in which a diffusion layer to be an emitter region and an intra-collector diffusion layer is selectively formed on the semiconductor substrate of FIG. 2; FIG. is a cross-sectional view showing the state in which the other electrode of the capacitor is formed on the semiconductor substrate shown in FIG. 3, and FIG. 5 is a cross-sectional view showing the semiconductor substrate shown in FIG.
6 is a cross-sectional view showing a state in which a + type scattering layer is formed, FIG. 6 is a cross-sectional view showing a state in which aluminum wiring for electrode extraction and wiring is formed on the semiconductor substrate of FIG. 5, and FIG. 8 is a cross-sectional view showing the planar state of the capacitor portion of the semiconductor integrated circuit device shown in FIG. 6, FIG. 9 is a cross-sectional view showing the state of other parts of the semiconductor integrated circuit device shown in FIG. FIG. 3 is a cross-sectional view showing another embodiment of the semiconductor integrated circuit device according to the invention. DESCRIPTION OF SYMBOLS 10...p-type semiconductor substrate, 12...n-type epitaxial layer, 14...n++ buried layer, 16...p+
+ Separation 1.18...Locos (partial oxide film), 20...
・Surface oxide film, 20a...insulating film (gate oxide film),
22...p-type conductive region (p-type diffusion layer), 24...n
++ conductive region (n f type diffusion R), 30... electrode (polycrystalline silicon), 32... p+ type scattering layer 34...
n+ type scattering layer 36... p- type conductive region 4 p- type well), 40... aluminum wiring, 41... contact region, Cm... capacitor, al... formation area for capacitor Om , Q2...npn type bipolar transistor, a2... formation region of bipolar transistor Q2. Qn...n channel MO8t field effect transistor,
Qp...p channel A/MO8 field effect transistor, a3...0-MoS field effect transistor Qn
+ Q p formation region, C... collector, B...
Base, E...emitter, Sn, Sp...source,
Gn, Gp...gate, Dn, Dp...drain. Fig. 5 r - Fig. 6 θ2 Fig. 7

Claims (1)

[Claims] 1, n (p ( formed in a semiconductor substrate of pJ conductivity type)
n) A semiconductor integrated circuit device comprising a capacitor formed by a conductivity type region, an insulating film formed on the surface of this region, and an electrode formed on the insulating film. 2. The semiconductor integrated circuit device according to claim 1, wherein the electrode is made of polycrystalline silicon. 3. A semiconductor integrated circuit device in which a bipolar transistor is formed, which includes a step of forming a p(n) conductivity type region in a semiconductor substrate of an n (pi conductivity type) and a step of forming a p(n) conductivity type region on the surface of this region via an insulating film. In the step of forming electrodes and Ic of forming a capacitor in the region, the above p (n
) A method of manufacturing a semiconductor integrated circuit device, characterized in that a conductivity type region is formed at the same time as a base region of the bipolar transistor. 4. The semiconductor according to claim 3, wherein an MO8 field effect transistor is formed in the semiconductor integrated circuit device, and the electrode of the capacitor is formed at the same time as the gate electrode of the MO8 field effect transistor. A method of manufacturing an integrated circuit device.