JPS6038828A - Digital and analog-contained integrated circuit device - Google Patents

Abstract

PURPOSE:To enhance efficiency for the test of a digital and analog contained integrated circuit without adding any terminal by a method wherein an electric passage, which is controlled by a signal to indicate a test mode, is provided in such a way that a test signal is supplied to a digital circuit from a terminal, which is served for the input and/or output of analog circuit parts, without passing through the analog circuit parts. CONSTITUTION:When a terminal 4 is usually in operation, the terminal 4 supplies a L-level signal. By this, a clocked interter 8 is turned into a state of high impedance and doesn't output a signal sent from a terminal 2. A terminal 10a in a switching circuit 10 is connected to a terminal 10b, while terminals 11a and 11b in a switching circuit 11 are mutually connected. Accordingly, an F-G input signal sent from a terminal 1 is supplied to a digital circuit 6 through an analog circuit 7, and regenerative signal sent from the terminal 2 is supplied to the digital circuit 6 through an analog circuit 5. As a result, a capstan speed control signal is obtained from a terminal 3. At this time, as the input impedance of the inverter 8 is an MOS gate input and is very high, an analog signal, which is supplied to the terminal 2, is given no influence.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to attracting two or more different impurities to one terminal in a +-conductor integrated circuit. Generally speaking, one input terminal number in an analog/digital mixed integrated circuit can be used as an analog input and a digital input terminal during testing, and can be used as a 3i input terminal without adding any additional terminals.
The purpose is to improve the efficiency of testing of printed circuits.

First, an example of a conventional analog/digital mixed integrated circuit will be explained with reference to FIG. Analota shown in Figure 1
The digital mixed type rejection circuit 100 is, for example, VTR.
1, 2, and 3 are terminals provided on the 1C100 for the digital servo of the capstan that can be used. A signal from a generator ('E' G ) that generates a frequency signal according to the rotational speed of the capstan is supplied to the terminal 1, which serves as an analog signal input terminal. The signal e supplied to the terminal is a signal obtained by reproducing the saw gear stun speed control signal recorded on the video tape eLIi, which is also an analog input terminal. Analog signals from terminals 1 and 2 are supplied to a PG input amplifier 7 and a reproduction control signal input amplifier 5 within the IC 100, respectively. The input capacitor amplifiers 5 and 7 have an analog configuration, and the digital servo controller 6 handles the input signal (converts it into an M waveform and an A 8 level.The controller 6L has a digital circuit configuration, and the analog circuit 5, 7
A capstor/speed braking signal is generated at terminal 3 in response to the output from the motor.

When testing the function of the DigiMole circuit 60 in the integrated circuit 100, an analog test signal must be input from the terminal 1 and input to the digital circuit 6 through the analog circuit 7. As described above, since test No. 18 must pass through the analog circuit 7, errors caused by the response and waveform of the analog circuit 7 become obstacles to complicated initial settings and speeding up in the functional test of the digital circuit 6. .

As a solution to this problem, a switch circuit and a test signal input terminal are provided, and during the test, test signal 18 is input directly to the digital circuit 6 via the analog circuits 7 and 5. The input is switched to the test signal input terminal. For this reason, the addition of a terminal for test signal input was eliminated.

The purpose of the present invention is to provide an integrated circuit that can directly supply test (no. This will be explained with reference to the drawings.

FIG. 2 shows an embodiment of the present invention. The same 11 functional capitals as the conventional example of the 1st ward are indicated by the same numbers and their descriptions are omitted. The integrated circuit 200 shown in No. 21 further includes a CMO8 (
It has a clocked inverter 8 and an inverter 9 having a complementary MO8I transistor configuration, a switch circuit 10, 11, and a switch control terminal 4. The input of the clot inverter 8 is connected to the terminal 2, and the output thereof is connected to the terminal 10C of the switch circuit 10. switch circuit 1
The other terminals IQa, 101) at 0 are connected to the input of the digital circuit 6 and the output of the analog circuit 7, respectively. As control signals for the clocked inverter 8, the signal at the switch terminal 4 and the signal inverted by the signal t inverter 9 are used, and the signal from the switch terminal 4 is used to further connect one switch. The switch circuit 11 is also controlled by the signal from the switch terminal 4 to the terminal 11a.

11b Ichiwan J is all done. Terminal 11a is digital circuit 6
The input terminal 11b is maintained at the output of the analog circuit 5, respectively.

Next, a description of the operation shown in FIG. 2 will be given. During normal use (non-test mode), terminal 4 supplies an L level signal. As a result, the clocked inverter 8 is in a constant impedance state and does not output a signal from the terminal 2. Also,
The terminal 10a in the switch circuit 10 is connected to the terminal 10b, and the terminals 11a and llb in the switch circuit 10
is connected. Therefore, the F and G inputs from terminal 1 (No. 8 are sent to digital circuit 6 via analog circuit (FG input amplifier) 7, and the old note signal from terminal 2 is sent to analog circuit (playback control signal input amplifier) 5. The signals are respectively supplied to a digital circuit (digital servo controller 6) via the terminal 3. A cabzukun speed control signal is obtained from the terminal 3.

At this time, the impark 80 input impedance is MOS
Since the gate is manually operated and there is no irises, is the analog 1B supplied to terminal 2 the 2 tube? I won't give it.

Next, for testing the digital circuit 6, when the H-level signal 1iS is supplied to the switch terminal 4, the clocked inverter 8 operates as a normal inverter.

Further, the terminal tOa of the switch circuit 10 is connected to the terminal 10C, and the terminals 118 and 11b of the switch circuit 11 are disconnected. When a test signal is supplied to the Njta element 2 in such a state, the test signal is supplied to the digital circuit 6 without passing through the analog circuits 5 and 7. Therefore, lQ'i if in the initial setup and screening speed-up of the digital circuit, which depends on the response characteristics and output characteristics of the analog 101 paths 5 and 7, is prevented.

Analog times%5. The digital circuit 141 is also constructed in the same manner as the digital circuit 141.

In the test mode, since a digital signal is input to the terminal 2, the analog circuit 5 is prevented from applying its output to the circuit j'2i6 by the switch circuit Tl611. Or, use another circuit structure Jlt (
(For example, if the output of the circuit 5 is derived outside the IC 200 or applied to another analog circuit) 1 switch tL! Circuit 11 is a must-fight.

In addition, if the operation of the analog circuit 5 is problematic, the analog circuit 5 may be disabled by No. 1b, which indicates a test mode in which human power is applied to the VC1 terminal 4 instead of the switch circuit 11. can.

Kates 8 and 9 are CMOS. As mentioned above, these can also be P-M (J8 or N-K08 inverters. In this case, even if the input is at an intermediate level, the gates in the line There is no problem because the current consumption of
L! Following FK, the γ self-expense current may increase abnormally, causing a problem. Therefore, by using a single clocked inverter 8 as shown in FIG. 2, the power supply to the gate 8 is turned off during non-test mode.

As described above, it becomes possible to easily perform a test without adding a terminal for digital No. 1b input during testing. In this embodiment, a digital servo for capstan speed control for a VTR is taken as an example, but the present invention can be applied to all other digital/analog mixed integrated circuits.

Although the input terminal 2 of the analog circuit is used as the digital signal input terminal in the test mode in FIG. 2, it is not necessarily limited to this. For example, there is no problem even if analog input terminal 1 is used.

It is also possible to use the output terminal of another analog circuit, whose output does not need to be checked during the test mode. However, in this case, it is necessary to devise measures in advance for the analog output circuit so that the analog output circuit is not cut off or has extremely low impedance during the test mode.

The third section is an example of an analog output circuit devised in this way. Since terminal 4 is at L level in non-test mode,
The transistor 17 connected through the resistor 16 is cut off, and the output of the analog circuit 12 is outputted from the terminal 2o through the resistor 13 and further through the emitter follower consisting of the transistor 14, load resistor 18, and power supply 15. ,
At this time, since the inverter 28 has a large impedance, there is no influence on the analog circuit 12. Further, the analog signal from the terminal 21 is passed through the analog circuit 27 to the digital circuit j! 'l' 126. On the other hand, in test mode, terminal 4 becomes 1 level and transistor 1
Since 7 is conductive, the trough 2 and 14 are about to be cut off regardless of the output of the analog circuit 12. Therefore, even if the digital signal Hg is applied externally to the terminal 2o, it is not connected to the output of the analog circuit 12 and is supplied to the digital circuit 26 via the inverter 28.

The switch means 30 is composed of cages 21-24. In the non-test mode, the terminal 4 is at the L level, so the output of the gate 23 is at the H level regardless of the output of the gate 28, and the output of the gate 8 is not transmitted to the digital circuit 26.

- An analog signal input from the terminal 21 is input to the gate 21 via the analog circuit 27, and is input to the digital circuit 26 via the gate 24. Test mode 1
Since terminal 4 of tf is at H level, the output of gate 22 is L.
The output of the gate 21 becomes H level regardless of the output of the analog circuit 27, and the test digital Buddhist symbol inputted to the terminal 20 is passed through the gate 28, gate 23, and gate 24 to the digital I! l is supplied to path 6.

In this way, according to the present invention, the MO8 type digital circuit and the MO
Adding just a few extra wires to an integrated N-way device containing an 8 or bibolar V analog ILA controller; testing of the digital section can now be done more easily. : There are stiff spots.

Furthermore, since the digital part can be tested through the analog circuit, there is an advantage that a general-purpose tester for digital ICs can be used.

The present invention is not limited to the circuit configurations shown in FIGS. 2 and 3, but can be widely applied to digital/analog mixed integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional example, FIG. 2 is a block diagram showing one embodiment of the present invention, and FIG. 3 is a block diagram showing another embodiment. 1 to 4, 20.21... terminal, 5. 7. 1
2゜27... Analog times 1i, 6.26...
... Digital circuit, 8 ... Clocked inverter, 9. Inverter for 28 ..., 10. 1.1.
30... Switch means, 13.16, 18.
...Resistance, 14.17...Transistor, 15...Electrical A, 21-24...Kate.・1-cho、・1、Representative Patent Attorney Uchihara Kita Town'）

Claims (1)

[Claims] 1. In an integrated circuit device including both a digital circuit section and an analog circuit section, an administrative reform is provided in which an electrical path is provided which is controlled by a signal indicating a test mode so that the analog circuit signal is Digital/analog mixed integrated circuit device.