JPS6037913B2 - electronic clock - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a speed adjustment device for an electronic timepiece, and more particularly to one that corrects rate errors during zero adjustment.

For example, if a crystal oscillator is used as an oscillator for an electronic clock,
Due to manufacturing variations in crystal oscillators, when assembling a watch, the trimmer capacitor attached to the oscillator is adjusted to adjust the oscillation frequency to a constant reference frequency.

However, the oscillation frequency of a crystal resonator fluctuates due to the influence of temperature changes, aging, etc. Conventionally, it has been proposed to incorporate an oscillation frequency stabilization circuit or a temperature compensation circuit into the oscillator to correct this problem, but these are all analog systems and require large devices, making them impossible to implement, especially in wristwatches. There was a flaw. Also, electronic watches that have a built-in zero adjustment device that resets the contents of the seconds counter to 0 whether the watch is behind or ahead by operating a pushbutton switch, etc. in accordance with an appropriate time signal. However, this only corrects clocks that tend to be slow or fast according to the time signal, but does not make clocks that tend to run late move forward or clocks that tend to run backwards late. The present invention does not use a conventional analog circuit, but instead uses a zero-setting device to perform zero-setting and at the same time determines the amount of delay or advance of the clock. Proceed step by step and
A clock that tends to run fast is slowed down little by little so that it always operates with a certain level of accuracy.

By the way, if you try to determine the amount of delay or advance of a clock based only on the contents of the seconds at the time of zero standard, depending on the operation timing of zero standard, if the amount of delay is large, it will be determined as advance, and if the amount of advance is large, it will be determined as lag. there is a possibility.

At this time, if the rate is corrected according to these determinations,
Clocks that tend to move forward are corrected to move further forward, while clocks that tend to move slower are corrected to move slower. The present invention provides a useful speed control device which also eliminates this drawback.

The present invention will be described below according to an embodiment of the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, the oscillation circuit 1 includes a crystal resonator and is 32.76 mm
Outputs the reference signal fo for the second day. The frequency dividing circuit 2 is composed of a large number of T-type flip-flops FF2, -FF2n, and divides the frequency of the reference signal fo to IH2. The frequency dividing circuit 2 inserts an OR gate between the flip-flops FF22 and FF in the second and third stages, and in addition to the output signal fo/4 of the second-stage flip-flop FF22, the delay correction described later is provided. The signal Pd and the advance correction signal Pf are also input to the T terminal of the third stage flip-flop FF23. The frequency-divided IHZ signal s is sequentially input to a second counter 3, a component force counter 4, an hour counter 5, and a day counter 6, and the respective time information is counted and displayed via each decoder/driver circuit (not shown). The time is displayed by the device. The second counter 3 is composed of a 1-digit second counter and a 1-digit standing second counter, each of which performs IG Hayabusa and hexadecimal operations, and the second counter 3 performs 6G operation.

The truth values of each BCD output of the second counter 3 are as shown in Tables 1 and 2.

Table 1: 1st digit second power - Table 2: 10th digit second power - These BCD outputs are input to the buffer memory 7, decoder 8 for generating a reference signal for correction, comparison circuit 9, and decoder for sand display (not shown). be done.

The buffer memory 7 is composed of D-type flip-flops corresponding to the number of BCD outputs, and reads and stores the BCD output of the second counter 3 at the rising edge of the clock signal c1 inputted to the cl terminal. Comparison circuit 9 is B of second counter 3
Input the CD output, compare whether it is 24 seconds or more or less than 24 seconds, and output a logical value 1 when it is 24 seconds or more, and open the AND gate A.
ND, and exclusive or gate Ex-OR
A carry signal is inputted to the component force counter 4 via. A minute signal m of 1/60 Hz frequency-divided by the second counter 3 is input to the other exclusive OR gate Ex-OR. Switch S is a push switch for zero regulation,
For example, if it is an electronic wristwatch, it is installed on the side, and when the switch S is pressed to turn on, the voltage V+ is applied to the zero regulation signal generator 1.
This is added and a logical value of 1 is input.

The 0-normalization signal generator 10 generates a set signal R by taking a clock signal CL having a single constant pulse in accordance with the input of the logic value 1.

The clock signal cl is input to the cl terminal of the buffer memory 7 mentioned above via the AND gate AND2, and is also input to the other of the AND gates AND to control the derivation of the output of the comparator circuit 9. The reset signal R rises after a slight delay from the fall of the clock signal cl, and is input to the R terminal of the sand counter 3 and the R terminal of the counter 1, and is reset while the logic value is 1.

The counter 11 is divided by 1/60× from the hour counter 5.
1/60 x 1/24 day 2 day signal d and gate AN
It is a counter whose output d30 becomes a logical value 1 only when the input pulse is inputted through D3 and the input pulse is 3.

When the 0-regulation press switch S is turned on by applying pressure, the output of the 0-regulation signal generator 10, the reset signal R, is input to the R terminal of the counter 1 to reset the counter 11.
Thereafter, when the reset signal R becomes a logical value of 0, the counter 5 starts counting.

The output d30 of the counter 11 is inputted to the other side of the AND gate AND3 via an inverter ln.

Therefore, after the counter 11 starts counting, when the day signal d from the hour counter 5 reaches 3 (point '' when 30 days have passed), the output d3 of the counter 11 is closed to close the AND gate AND3. If it is within 30 days from the start of counting, the logical value is 0, and if more than 30 days have passed, the logical value is 1. In addition, the output d3 of the counter 11 and the inverter ln
, to the AND gate AND2 to control input of the clock signal CL to the CL terminal of the buffer memory 7.

The output of the buffer memory 7 is input to a numerical value detection gate circuit 12.

That is, this numerical value detection gate circuit 12 is 4 to 8 seconds from the memory BCD output of the buffer memory 7, 9 to 1 Shinsa 14 to
1 parent sand, 19-2 lactic acid, 24-2 parenteral, 27-31 seconds, 32-3 present small 37-41 seconds, 42-46 seconds, 47-
51 seconds, 52 to 5 Kagami sand, each second detection signal C,, C2...C, . occurs. Third
Table Numerical detection gate circuit The correction reference signal generation decoder 8 that receives the BCD output of the sand counter 3 has the contents of the second counter 3 as "6J "12", "14", "24".
, "28", "30", and "36", outputs signals D6, D, 2, D, 4, . . . , D36 whose logical value is 1, respectively.

Outputs D6, D, 2 of the decoder 8 for generating reference signals for damage
...Correction reference signal generation circuit 1 3 which inputs D36
are respectively D6, D60D, 2, D60D, 20D, 4, D
G+D, 20D, 40D24,”・, DB+D, 20○
, F based on the logic of 40D240DKani10D3o+D36
,,F2,F3,F4,F5,F6,F7 are output.
Outputs F, , F2, F3, of the correction reference signal generation circuit 13
F4 and the outputs C, , C2, of the numerical value detection gate circuit 12,
In the first rate correction amount selection gate circuit 14 which receives C3 and C4 as inputs, the correction reference signal F. , F2, F3, F4 and second detection signal C. , C2, C3, and C4 are paired and ANDed, and the OR output using these AND outputs as input is the output Pd of the first rate correction amount selection gate circuit 14.
'. That is, when the second detection signal C, has a logical value of 1, the output Pd' of the first rate correction amount selection gate circuit 14 is:
Outputs one pulse every minute. When the second detection signal C2 has a logical value of 1, the output Pd' outputs two pulses every minute.
When the second detection signals C3 and C4 have a logical value of 1, the output Pd' outputs 3 pulses and 4 pulses every minute.
Outputs F, , F2, . . . of the correction reference signal generation circuit 13
F7 and second detection signals C5, C6. ...,C,. In the second rate correction amount selection gate circuit 15 which receives as inputs correction reference signals F,, F2,..., F7 and second detection signals C,
．． , CM C9. .
becomes.

That is, the second detection signals C5, C6, . . . , C, . When each has a logical value of 1, the output Pf' outputs 7 pulses, 6 pulses, . . . , 1 pulse every minute.

In the correction reference signal generation decoder 8, in the above embodiment, the contents of the second counter 3 are "6", "12", ..., "
36'', but the present invention is not limited to this.

In short, here, it is sufficient to obtain seven independent (that is, different phases) pulses in one minute, and there is no problem with any value as the content to be decoded. In the correction reference signal generation circuit 13, the logical sum of these is appropriately taken, and the outputs F, (a signal with one pulse per minute, F2 (a signal with two pulses per minute), ..., F7( 1
7 pulse signals per minute). As described below, only the number of pulses per minute affects rate correction. 1st
, the output Pd of the second rate correction amount selection gate circuits 14 and 15
' and Pf' are respectively input to a correction signal generation circuit 16 that generates a delay correction signal Pd and a lead correction signal generation circuit 17 that generates a lead correction signal Pf.

Details of the delay correction signal generation circuit 16 and the advance correction signal generation circuit 17 are shown in FIGS. 2 and 3, respectively.
In the delay correction signal generation circuit 16, the output Pd' of the rate correction amount selection gate circuit 14 is connected to a D-type flip-flop FF.
, is input to the ○ terminal of the elbow, and this D-type flip-flop F
The Q terminal output of F, 6-, is input to the D terminal of the next stage D-type flip-flop FF, 6-2.

The T terminals of these D-type flip-flops FF, elbow, FF, 6-2 are connected to an inverted signal fo of the reference signal fo of the oscillation circuit 1.
, the output signals fo/2, fo/ of the first and second stage T-type flip-flops FF2, FF2 of the frequency dividing circuit 2.
The output of the NAND gate NAND,6 which has input 4 is input. The AND gate AND,6 inputs the Q terminal output and the Q terminal output of the D-type flip-flops FF,6- and FF,5-2, and outputs it as a delay correction signal Pd to the second and third stages of the frequency dividing circuit 2. Tier T-type flip-flop F
It is input to the OR gate OR inserted in questions F22 and FF23.

In the advance correction signal generation circuit 17, the output Pf' of the rate correction amount selection gate circuit 15 is connected to a D-type flip-flop FF.
, 7-, and its Q terminal output is input to the D state of the next stage.
Type flip-flop FF. It is input to the D terminal of 7-2.

These D-terminal flip-flops FF, 7-. and F.F.
, 7-2, the output signal fo/4 of the second-stage T-type flip-flop FF22 of the frequency dividing circuit 2 is input. The AND gate AND, 7-, inputs the Q terminal output and Q terminal output of the D-type flip-flops FF, 7- and FF, 7-2, respectively, and the AND gate AND,
7-2 is the output of the AND gate AND, 7-, the inverter ln, 7-, and the inverted signals fo/2, fo/4 of the output signals fo/2, fo/4 through the inverter ln, 7-2, and the inverter ln, 7-2. The reference signal fo of the oscillation circuit 1 is input. The output of the AND gate AND,7-2 is inputted to the OR gate OR, as the advance correction signal Pf. The operations will be explained in detail. When the 0-regulation press switch S is pressed and turned on in time with an appropriate time signal, the 0-regulation signal generator 10 generates a clock signal cl and a reset signal R.

Here, if the second content of the second counter 3 is 24 seconds or more, the comparator circuit 9 detects this and outputs a logical value 11.

If the output of the comparison circuit 9 has a logical value of 1, the clock signal cl inputs a carry signal to the component counter 4 via the AND gate AND and the exclusive OR gate Ex-OR. Conversely, the second content of second counter 3 is 2.
If the time is less than 4 seconds, the output of the comparator circuit 9 has a logical value of 0, and no carry signal is input to the component force counter 4. In other words, the zero standard here is that when pressing the switch S in time with the time signal, if the contents of the second counter 3 are less than 24 seconds, the clock is considered to be ahead, and the second counter 3 is reset to 0 to set it to the hour. If it is 24 seconds or more, it is considered that there is a delay, and the second counter 3 is reset to 0, and at the same time, the minute force counter 4 is reset.
A carry signal is input to the counter, one minute is added to the contents of the component force counter 4, and counting is restarted immediately thereafter.

On the other hand, if it has been less than 30 days since the previous 0 standard,
Since the output d3 of the counter 11 has a logical value of 0, the inverter ln. One side of the AND gate AND2 is set to logic value 1 through
Therefore, the clock signal cl is transferred to the buffer memory 7.
is input to the cl terminal of.

On the other hand, if sewing has been carried out for more than 30 days, the output d30 of the counter 11 has a logical value of 1, so the clock signal cl is not input to the cl terminal of the buffer memory 7. That is, the output d30 of the counter 11 has a logic value of 0, and the clock signal c
Only when 1 is input to the buffer memory 7, the buffer memory 7 starts the seconds counter 3 at the rising edge of the clock signal cl.
Read and store the BCD output.

The reset signal R becomes a logic value 1 after the clock signal cl becomes a logic value 0, and the reset signal R becomes a logic value 1 after the clock signal cl becomes a logic value 0.
Reset to 0.

When the reset signal R becomes a logical value 0, the reset of the second counter 3 and the counter 11 is released, and the second counter 3 restarts counting with the one second signal s, and the counter 11 restarts counting with the day signal d. The numerical value of the contents stored in the buffer memory 7 is detected by the numerical value detection gate circuit 12,
Logical value 1 from the corresponding second detection signal C,, C2...CI,
Output.

For example, if a value of 4 to 8 seconds is detected, the second detection signal C
, outputs a logical value of 1. In the first rate correction amount selection gate circuit 14, the correction reference signal F is input to the delay correction signal generation circuit 16 based on the second detection signal C. FIG. 4 is a time chart for explaining the operation of the delay correction signal generation circuit 16.

The NAND gate NAND, 6 is the reference signal fo of the oscillation circuit 1.
The inverted signal fo, the output signal fo/2 of the second and third stage T-type flip-flops FF2, FF22 of the frequency dividing circuit 2
, fo/4, and fo・(fo/2)・(fo/4
). When the D terminal of the D-type flip-flop FF,6- becomes a logical value 1, the NAND gate NAND. 6
At the first rising edge of the output, a logic value 1 is output to its Q terminal (time chart Q, 6-,), and at the next rising edge, a logic value is also output to the Q terminal of the D-type flip-flop FF, 6-2 in the next stage. 1 is output (time chart Q, 6-2). The AND gate AND,6 is connected to the Q,6-.・Q. Delay correction signal P by using the logic of 6-2
Output as d. The delay correction signal Pd is the output signal fo/
4, and the output signal fo/4
In order to reach the logical value 1 between two consecutive logical values 1, if the logic of Pd + fo/4 is taken by the OR gate, one of the output signals fo/4 as shown in the time chart. Erase the logic value 1 pulse.

For example, if the correction reference signal F is input to the delayed positive signal generation circuit 16 as described above, the correction reference signal F will generate one pulse every 60 seconds.
One logic value 1 pulse of the output signal fo/4 is erased once every minute. When one logic value 1 pulse of output signal fo/4 is erased, there is a delay of 4/3276 0 seconds. Therefore, if one pulse per minute is input to the delay correction signal generation circuit 16, 60×60×24×
1/60=144 hard logical value 1 pulse is erased and 4/
32768 x 1440 = 0.17 mother sand delayed. If one month is calculated as 30 days, 0.176 x 30 = 5.2
Current sand can be delayed.

When the numerical value detection gate circuit 12 detects 9 to 1 mirror sand and the second detection signal C2 becomes a logical value 1, the correction reference signal F2 is input to the delay correction signal generation circuit 13, and the output signal fo/ The logical value 1 pulse of 4 is the correction reference signal F,
Since it is erased twice as much as in , it can be delayed by 10.56 seconds per month. Similarly, when the numerical value detection gate circuit 12 detects 14 to 1 mirror sand and 19 to 2 phantom sand, the delay can be delayed by 15.84 seconds and 21.12 seconds, respectively, per month. In the numerical value detection gate circuit 12, 24-2 nail sand, 27-31 seconds, 32-3 competitive selection, 37-
41 seconds, 42-4 mother sand, 47-51 seconds, 52-5 When the competitive sand is detected, each second detection signal C5, C6,...
・、C、． is output as a logical value of 1.

In the rate correction amount selection gate circuit 15, second detection signals C5, C6, . . . , C, . Correspondingly, the rash correction reference signals F7, F6, . . . , F, are output as Pf', respectively. The operation of the advanced failure signal generating circuit 17 will be explained with reference to the time chart of FIG.

The D terminal of the D-type flip-flop FF, 7-, has a logic value of 1.
Then, at the first rise of the output signal fo/4, the Q terminal output outputs a logic value of 1 (time chart Q,7-・
), at the next rising edge, the Q terminal output of the D-type flip-flop FF, 8-2 outputs a logic value of 1 (time chart Q,
7-2), AND gate AND. 7-, is Q, 7-.・
QQ, take the logic of 7-2 and gate AND, ? -2
Enter. AND gate AND, 7-2 is further Q, 7
−．・Q, 7-2 ・fo/su ・f both ・The period when the output signal fo/4 has a pulse corresponding to 1/2 period of the reference signal fo by taking the logic of fo and the output signal fo/4 has a logic value of 0. A positive signal Pf is output after the advance becomes logical value 1. When the logic of fo/40Pf is taken by the OR gate OR, one logical value 1 pulse is added to the output signal fo/4.

This is performed every time Pf' input to the advance correction signal generating circuit 17 becomes a logical value 1. Therefore, if calculated in the same way as above, 24 to 26 seconds will be detected, and when inputting the correction reference signal F7, 36.96 seconds per month, 27 to 26 seconds per month will be detected.
When detecting 31 seconds and inputting the correction reference signal F6, 31. Total seconds, 32-3 Reisha, 37-41 seconds, 42-4
When detecting 47 to 51 seconds and 52 to 56 seconds of less food, 26.4 fewer baits per month, 21.12 steps,
It is possible to advance by 15.84 seconds, 10.56 seconds, and 5.28 seconds. Note that the correction signals F,,F2,...,F7 are obtained by inputting the BCD output of the second counter 3 to the correction reference signal generation decoder 9, so the time intervals are not exactly every minute. The error is almost ignored.

Table 4 shows the rate correction of this watch.

In Table 4, "-" indicates delay, "11" indicates advance, and "1" or "11" in the correction time means that the clock is operated to delay or advance by that value.After correction The error means that due to the correction mentioned above, the apparent delay or advance has become the value corresponding to the contents of seconds at the time of each operation.Also, the delay time is equal to the contents of seconds at the time of operation. It is shown in parentheses. Table 4: Rate correction - As is clear from the table, the rate after correction can be within the range of approximately 3 seconds/month, and the rate of the clock can be adjusted without correction. In other words, in Table 4, the seconds at the time of operation are set to 0 to 3 seconds or 57 to 59 seconds.

Now, in general, an oscillation circuit that is a coarse combination of a crystal resonator and a C-MOS inverter tends to lag, and if the boundary value for determining lag/advance is set to 24 seconds, the clock will be ahead by 2 seconds or 3 times behind, but at least Assuming it will take 30 days,
By performing the zero-setting operation approximately every 30 days, you can expect almost accurate hourly time, including the carry to the minute counter 4.

However, here, as described above, at the same time as the zero standard operation, the rate is corrected according to the seconds at the time of the zero standard. However, since the last zero calibration, the next zero
If it takes a long time to perform the adjustment, the cumulative error will become very large, and there will be a strong possibility that the user will attempt to distinguish between a lag and a lead when correcting the rate. For example, in the case of a clock with a lead of 5 and a sand with a lag of 5 during zero-normal operation, it is determined that there is a sand with a lag of 1 and a cram school with a lead of 1, and the clock that tends to advance is more A clock that tends to advance or lag may end up adjusting its rate to become even more delayed. As described above, in this device, reading of the buffer memory 7 is controlled by the output d30 of the counter 11, and the contents of the buffer memory 7 are not rewritten for 30 days or more.

In other words, if the period from the previous zero adjustment to the next zero adjustment is 30 days or more, only the zero adjustment is performed and no rate correction is performed. Therefore, this device effectively prevents the rate from being corrected in at least the intended direction. In addition, if the period for performing the zero adjustment is long, the determination of the delay or advance in the zero adjustment may be compromised and the content may be one minute short or one minute surplus, but this is due to the time adjustment mechanism (not shown). It can be easily corrected, and it is not necessary to control the zero-normalization operation using the output d30 of the counter 11 in the same way as rate correction. Also, the reason why it takes a long time to perform zero adjustment is because the current clock has a small rate, and in such cases, there is no need to correct the rate and it is sufficient to perform zero adjustment. Therefore, this device is convenient and very useful. As described above, in this embodiment, the boundary value for determining whether the clock is ahead or behind is set to 24 seconds, and it is assumed that it takes at least 30 days for the clock to advance by two or three times, but other setting values and other periods may be used. But of course it is possible.

In addition, by arbitrarily setting the second content detection range during zero-normal operation, the reference signal for correction, and the division stage controlled by the reference signal for correction, it is also possible to obtain still another preferable speed adjustment device. As described above, according to the present invention, the adjustment device can be digitized and built into a single LSI chip etc. together with other watch circuits, which is very useful for electronic wristwatches etc. with limited mounting area, and it is also convenient for the user. To provide a convenient speed adjustment device capable of simultaneously adjusting zero and rate by simply operating it by hand according to a time signal.

In addition, when correcting the rate, it is possible that the period of the zero-normalization operation may cause the rate to be further deviated due to incorrect determination of lead/lag, but in the present invention, when the period is long, reading of the seconds to be compared is prevented. , the rate will not be adjusted in the wrong direction.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a more specific block diagram showing the delay correction signal generation circuit 16 of FIG. 1. 3 is a more specific block diagram showing the advance correction signal generation circuit 17 of FIG. 1, FIG. 4 is a time chart showing the signal waveforms of each part of FIG. 2, and FIG. It is a time chart showing signal waveforms of various parts. 1...Oscillation circuit, 2...Divide circuit, 3
...Second counter, 4...Component force counter, 7...Buffer memory, 8...Decoder for generating reference signal for correction, 9...Comparison circuit, 10. ...0
Regulation signal generator, 11... Counter for rate correction control, 12... Numerical detection gate circuit, 13.
...Reference signal generation circuit for rash correction, 14...
First rate correction amount selection gate circuit, 15...Second
Rate correction amount selection gate circuit, 16...delay correction signal generation circuit, 17...advance correction signal generation circuit. Figure 2 Figure Ship Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] 1. A reference signal generating means including a crystal oscillator, a frequency dividing means for dividing the frequency of the reference signal into a low frequency, and a counter for counting the divided output of the low frequency and measuring time information such as seconds, minutes, hours, etc. In an electronic timepiece comprising: a zero adjustment means for resetting the second content of the second counter to 0 by operating a switch, and controlling carry-up to the minute counter according to the second content at the time of operating the switch; means, a rate correction means for reading the second content at the time of operation of the switch, and controlling the number of pulses to be deleted or added to the high frequency frequency dividing stage output signal in the frequency dividing means based on the second content; a zero-normal operation period counter means for counting the period during which the zero-normal operation is performed, and when the zero-normal operation period counter means counts a certain period or more, the rate correcting means calculates the period when the switch is operated. An electronic timepiece characterized by having a configuration that prevents reading of seconds contents.