JPS603565A - Testing device - Google Patents

Abstract

PURPOSE:To exert no influence on others whichever is set, by providing the fourth circuit for generating a phase setting signal by inputting a signal of the first and the third circuits, and the fifth circuit for generating a variable phase output signal by inputting the second and the fourth circuits. CONSTITUTION:A frequency fi1 set by a frequency setting part 1 is outputted from a frequency oscillating part 2, and this frequency is divided by a frequency circuit 10, becomes fi2 and is outputted. A phase signal generating part 5 generates an output pulse following a set value of a phase angle setting device 4. Also, an input of a counter circuit 6(1) is only a frequency input of fi2, therefore, generates an output to a zero detecting circuit 7. The phase signal generating part 5 starts a count of an input frequency of fi1, and when it conforms with an output value of the phase setting part 4, a zero resetting signal is outputted to a counter circuit 6(2). As a result, the counter circuit 6(2) executes a motion governed by an output pulse of the phase signal generating part 5. Accordingly, the input frequency of fi2 executes a function for only sending said signal as an address signal to an ROM8(2), and becomes a motion of a variable phase outputting circuit.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a test device for measuring the frequency alignment and phase characteristics of electrical equipment, etc., and digitally measures the frequency and the phase angle of two alternating current electrical quantities. The present invention relates to a test device that can set and output frequency and phase angle independently of each other.

[Technical background of the invention and its problems] Figure 1 shows an example of a conventional test device used as a signal source of alternating current electricity for measuring frequency characteristics, phase characteristics, etc. of electrical equipment, etc. It is something. In the figure, 1 is a frequency setting section for digitally setting the frequency, and 2 is a frequency oscillation section that oscillates a frequency f11 according to a setting value output from this frequency setting section 1. The relationship with the final output frequency f0 of the device is as shown in the following equation.

fo=f,
is the full count value.

3 is a frequency multiplier, and the relationship between this output frequency fI2 and the final output frequency f0 is fI2=fo
-(2) This fI2 becomes the input frequency of the phase control section.

The meaning of the above expression is n! When =1, fI is 360 times fo. This allows the phase control to be f. It is possible to perform setting at intervals of 1°.

4 is a phase setting section, and 5 is a phase signal generation section. This circuit includes a counter circuit that counts the input frequency f12 (counts up to 360xn2), and a counter circuit that receives the output signal of the zero detection circuit 7, which will be described later. , a reset circuit that resets this counter circuit to zero, and an output circuit that generates an output pulse of this circuit when the counter output and the output signal of the phase setting section 4 match, and this output signal counter circuit 7 (2), which will be described later.
).

6(1) is a counter circuit (for reference phase circuit) for counting fl1, and 7 is a zero detection circuit that generates an output pulse when the output of the counter circuit 6(1) becomes zero. Further, 6(2) is a counter circuit for counting fu, but is a counter circuit for a variable phase circuit which has a feature that it is initialized by the output signal of the phase signal generating section 5. With such a configuration, the counter circuit 6(2)
Compared to the counter circuit 6(1), the settled phase Kumon performs counting with a delay, thereby making it possible to settle the phase difference.

8(1) and 8(2) are ROMs (read only memories), which use the output signal of counter circuit 6 (IL) as an address signal input and output the waveform contents written in the ROM as output data. 9(1) and 9(2) are D/A converters, counter circuit 6(1), ROM 8
The output signal of (2) is digital-to-analog converted and output as an analog waveform.

With the above configuration, even if the frequency setting is changed, the phases of the two electric quantities are not affected, and even if the phases are changed, the setting frequency is not affected. However, since the frequency multiplier 3 uses a PLL circuit (phase-locked loop circuit) or the like, it has the disadvantage that if the input frequency changes over a wide range, the circuit operation cannot follow it, making phase settling impossible. .

[Object of the Invention] The present invention has been made in view of the above circumstances, and it is possible to reliably perform phase settling in all regions of the settling frequency as long as the settling frequency is not zero, and to set either the frequency setting or the phase setting. It is an object of the present invention to provide a test device that does not have the above-mentioned drawbacks and is equipped with a signal source that does not affect others even when the test is performed.

[Summary of the invention]

The present invention includes a first circuit that generates a digitally set frequency, a second circuit that divides the output frequency of the first circuit, and a third circuit that generates a reference phase output signal by the output of the second circuit. a fourth circuit which inputs the output of the first circuit and the zero detection signal of the third circuit to generate a phase setting signal, and inputs the output of the second circuit and the output of the fourth circuit. The above object is achieved by providing a fifth circuit for generating a variable phase output signal.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings. Second
The figure shows an embodiment of the present invention, in which 1 is a frequency setting section, 2 is a frequency oscillation section that oscillates a frequency fll according to the setting value of the frequency setting section 1, and together with the frequency setting section 1, the first circuit 11 to generate a digitally settled frequency. Reference numeral 12 denotes a second circuit that divides the output of the first circuit 11, and is constituted by the frequency dividing circuit 10. 13 is a third circuit that generates a reference phase output signal based on the output of the second circuit 12, and includes a counter circuit 6 (1), a zero detection circuit 7, and an RO
It is composed of M8(1) and D/A conversion circuit 9(1).

14 is a fourth circuit that receives the zero detection signal from the third circuit 13 and generates a phase setting signal, and includes a phase setting section 4 and s'
11, a phase setting signal of the phase setting section 4, and an output signal of the zero detection circuit 7, the phase signal generating section 5 outputs a heliset signal to a counter circuit 6 (2) to be described later to perform phase control. be done.

The frequency dividing circuit 10 constituting the second circuit 12 above is 'l
It receives an input signal l and generates an output signal f12.

Here, the relationship between fi2 and the modified output frequency f0 is expressed by the following equation.

f+2= f, xnx ・・・・・・・・・・・・(
3) nl in equation (3) is the counter circuit 6(1), 6(2)
) is set to the full count value. Furthermore, fIl and the final output frequency f. To show the relationship, f+s = fo+ 360 x n2. ,,44 songs (
4> n2 in the above equation represents the setting resolution of the phase angle setter, and if n2 = 1, the phase is set at 1° intervals, or n
If 2=10, it is possible to set the angle at intervals of 0.1°.

Also, the relational expression between fll and f12 is f12""-
i; Ding 6(1) is the counter circuit (for reference phase circuit) for counting f12, and 7 is the counter circuit 6(
This is a zero detection circuit that generates an output pulse when the output of 1) becomes zero.

15 is a fifth circuit which generates a variable phase output signal by inputting the output of the second circuit and the output of the fourth circuit, and includes a counter circuit 6 (2), a OM 8 (2), and a conversion circuit It consists of 9(2). The counter circuit 6 (2) is a counter circuit for counting <fez, which is the same as the counter circuit 6 (1), but the phase signal generator 5
The counter circuit 6(2) has a feature that the counter circuit 6(2) is initialized by the output signal of the counter circuit 6(2). With this configuration, the counter circuit 6 (2) counts the settled phase Kumon with a delay compared to the counter circuit 6 (1), making it possible to settle the phase difference. .

The ROMs 8 (1) and 8 (2) use the outputs of the counter circuits 6 (1) and 6 (2) as address signal inputs, and output the waveform contents written in the FLOMs as output data. Further, the D/A conversion circuits 9(1) and 9(2) output the outputs of the ROMs 8(1) and 8(2) as digital-analog waveforms.

This completes the explanation of the configuration, and next the operation of the present invention will be explained. That is, in the present invention, the frequency f, ! is output from the frequency setting section 2. This fll old frequency is divided into 02 × 360- by the frequency dividing circuit 10, and '211':>'I'E17't''・``62・*@
* @ '; 0% #15 input frequency fIl
and the input frequency of the counter 6(1), a frequency difference of 1×''- is generated.

n2 360 The phase signal generator 5 generates an output pulse according to the setting value of the phase angle setter 4. However, the resolution of the setting value is determined by n2, and if n2 = l, then 1° interval, nz = lQ
If so, it is possible to set the angle at intervals of 0.1°.

Further, since the input of the counter circuit 6(1) is only the frequency input fI2, when the frequency f12 is counted, it resets itself and generates an output to the zero detection circuit 7. In other words, the period from when you start counting on your own until it reaches full count is the final output f0.
This is one cycle of Therefore, this counter circuit 6 (
1) becomes the reference phase.

The zero detection circuit 7 is activated by the full count of the counter circuit 6(1), that is, the pulse at the end of the cycle of the counter circuit 6(1), and the counter circuit in the phase signal generator 5 is reset to zero. From that point on, the phase signal generator 5 starts counting the input frequency fIl,
When the output value matches the output value of the phase setting section 4, the phase signal generating section 5 outputs a zero reset signal to the counter circuit 6(2).

As a result, the counter circuit 6(2) is reset to zero by the output pulse of the phase signal generator 5 as described above, and therefore performs a movement dominated by the output pulse of the phase signal generator 5.

Therefore, the input frequency fI2 is
8 (2) It serves only as an address signal and operates the variable phase output circuit.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, by configuring an all-digital circuit before the final output D/A conversion circuit without including an analog system such as a PLL, all frequency ranges other than zero hertz can be processed. Therefore, both the frequency and the phase angle can be set independently, and an effective test device can be provided that does not affect the other components.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional test device, and FIG. 2 is a block diagram showing an embodiment of the present invention. 11...First circuit 12...Second circuit 13...
- Third circuit 14...Fourth circuit 15...Fifth circuit.

Claims (1)

[Claims] a first circuit that generates a digitally set frequency; a second circuit that divides the output frequency of the first circuit; and a second circuit that generates a reference phase output signal by the output of the second circuit. a fourth circuit that generates a phase settling signal by inputting the output of the first circuit and the zero detection signal of the third circuit; and a fifth circuit that generates a variable phase output signal by inputting the output of the circuit, and is characterized in that the frequency and phase angle can be independently varied digitally in a settling frequency range other than zero frequency. Test equipment.