JPH0234203B2 - SHINGOHATSUSEIKI - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a signal generator that supplies two signals: a reference signal and a variable amplitude signal. In particular, the present invention relates to a signal generator capable of changing the amplitude of one output signal within a given range without shifting the phase. For example, in an impedance measuring device such as an LCR meter equipped with a vector ratio detection circuit, linearity in the amplitude and phase of an input signal is checked to evaluate its performance. For this reason, only the amplitude of the input signal is changed and its output is measured in advance. Conventionally, transformers have been used, but they have a limited output frequency range and are extremely difficult to automate. Instead, when the output of the oscillator is divided into resistors using an attenuator or the like, the phase of the output shifts due to the distributed capacitance that exists in parallel between the resistors. The present invention has been made in view of these points. FIG. 1 is a diagram showing the concept of the present invention. a is a pulse waveform centered at time _T1 . this time
Define T ₁ as the pulse center time. b is a composite waveform consisting of the same five pulses as a. The center pulse of b has the same center time T ₁ as a, ie, the same center time T ₁ as a. Therefore, a and b have the same phase, and since they have different energies, they differ only in the amplitude of the fundamental wave determined as described below. If, instead of b, a single pulse waveform having approximately the same composite waveform transition time as b as shown in c is used, the following drawbacks will occur. Normally, due to the charge accumulation effect of the semiconductor switch, the waveform becomes less sharp as shown by P, and its fall time becomes longer. As a result, the pulse waveform of c is not symmetrical, and the center time _T1 is no longer the same as that of a, so that the amplitude changes and the phase shifts at the same time. An embodiment of the signal generator according to the invention is shown in FIG. 2 and will be described in detail below. In this example, 4-bit
Binary counter A, decoder B and AND gate
C ₁ to _{C 8} , OR gate D, inverter E, low-pass filters F ₁ and F ₂ , and monostable multivibrator H
(hereinafter referred to as monostable multi). Here, 1 is a pulse signal input terminal, 2 and 3 are output terminals, and X, Y, and Z are control signal input terminals. Input terminal 1 is connected to a 4-bit binary counter A, and via an inverter E to an AND gate _C8 . MSB of 4-bit binary counter A
The (most significant bit) output (here the output divided by 1/16) is applied to AND gate _C7 ,
In addition, the output terminal ₂ is connected via the low-pass filter F1.
A constant reference signal is output. Other outputs of the 4-bit binary counter A (in this case, outputs frequency-divided into 1/2, 1/4, and 1/8) are applied to decoder B. As shown, decoder B
Of the output terminals 0 to 7, the output terminals 1 to 3 and 5 to 7 are ORed through AND gates C ₁ to _{C 6} , respectively.
Connected to gate D, output terminal 4 is directly connected to decoder B
connected to. Control signal terminals X, Y, and Z are connected as follows. The X terminal is connected to AND gate _C1 .
to C ₆ , Y terminal to AND gates C ₂ and C ₅ , Z terminal to
Connected to AND gates C ₃ and C ₄ . OR gate D
The output of is AND gate C ₇ , C ₈ , monostable multi-H
The signal is applied to the low-pass filter F ₂ via the filter F 2 , and sent to the output terminal 3 . The operation of this embodiment will be explained below using FIG. FIG. 3 shows signals I to I in I shown in FIG. To the input terminal 1, a pulse signal at constant time intervals as shown in FIG. 3A is applied. Signal A is
Next, 1/2 by 4-bit binary counter A
(Least Significant Bit, LSB), 1/4, 1/8, 1/1
The frequency is divided into 6 (MSB). This MSB signal is shown in (b). In this embodiment, three outputs (1/2, 1/4, 1/8) of the 4-bit binary counter A are input to the decoder B. These outputs are displayed in 3 bits and decoded into 0-7. That is, in the output of 0, 0, 0, a signal with a higher level is output from the 0 terminal of decoder B at 2 ⁰ (0) + 2 ¹ (0) + ^{2 2} (0) = 0, and similarly, 1, 0, ,0, 2 ⁰ (1) + 2 ¹ (0)
When +2 ² (0)=1, one terminal of decoder B outputs a high level signal. The control signals applied to the X, Y, and Z terminals are shown in Table 1 below.

[Table] L indicates low level, H indicates high level. The number of pulses is the number of pulses of the output signal of the AND gate _C8 , as described later. When the number of pulses is 1, from Table 1, all low level signals are supplied to the X, Y, and Z terminals, and therefore, OR
Gate D outputs signal C. AND gate _C7 outputs E, which is the AND signal of signals B and H. The signal I inverted by the inverter E is input to the AND gate _C8 . Therefore, the monostable multi-H is triggered when the output of the AND gate _C8 is at a high level, and outputs the signal shown in G having the center time _T1 . Here, since the signal H is a single pulse, the monostable multi-H outputs a single pulse as well. Then, the harmonic components of the signal T are removed by a low-pass filter _F2 , and a fundamental wave, which is a sine wave, can be obtained. The fundamental wave component S ₁ of the output of this low-pass filter F ₂ is expressed by equation (1). S ₁ = 2/π・sinπτ/T・cos (2πft+φ) …(1) Here, T・=1, is 1/16 of the pulse frequency, φ is the phase shift by the low-pass filter F ₂ ,
The height of the pulse is a unit potential (eg 1V). Next, when the control signal for the case where the number of pulses is 5 is applied to the X, Y, and Z terminals, L, H,
An H signal is sent. Therefore, OR gate D outputs signal D. As a result of inputting signals B and D to AND gate _C7 , signal H is output. Therefore, while the signal H is at a high level, a signal H consisting of five pulses is output from the monostable multi-H. The center pulse of this signal H also has a center time similar to the center time _T1 of signal G. Then, the signal T passes through the low-pass filter F ₂ as described above to obtain the fundamental wave component S ₂ shown in the following equation (2). This fundamental wave component S ₂ is 2/π sin
π τ/Tcos (2πft+φ) on the time axis, 2T/16,
It is expressed as the sum of the values shifted by T/16, -T/16, and -2T/16. S ₂ = 2/π sin πτ/T _o 〓 ^n=-2 cos (2π(t + nT/16) + φ} = 2/πsin π τ/T (1+2cosπ/8 +2cosπ/4) ・cos (2πt+φ) …( 2) As can be seen by comparing equations (1) and (2), the amplitude of the fundamental wave component S ₂ is equal to ( ₁ +2cosπ/8
+2cosπ/4), and the phase remains unchanged. In other words, as explained in FIG. 1, the center time T ₁ of the center pulses T and T does not change. In this way, it is possible to obtain a signal whose phase does not change, but whose amplitude is varied by a known value according to the control signal. In the case of 3 and 7 pulses, signals differing only in amplitude are obtained from the output terminal 3 in the same manner. The width τ of the output pulse of the monostable multi-H is set to a value smaller than the period of the pulse signal. This is because when the pulse width τ is larger than the pulse period, the second transition time of the final pulse of the signal Q is delayed, that is, it is no longer symmetrical at the center time T ₁ of the center pulse, and the phase changes. In addition, monostable multi-H makes the period of high level (logic 1) as long as possible in one cycle of signal A.
That is, it is used to obtain higher energy, so it is not necessarily necessary. Therefore, instead of this embodiment, the output of the AND gate _C8 may be applied directly to the low-pass filter _F2 . As explained above, in this embodiment, the fundamental wave component from the signal B is supplied to the output terminal 2 via the low-pass filter _F1 , and its phase and amplitude are known and always constant. The output terminal 3 is then supplied with a signal having a known amplitude and no phase shift determined by the control signals applied to the X, Y, and Z terminals, as described in detail. In FIG. 2, the 4-bit binary counter A is used to divide the signal A into 16 equal parts at most, but the present invention is not limited to this, and any number of equal parts may be used as long as the number is 4 or more.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the concept of the present invention. FIG. 2 is a circuit diagram of an embodiment of a signal generator according to the present invention. FIG. 3 is a diagram showing signal waveforms at various parts in FIG. 2. A: 4-bit binary counter, B: decode, _C1 to _C8 : AND gate, D: OR gate,
E: Inverter, F ₁ , F ₂ : Low pass filter,
H: Monostable multivibrator.

Claims (1)

[Claims] 1. Frequency dividing means for generating a plurality of frequency division signals having different frequency division ratios from an input pulse signal;
decoding means for decoding the plurality of frequency-divided signals excluding the minimum frequency signal; and selectively combining the plurality of output signals of the decoding means in response to a control signal to obtain a desired pulse width having a fixed pulse center time. combining means for outputting a signal; gate means for passing the input pulse signal for a time equal to the pulse width of the output signal of the combination means; and harmonic components of the minimum frequency signal and the output signal of the gate means. A signal generator comprising a low-pass filter for removing the signal, wherein the pulse center time of the center pulse of the pulse output signal of the gate means is constant, and only the number of pulses is variable. 2. The signal generator according to claim 1, wherein the gate means comprises an inverter for inverting the input pulse signal and an AND gate to which the output of the combination means and the output of the inverter are connected. . 3. The signal generator according to claim 1, wherein the frequency dividing circuit is a 4-bit binary counter. 4. In the signal generator according to claim 1, the combination means includes a plurality of ANDs to which the output signal of the decoder and the control signal are input.
The present invention is characterized in that it includes a gate, an OR gate to which output signals of the plurality of AND gates are input, and an AND gate to which output signals of the OR gate and the minimum frequency divided signal are input.