JPS57180227A - Signal generator - Google Patents
Signal generatorInfo
- Publication number
- JPS57180227A JPS57180227A JP6540781A JP6540781A JPS57180227A JP S57180227 A JPS57180227 A JP S57180227A JP 6540781 A JP6540781 A JP 6540781A JP 6540781 A JP6540781 A JP 6540781A JP S57180227 A JPS57180227 A JP S57180227A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- output
- signal
- frequency
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
- H03K5/05—Shaping pulses by increasing duration; by decreasing duration by the use of clock signals or other time reference signals
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Pulse Circuits (AREA)
Abstract
PURPOSE:To pick up a signal with constant phase and changing amplitude, by frequency-dividing a clock signal, taking almost the center time of a frequency output as the pulse center, changing the pulse width with a control signal and passing through the pulse to a logical circuit and an LPF. CONSTITUTION:A clock input signal 1 is applied to a 4-bit binary counter A and an inverter E. An MSB output of the counter A outputs 1/16 frequency dividing waveform of the clock frequency at a terminal 2 via an LPFF1 and is applied to an AND gate C7, and another output of the counter is applied to a decoder B. Output terminals 1-7 of the decoder B are connected to AND gates C1-C6 and an OR gate D, and control signal terminals X, Y, and Z are connected to the gate D via a prescribed gate out of the gates C1-C6. The output of the gate D is applied to an AND gate C8 together with the output of the inverter E via a gate C7. The output of the gate C8 is outputted to a terminal 3 via a monostable multivibrator H and an LPFF2. A control signal produces a signal with constant phase and changing amplitude at the terminal 3.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6540781A JPH0234203B2 (en) | 1981-04-28 | 1981-04-28 | SHINGOHATSUSEIKI |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6540781A JPH0234203B2 (en) | 1981-04-28 | 1981-04-28 | SHINGOHATSUSEIKI |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57180227A true JPS57180227A (en) | 1982-11-06 |
JPH0234203B2 JPH0234203B2 (en) | 1990-08-02 |
Family
ID=13286136
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6540781A Expired - Lifetime JPH0234203B2 (en) | 1981-04-28 | 1981-04-28 | SHINGOHATSUSEIKI |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0234203B2 (en) |
-
1981
- 1981-04-28 JP JP6540781A patent/JPH0234203B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH0234203B2 (en) | 1990-08-02 |
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