JPS6034855B2 - Tuning voltage generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a tuning voltage generation circuit used in an electronic channel selection device of a television receiver.

In the electronic tuning device of a television receiver, in order to variably control the output frequency of the local oscillator according to the tuning, the local oscillator is tuned by variably controlling the tuning voltage applied to the variable capacitance diode of the local oscillator. Variable frequency control is commonly practiced. When setting the above-mentioned tuning voltage to a different value for each channel selection, the width of a constant period pulse is modulated according to the channel selection, and this pulse width modulation signal is converted into digital/analog (D/A). A system is being considered in which a DC tuning voltage that changes stepwise in accordance with the channel selection is generated. In this case, the amount of change in the tuning voltage is usually several mV (approximately 7 mV) in order to obtain clear changes in the television image, and the greater the number of stepwise changes in the tuning voltage, the more fine tuning adjustment is possible. It is. If the number of stepwise changes is fixed at about 410M and pulse width modulation is performed by counter output, at least 212=4096 changes can be obtained by using a counter circuit of 12 bits or more. This counter circuit is a MOS
If it were to be realized with an IC, the maximum operating frequency with current mass production technology is approximately 8 MHz, so if a 12-bit counter circuit is configured and the clock frequency is selected to 4.098 MHz, the frequency of the divided output will be 1 kHz. Become.

The duty of this frequency-divided output, in other words, the pulse width, is changed in 4.096 steps according to the channel selection, and this pulse is D/A converted to 4.096 steps in 7 mV units.
Obtaining a change of 96 steps results in a tuning voltage change range of approximately 28.5V (7mV x 4.096). By the way, when the frequency-divided output of the above-mentioned counter circuit is subjected to D/A conversion by a low-frequency wave generator, the ripple of this wave wave output must be about 0.8 hV or less.

This is because unless the ripple of the tuning voltage is about 0.8 hV or less, a change in the image on the television screen will be visually detected due to the IJ pull. Therefore, as a condition for the low frequency reactor, the pulse frequency lk with a pulse duty of 50% is
With HZ as the center frequency, the attenuation amount of the ripple frequency must be 0.6 mV/28.5 V, that is, 18 mother B or more, relative to the attenuation amount of the frequency that generates the maximum tuning voltage of 28.5 V. However, in order to obtain such a large amount of attenuation in the low frequency range, the configuration of the reactor waver needs to be complicated with multi-stage connections, and the time constant becomes large, resulting in an increase in delay time and insertion loss. Therefore, the counting operation of the counter circuit is controlled to continuously change the frequency-divided output pulse width, the tuning voltage by D/A conversion is changed in a sweep manner to perform reception tuning, and the above-mentioned sweeping is stopped by the tuning detection output. When performing closed loop control, the delay time of the wave generator is long, so the transient response becomes slow and the tuning voltage at the time of stopping the sweep and the actual tuning voltage at the time of tuning detection deviate. The present invention has been made in view of the above-mentioned circumstances, and provides attenuation of a furnace wave generator for generating a tuning DC voltage by D/A converting a pulse width modulation signal having a pulse width corresponding to tuning frequency information. An object of the present invention is to provide a tuning voltage generating circuit that can be easily set, simplify the configuration of a wave generator, and shorten delay time.

An embodiment of the present invention will be described in detail below with reference to the drawings.

First, the basic configuration of a pulse width modulation type tuning voltage generation circuit will be explained.

In FIG. 1, reference numeral 11 denotes a clock pulse generation circuit, and the output of this circuit is led as a count input to a master counter circuit 12 and is converted into a predetermined low-speed clock pulse by a frequency divider 13.

This slow clock pulse is directed as a count input to the sweep counter circuit 14. The count output of this sweep counter circuit 14 is read into a memory circuit 15 by a preset command, and the read output of this memory circuit 15 and the count output of the master counter circuit 12 are respectively led to a comparison circuit 16 as comparison inputs. The comparison circuit 16 generates a match output when the two comparison inputs match, and provides it as a set input to the latch circuit 17. Further, this latch circuit 17 receives the count output "0" of the master counter circuit 12 as a set input, and the latch output is guided to a low frequency wave generator 19 via a pulse amplification circuit 18. The output tuning voltage of this wave generator 19 is the tuner 2
The variable capacitance diode of the local oscillator of 0 is applied.
The tuning detection output of the tuner 20, that is, the AFT signal, is then led to a discrimination circuit 21, which discriminates the AFT signal, and causes the sweep counter circuit 14 to perform a count-up operation or a count-down operation depending on the direction of the tuning deviation. setting, and generates a discrimination output that stops the counting operation when synchronization is completely achieved. Next, the operation of the tuning voltage generating circuit will be explained.

For convenience of explanation, the resolution of the counter circuits 12 and 14 is 4 bits each, and the sweep counter circuit 1
It is assumed that the count output of 4 passes through the memory circuit 15 as it is and is led to the comparison circuit 16. In FIG. 2, the flip-flop circuit (FFO to FF3) corresponds to the master counter circuit 12, and its input clock pulse is CP.
, and the flip-flop circuits FFIO to FF1
3 corresponds to the sweep counter circuit 14, and its input clock pulse is CP2. The outputs Qo to Q3 of the flip-flop circuits FFO to FF3 and the outputs Q, o to Q, 3 of the flip-flop circuits FFIO to FF13 are compared in a comparison circuit 16, and if they match, a match output COR is output.
is generated and becomes the reset input of the latch circuit 17. Further, the count output "0" of the master counter circuit 12 is detected by the NOR circuit 22, and this detection output ±6S becomes the set input of the latch circuit 17. Thus, the output clock pulse CP of the clock pulse generator 11 is the third clock pulse CP.
As shown in the figure, this clock pulse CP,
is guided to the frequency divider 13 to obtain the low-speed clock pulse C
The output of P2 counted by the sweep counter circuit 14 is now as shown in Fig. 3 (Q, o, Q river Q, 2, Q,
3)=(1,0,0,1=9).

Therefore, the count output of the master counter circuit 12 becomes "0" at the 0th clock pulse CP, and this becomes /
The latch circuit 17 is set by the output SS of the latch circuit 22. and clock pulse CP,
As shown in FIG. 3, the count output of the master counter circuit 12 at the 9th point of
, 0, 1 = 9), the comparison circuit 16 generates a coincidence output COR as shown in FIG. Output RQ is generated. Then, the master counter circuit 12 generates clock pulses 0 to 1 for 16 bits.
After counting 5, when the next clock pulse 0 is counted again, the latch circuit 17 is set again by the detection output SS of the NOR circuit 22, and eventually the frequency of the latch output RQ of the latch circuit 17, in other words, the period becomes the master clock. A constant value T is determined by the time required for one cycle of the counting operation of the counter circuit 12. Next, the count output of the sweep counter circuit 14, o to Q, 3 are (0, 1, 0, 1 = 10)
Then, the pulse width upper 2 of the latch output RQ is determined in one cycle of the counting operation of clock pulses 0 to 10. In this way, the pulse width of the latch output is modulated by the count output of the sweep counter circuit 14. The pulse width modulated latch output is made constant in peak value by the pulse amplification circuit 18, passes through the pulse processing circuit 23, is D/A converted by the low frequency wave generator 19, and becomes a tuning DC voltage. This wave generator 19 derives the DC component of the input pulse, and the level of the output is determined by the width of the input pulse, assuming that the peak value and period of the input pulse are constant. Therefore, this pulse width changes in a sweeping manner as the sweep counter circuit 14 performs the counting operation, the tuning voltage also changes in a sweeping manner, and the local frequency of the tuner 20 changes in a sweeping manner. In the process of this sweep change, an AFT signal corresponding to the reception tuning state is generated, and when this AFT signal is discriminated by the discrimination circuit 21, the discrimination output causes the sweep counter circuit 1 to
The counting operation of 4 is controlled to obtain a reception tuning operation. Therefore, the above-mentioned sweep operation is performed for each selected channel, and the count output of the sweep counter circuit 14 at the time of reception tuning is read into the memory circuit 15 and preset by a preset command, and the reselection of the preset channel is performed. In this case, by reading the preset information of the selected channel from the memory circuit 15 and applying it to the comparison circuit 16, reception tuning for this reselected channel can be performed immediately.

By the way, in the present invention, the frequency of the clock pulse CP is, for example, 4.098 MHz, and each of the counter circuits 12 and 14 is of, for example, 12 bits.
When the latch output frequency is low such as lkHz, the latch output is pulse-amplified and directly output to D by the low frequency wave generator 19.
The pulse processing circuit 23 is designed so that there is no problem in terms of the structure and characteristics of the wave generator 19 even if /A conversion is attempted, and the pulse processing circuit 23 will be explained below.

FIG. 4 shows the pulse processing circuit 23, 41'
It is a flip-flop, and alternately generates an ON "1" and an OFF "0" output every time a switching pulse is input.

This switching pulse is 0 in the master counter circuit 12.
→This occurs every time the count operation goes around until 0.
For example, the pulse SS is used. The output of the flip-flop 41 is stored in a memory 42.
The read output of this memory 42 is guided to a pulse width conversion circuit 43. A pulse width modulation signal PWM outputted from the pulse amplification circuit 18 and a clock pulse CP synchronized therewith are also guided to this circuit 43. FIG. 5 shows the waveforms of the pulse width modulated signals A to E and F and the clock pulse CP, which are swept so that the pulse width gradually increases with time. By the way, the pulse width conversion circuit 43 is composed of NAND circuits NA, NOR circuits NR, NR.
2, NR3, and a combination of inverter circuits 1, 12.

If the output of the flip-flop 41 is now "1" and the readout output of the memory 42 is also "1", then this "1"
” is added, the output of the NAND circuit NR2 becomes “0”, but in the NAND circuit NA, the pulse width modulation signal PW
M and clock pulse CP are NANDed, further inverted by inverter circuit 1, and guided to one input of NOR circuit NR3. Since "0" is added from the NOR circuit NR2 to the other input of this NOR circuit NR3, when one input of this NOR circuit NR3 is "1", the output becomes "0", and this is the inverter circuit 12. It is inverted to "1" and derived. Therefore, corresponding to the pulse width modulated signals A to E, the pulse width conversion circuit 43 obtains converted pulses ~Eo as shown in FIG. 5. Then, when the pulse duty of the pulse width modulation signal changes from 0 to 1, that is, the counting operation of the master counter circuit 12 completes one cycle from 0 to 0, a switching pulse SS is generated and the output of the flip-flop 41 is inverted and becomes "0". .

Therefore, the output of the NAND circuit NA becomes "1", which is inverted to "0" by the inverter circuit 1 and is applied to one input of the NOR circuit NR3. On the other hand, the pulse width modulated signals F to J and the clock pulse CP are generated by the NOR circuit NR. So/A is taken, and further NOR circuits NR2, NR3
, the converted pulses Fo to Jo as shown in FIG. 5 are obtained through the inverter circuit 12. That is, each time the master counter circuit 12 completes one round of counting operation, the flip-flop 4
1. The first step is to invert the output of the memory 42 and control the conversion circuit 43 to gradually increase the number of pulses within a certain period like pulses Ao to Eo until it reaches the same period as the clock pulse CP. Period and pulse Fo~Jo
Each “0” section of the clock pulse CP is sequentially changed to “1” as shown below.
The pulse duty can be changed from 0 to 100% in two sweep periods by alternately obtaining the second period of sweeping so as to change to ``. Kirifusuma (Kirifusuma of the tuning circuit that provides the tuning voltage.

), it becomes possible to subtract the pulse width modulation signal PWM twice for each band. Now, assuming that the master counter circuit 12 has 12 bits and the input clock CP is 4 MHZ, the pulse width modulation signal PWM
The frequency is about 1kHz, and therefore the period is about 1ms. When 2MH2 is used as the clock pulse CP, the pulse A is generated in the first period. There is one pulse with a pulse width of 250 ps during one period (lms), and the pulse Co is 25
Two pulses are generated at an interval of 0 peaks, the number of pulses increases as the pulse is swept, and finally becomes a pulse Eo with a frequency of 2 MHZ, the same as the clock pulse CP. In the second period,
Since the "0" sections of the pulse output, such as pulses Fo to Jo, are sequentially changed to "1", the frequency gradually decreases from 2 MHZ. Even in the period of shift and shift, the period is lms except for pulses Eo and Jo during the sweep, but the period is 2 ms.
Since it has the MHZ clock pulse CP component, the frequency component is high, and the IKHZ fundamental wave component is greatly reduced. Therefore, the pulse output PWM converted into pulses in this way is
When the signal ' is converted from D/A by the low frequency wave generator 19, the characteristic of the wave wave converter 19 is that a DC component with small ripple can be obtained in the low range without having to have a very large amount of attenuation. For example, for a pulse width modulated signal PWM as shown in FIG. 6, the pulse output PWM is converted into a pulse as shown in FIG.
', in the section W where the pulse is output, "1", "0"
” are alternate, so the area of the “1” section is 1/2 compared to the original pulse width modulation signal PWM, and the amplitude of the fundamental wave component is also 1/2. Therefore, along with the above pulse conversion process, The amount of attenuation of the fundamental wave component can be obtained in a consistent manner.Also, as the frequency increases, the attenuation amount of the low frequency wave generator 19 increases rapidly as shown in Fig. 7, so the configuration of the low frequency wave generator 19 is simple The pulse width modulation signal is swept to sweep the tuning voltage, and the tuning detection output is fed back to perform sweep control.In the tuning loop, the sweep speed increases and the bridge voltage and the transient response become more distant. The voltage difference from the sweep stop voltage at the tuning point becomes small.In the above embodiment, the clock pulse input CP of the master counter circuit 12 is 4 MHz, whereas the clock pulse input CP of the pulse processing circuit 23 is 1/2, 2 MHZ. Therefore, as shown in FIG. 5, the number of converted pulses Ao to Eo changes as 1, 1, 2, 2, 3, 3, etc. according to the step change of the pulse width modulation signal PWM. The change in the number of conversion pulses F. to J. is n,
It changes like n, n-1, n-1, n-2, n-2... On the other hand, if the clock pulse input CP of the pulse processing circuit 23 is set to 4 MHZ like CP, the converted pulses Ao, Bo, and C are generated as shown in FIG. The number of pulses changes as 1, 2, 3...'n, n-1, n-2.... Conversely, if the frequency of the clock pulse CP is very slow, for example 64kHz, the master counter circuit 1 that generates the pulse width modulation signal PWM
Assuming that there is a resolution of 2=4,096 steps, one period of the clock pulse CP corresponds to 64 steps.

Therefore, when the pulse modulation signal PWM is converted using this clock pulse CP, the output is "1" for the first 32 steps, "0" for the next 32 steps, and every 32 steps thereafter. “1”,“
0" appears.Then, when the converted pulse changes from to to Co and reaches 64kHz, the next output pulse is D.,Eo..., 64 step intervals of "0" are displayed one step at a time. 1. At this time, the section where the output does not change even if the step increases, that is, the conversion pulse A
. ~In the “0” interval during Ao to Co until Do reaches 64kHz2 and in the “1” interval after Do when the output becomes all “1” from the 64kHz pulse, if the pulse width modulation speed is increased, it will stop. There will be less time. For example, if the pulse width modulation is swept at 1kHz in the section where the output changes, then in the section where the output does not change, for example, 64
If it is set to kHz, the rest period becomes 1/64, which is the same as the time required for one step change in pulse width modulation, and D/
It has almost no effect on A conversion. The above-mentioned switching of the sweep speed is achieved by changing the input clock frequency of the sweep counter circuit 14, which determines the sweep speed of the pulse width modulation signal, by a logic circuit including a /A circuit, a NAND circuit, and an inverter circuit as shown in FIG. This can be implemented by switching to different Cs or CFs. in this case,
Input M is the readout output of the memory 42, and is used for switching to make the sweep of the "0" section faster or to make the sweep of the "1" section farther depending on the first and second periods of the sweep. Of course, the above pulse width processing may be performed before pulse amplification.

As described above, the present invention makes it possible to easily set the attenuation amount of a furnace wave generator for generating a tuning DC voltage by D/A converting a pulse width modulation signal having a pulse width corresponding to tuning frequency information. It is possible to provide a tuning voltage generation circuit that can perform the following steps, simplify the configuration of the wave generator, and shorten the delay time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the tuning voltage generation circuit according to the present invention, FIG. 2 is a configuration explanatory diagram showing the pulse width modulation signal generation section taken out from FIG. 1, and FIG. 3 is the diagram shown in FIG. 2. The timing chart shown to explain the operation of
Fig. 4 is a configuration explanatory diagram showing an example of the pulse processing circuit shown in Fig. 1, Fig. 5 is a timing chart shown to explain the operation of Fig. 4, and Fig. 6 is a basic diagram of the operation of Fig. 5. FIG. 7 is a diagram showing an example of the characteristics of the low-frequency wave generator shown in FIG. 1, and FIG.
9 and 9 are diagrams respectively shown to explain a modification of the operation of FIG. 4, and FIG. 10 is a logic circuit diagram showing an example of the sweep speed switching control means of FIG. 2. 12... Master counter circuit, 14... Sweep counter circuit, 16... Comparison circuit, 17.
...Latch circuit, 19...Low frequency wave generator,
23...Pulse processing circuit. Figure 1 Figure 2 Figure 3 Figure 4 Figure 6 Figure 5 Figure 7 Figure 8 Figure 9 Figure 10

Claims (1)

[Claims] 1. A pulse width modulation signal generation means for generating a pulse width modulation signal of a constant period whose pulse width is modulated according to tuning frequency information, and a pulse width modulation signal generated by this means. a pulse processing means for converting a pulse section into a clock pulse of a predetermined period in a sweep period and sequentially converting a "0" section of a clock pulse into a "1" in a subsequent sweep period; D/A
1. A tuning voltage generation circuit comprising: a filter that converts and generates a tuning DC voltage. 2. Claim 1 comprising control means for causing the processing operation of the pulse processing means to be performed every time the tuning band is switched.
Tuning voltage generation circuit described in section.