JPS6033742A - Pass band adjusting circuit - Google Patents

Abstract

PURPOSE:To decrease mixers relating to frequency conversion by adding frequencies by means of addition of digital quantity. CONSTITUTION:The level of a control signal to a VCO17 and an A/D converter 23 is increased/decreased by adjusting a variable resistor 21 for width. Further, a variable resistor 22 for shift gives a control signal to an A/D converter 24 and a VCO18. The A/D converters 23, 24 convert the control signal inputted from the variable resistor 21 for width and the variable resistor 22 for shift into a digital quantity, which is outputted to a digital adder 25 via data buses 23a, 24a. The digital adder 25 inputs the program information formed by a pulse integration counter 15 via a data bus 15a, adds the program information and the digital quantity of the data buses 23a, 24a and transmits the result to a programmable counter 14 of a PLL circuit 8 via a data bus 25a.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a passband adjustment circuit, and in particular has a function generally called shift and width for removing interference signals adjacent to a desired signal. The present invention relates to a passband adjustment circuit applied to a machine.

Usually, a communication receiver has an occupied frequency bandwidth determined according to the radio wave format, and various circuits are provided according to the format of the received signal f1 so that this occupied frequency bandwidth can pass through the receiving circuit. Uke M side defeat ^+fl WQ
la Am 4 HFI 1/ New LjL lr-
w-=-+1 N Rp' It is composed of a unit 2, a mixer 3, a bandpass filter 4, a mixer 5, a bandpass filter and a demodulator 7. Mixer 3-5 from local side terminals 3a, 5a, 7m of mixers 3, 5 and demodulator 7
The frequency of each oscillation signal injected into the demodulator 7 and the characteristics of the Pandonoss filters 4 and 5 determine the passband of the selected received signal.

The first and second filters are installed in the front and rear stages of the pantone filter.
The second frequency conversion means, that is, the bandpass filter 4
If we pay attention to the frequency of the first and second local signals related to the mixers 3 and 4 and the band pass filter 6, the center frequency of the band pass filter and the carrier wave of the received signal fi are Since the positional relationship between
It is possible to perform a quiz operation in which the frequency of the oscillation signal of O17t or vco is deviates from the normal frequency and change the passband width, or a shift operation in which the positional relationship between the center frequency and the carrier wave is changed. The shift and width remove interference signals adjacent to the desired signal.

Generally, a circuit such as a mixer that completely converts the frequency of an oscillation signal has the risk of generating unnecessary harmonics. For this reason, the mixer 3#5 and the demodulator 7 provided in the main path are essential circuits, but the mixers 12 and 13 provided in the PLL loop of the PLL circuit 8 are functionally replaceable. If the circuit can be removed, the multi-signal characteristics can be improved.

In FIG. 1, reference numeral 9Fi phase comparator, 1o a low/bus filter, 11 a VCo, 14 a programmable counter, 15 a pulse integration counter that forms grogram information that determines the division ratio of the programmable counter 15, and 16 a pulse integration counter. The pulse generator 2o is a frequency adjustment dial that determines the number and polarity of the cumulative pulses sent to the pulse generator 16 and the pulse counting counter 5.

The present invention has been made in consideration of the above-mentioned points, and provides a passband adjustment circuit that can be applied to a wireless communication device incorporating a PLL circuit for local signal generation and that reduces the need for frequency conversion circuits such as mixers. The purpose is to provide money.

The passband adjustment circuit according to the present invention has first and second filters provided before and after a bandpass filter. The entire basic circuit of the second frequency conversion means is as follows. 1st. The first frequency injected into the second frequency conversion means. The second local signal is transmitted to the first local signal. It is generated by a second voltage controlled oscillator.

In order to fully control the second voltage controlled oscillator, voltage variable means such as a variable resistor is provided. Analog-to-digital conversion means is provided to convert the amount of voltage change by the voltage variable means into a digital amount. Since the first voltage controlled oscillator is incorporated into the PLL Luzo together with a programmable counter and is controlled by digital program information, the system is configured to add the total amount of voltage change converted into a digital amount by the analog-to-digital conversion means to this program information. It's piled high.

Hereinafter, a second embodiment of the passband adjustment circuit according to the present invention will be described.
It is also explained in the figure.

In FIG. 2, 21 is a width variable resistor. The width variable resistor 21 increases or decreases the level of the control signal to the VCO 17 and the analog-to-digital converter 23 by operation. The variable resistor 22 for shifting also sends control signals to the analog-to-digital converter 24 and the VCo 18. In addition,
The control signal is an analog quantity such as a DC voltage to form a controlled quantity @ Analog-to-digital converters 23 and 24 convert the control signals inputted from the width variable resistor 21 and the shift variable resistor 22 into digital needles, and convert them into digital needles. a s 24
It is output to the digital adder 25 via a.

The digital adder 23 receives the program information formed by the pulse integration counter 15 via the data bus 15a, and receives this program information and the data buses 23a, 2.
4a's digital ffi' is added and the glogram information including pass band adjustment information is obtained as f"-Tahas 25 a f
The signal is sent to the programmable counter 14 of the PLL circuit 8 via the PLL circuit 8.

Here, if an oscillation signal that does not shift is injected into the local side terminals 5m and 7a, the passband width is normal and the center frequency of the passband does not change. When the frequency adjustment dial 20 is rotated in the normal or reverse direction, a calculated pulse is sent from the pulse generator 16 to the i4 pulse integrating counter 15, and the pulse integrating counter 15 forms all the program information in accordance with this integrated pulse.

The programmable counter 14 of the PLL circuit 8 divides the frequency of the oscillation signal of the vCO (not shown) provided in the PLL loop with a frequency division ratio according to the program information formed by the pulse adjustment counter 15.

Therefore, the frequency of the oscillation signal of the local side terminal 3a is determined following the operation of the frequency adjustment dial 20, and a desired signal can be selected.

Quiz variable resistor 21fjI on operation panel 19: Operate. If the reference potential point is set to the normal control signal level, the tBlj control signal level increases by operation, and mixers 3 and 5
The frequency of the oscillation signal shifts. Note that the direction of increase/decrease in this shift and the amount of shift are determined so that the frequency of the received signal fl does not change. Further, for the sake of explanation, if the deviation is assumed to be in the frequency increasing direction, the frequency of the oscillation signal of the VCO 17 increases as the control signal level increases. Further, the analog-to-digital converter 23 converts the amount of increase in the control signal level into a digital amount and sends it to the digital adder 25. Therefore, the program information sent from the digital adder 25 to the programmable counter 14 of the PLL circuit 8 includes the increase in the control signal level formed by the width variable resistor 21, and is injected into the mixer 3. The frequency of the oscillated signal increases more than in the normal case. For this reason, the frequencies that all pass through the band/fourth filter 4 are shifted from those in the normal case. In addition, since the oscillation signal of the mixer 5 is also shifted compared to the normal case, the two shifts cancel each other out and return to the normal frequency. has moved. Therefore, since the frequency width passing through the band/yas filter changes by the amount of the above movement, the width function can be obtained by operating in a direction narrower than in the normal case. Furthermore, when the shift variable resistor 22 is fully operated, the frequency of the oscillation signal generated by C018 shifts. At the same time, the analog-to-digital converter 24 converts the increase in the control signal level caused by the variable shift resistor 22 into a digital amount and sends it to the digital adder 25 via the data bus 24 a f. The digital adder 25 separately sends the program information formed by the pulse integration counter 15, the increment due to the width variable resistor 21, and the increment due to the shift variable resistor 22 to the program pull counter 14. Therefore, the frequency of the oscillation signal injected into the mixer 3 corresponds to the frequency adjustment dial 20, the width variable resistor 21, and the shift variable resistor 22. In this case, the frequency of the oscillation signal injected into the mixer 5 remains shifted by the operation of the width variable resistor 21, so the frequency widths of the bandpass filter 4, mixer 5, and bandpass filter 60 do not change. In terms of operation, the shift operation is the same as when the bandpass filter 4 is replaced with 6 and the mixer 4 is replaced with demodulator 7.

In the above embodiment, the amounts of change in the width variable resistor 21 and the shift variable resistor 22 are each converted into digital amounts and then added by the digital adder 25, but the amounts of change in both are added as analog amounts, The added analog quantity may be converted into a digital quantity. In this case, the number of analog-to-digital converters can be reduced by one, but an additional analog adder is required.

The passband adjustment circuit according to the present invention has first and second filters provided before and after a bandpass filter. The first frequency conversion means is related to the second frequency conversion means. When the frequency of the second local signal is changed using control information consisting of a digital quantity and an analog quantity, the other ilj control information consisting of an analog quantity is converted into a digital quantity and added. Therefore, it has the advantage that frequencies can be added together by adding digital quantities. Therefore, it is possible to reduce the number of mixers and the like involved in frequency conversion, and it is possible to prevent the occurrence of snorias caused by the mixers and the like.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional passband adjustment circuit, and FIG. 2 is a diagram showing an embodiment of the passband adjustment circuit of the present invention. 2 is an RF unit), 3-5 is a mixer, 4 and 6 are band pass filters, 7 is a demodulator, and 8 is a P
LL circuit, 9 is a phase comparator, 10 is a low-pass filter,
11.17.1R is a VCo, 14 is a programmable counter, 15 is a pulse integration counter, and 16 is NoJ? 19 is the operation channel, 20 is the frequency adjustment dial, 21 is the variable resistance for width, 22 is the variable resistance for shift,
23 and 24 are analog-to-digital converters, and 25 is a digital adder. Patent applicant Yaesu Musen Co., Ltd. Figure 1

Claims (1)

[Claims] 1. The first filter is installed before and after the bandpass filter. a second frequency conversion means; a first frequency injected into the first and second frequency conversion means; The first oscillator generates a second local signal. a second voltage controlled oscillator, a voltage variable means for controlling the second voltage controlled oscillator, and an output of the second voltage controlled oscillator which is changed according to the voltage variable means; a third frequency conversion means for mixing the output; a PLL circuit including the first voltage controlled oscillator, the third frequency converter, and a programmable counter in a PLL loop; and a program that determines a frequency division ratio of the programmable counter. A pulse integration counter that generates information, a pulse generation circuit that supplies an integration pulse to the pulse integration counter, and a passband adjustment circuit that is fully equipped with the analog-to-digital conversion means,
digital addition means for fully adding up the digital quantity converted by the analog-to-digital conversion means and the digital quantity accumulated by the pulse integration counter; and the programmable counter which uses the digital quantity added by the digital addition means as the program information. 5. A passband adjustment circuit comprising: (5) the third frequency conversion means is removed from the PLL loop.