JPH043505A - Voltage-frequency conversion circuit - Google Patents

Abstract

PURPOSE:To attain high performance and high stability and to reduce the cost by supplying a digital signal corresponding to an input signal to a frequency division control terminal of a variable frequency divider to vary the frequency division ratio, thereby varying the output of a phase comparator and the output frequency of a voltage controlled oscillator. CONSTITUTION:A PLL(phase locked loop) circuit 7a consists of a phase comparator 8a, a low pass filter 9a, a VCO(voltage controlled oscillator) 10a and a variable frequency divider 11a. A PLL circuit 7b is constituted similarly. Then the variable frequency divider 11a (11b) frequency-divides an output frequency of the VCO 10a (10b) having a frequency division ratio designated by the digital signal and the phase comparator 8a (8b) outputs a signal corresponding to a difference between a reference frequency give from a reference frequency signal source 12 and a frequency given from the variable frequency divider 11a (11b). The output is smoothed by a low pass filter 9a (9b) and the input to the VCO 10a (10b) an the VCO 10a (10b) generates an output having a frequency corresponding to the input voltage. Thus, high performance and high stability are attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a voltage-frequency conversion circuit suitable for an FM (frequency modulation) recording type magnetic recording device (mainly a measurement data recorder).

[Prior Art] A voltage-frequency conversion circuit of a conventional FM recording type data recorder is configured to change the oscillation frequency by controlling the charging current of a capacitor in an astable multibiflator using an input voltage.

[Problems to be Solved by the Invention] By the way, a conventional voltage-frequency conversion circuit is basically an analog circuit and consists of many parts. Therefore, variations in the electrical characteristics and temperature characteristics of individual components affect the overall electrical characteristics and temperature characteristics, making it difficult to obtain a highly stable and high-performance voltage-frequency conversion circuit.

In addition, in a multi-channel data recorder, a voltage-frequency conversion circuit is provided for each channel to be drawn.
Many adjustments were required to obtain the desired properties.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a voltage-frequency conversion circuit that can achieve high performance, high stability, and low cost.

[Means for Solving the Problems] The present invention for achieving the above object includes a reference frequency signal source, at least a phase comparator, a low-pass filter, a voltage controlled oscillator, and a variable frequency divider, and the phase comparator one input terminal is connected to the reference frequency signal source, the other input terminal is connected to the variable frequency divider, the low-pass filter is connected between the phase comparator and the voltage controlled oscillator, The variable frequency divider is connected between a PLL circuit connected to the voltage controlled oscillator, an input circuit for inputting an analog signal, and a division ratio control terminal of the variable frequency divider. The invention relates to a voltage-frequency conversion circuit consisting of an analog-to-digital converter.

In addition, when performing voltage-frequency conversion on a plurality of analog signals, the outputs of the plurality of input circuits may be time-division multiplexed using a multiplexer and provided to the analog-to-digital converter, as shown in claim 2. is desirable.

[Function] The variable frequency divider in the voltage-frequency conversion circuit of the present invention is
For example, in a programmable divider, the frequency division ratio is changed by applying a digital signal corresponding to an analog signal (input signal) to this frequency division control terminal. As a result, the output of the phase comparator changes, and the output frequency of the voltage controlled oscillator also changes. Thereby, a change in the output frequency corresponding to a change in the voltage level of the input analog signal can be obtained.

In the invention of claim 2, the analog-to-digital converter is used in a time-division manner. As a result, not only is it possible to reduce the number of analog-to-digital converters to one or a small number, but the man-hours for adjusting the analog-to-digital converters are also significantly reduced, and the number of analog-to-digital converters in multiple channels can be reduced. There will be less variation.

[Embodiment] Next, an FM recording type multi-channel data recorder according to an embodiment of the present invention will be explained with reference to FIG.

The first and second input circuits 1a and 1b are circuits for providing first and second analog signals to be recorded on the magnetic tape recording medium 2. Although only two input circuits 1a and 1b are shown here for convenience of illustration, an actual multi-channel data recorder has many more input circuits.

Input circuit la.

The multiplexer 3 to which 1b is connected time-division multiplexes the first and second analog signals and outputs the resultant signals.

An A/D (analog-to-digital) converter 4 connected to the multiplexer 3 converts the first and second analog signals into first and second digital signals in a time-sharing manner.

First and second latch circuits 5a and 5b connected to the A/D converter 4 hold the first and second digital signals, respectively.

The timing control circuit 6 provides a control signal (timing signal) that causes the multiplexer 3, the A/D converter 4, and the first and second latch circuits 5a and 5b to operate in a mutually related manner.

First PLL (phase locked loop) circuit 7
a is the first phase comparator 8a and the first low-pass filter 9
a, a first VCO (voltage controlled oscillator) 10a, and a variable frequency divider 11a with a first programmable divider, and the second PLL circuit 7b similarly includes a second phase comparator 8b and a second low-pass filter 9b and second VCO
lob and a variable frequency divider 11b consisting of a second programmable divider. First and second PL
One input terminal of the phase comparators 8a, 8b of the L circuits 7a, 7b is connected to the reference frequency signal source 12, respectively, and the other input terminal is connected to the variable frequency divider 11a, 11b, respectively. The output terminals of the respective phase comparators 8a and 8b are connected to VCOloa and 10b via low-pass filters 9a and 9b.
l: connected, and the output terminal of VCOloa, 10b is connected to the variable frequency divider 11a, 111b, and via the first and second frequency dividers 13a, 13b and the first and second recording circuits 14a, 14b. Signal conversion magnetic head 15a11
5b.

The variable frequency dividers 11a and llb have variable control terminals 16a and 16b of a plurality of bits, and are configured so that the frequency division ratio changes when the digital signal applied thereto changes.

The first and second latch circuits 5a and 5b are connected to variable control terminals 16a and 16b of variable frequency dividers 11a and llb, respectively, by multi-bit transmission lines.

[Operation] The first and second analog signals (input signals) of the first and second input circuits 1a and 1b are time-division multiplexed by the multiplexer 3 and provided to the A/D converter 4. From the A/D converter 4, a time-division multiplexed digital signal corresponding to the time-division multiplexed analog signal is obtained. For example, the first signal included in a time division multiplexed digital signal consisting of 16 bits
and the second digital signal are read into the first and second latch circuits 5a and 5b. The A/D converter 4 has a built-in sample and hold circuit and converts the analog signal into a digital signal, and the first and second digital signals are time-divisionally arranged and output, so the first and second latch circuits 5
a and 5b read the first and second digital signals in synchronization with the transmission period of the first and second digital signals. This makes it possible to extract the first and second digital signals from the time division multiplexed signal. The extracted first and second digital signals are held in the latch circuit 58% 5b until the next sample is input, and are output to the variable control terminal 16.
a, 16b.

The variable frequency dividers 11a and 11b have a frequency division ratio specified by the first and second digital signals Vc.

The output frequency of 10a and 10b is divided and the phase comparator 8a
, send to 8b.

The phase comparators 8a and 8b output signals corresponding to the difference between the reference frequency given from the reference frequency signal source 12 and the frequency given from the variable frequency dividers 11a and 11b. The outputs of the phase comparators 8a and 8b are passed through a low-pass filter 9a%.
9b is smoothed to become the human power of vCOIQa, 10b, and VColoa, 10b generates an output having a frequency corresponding to the input voltage.

The output frequency signal of VCOloa, 10b is sent to the frequency divider 13a.
, 13b and the head 15 via the recording circuits 14a and 14b.
a, 15b, and recorded on the recording medium 2.

When the values of the first and second digital signals change in response to changes in the voltage levels of the first and second analog signals,
The frequency division ratio (1/N) of variable frequency dividers 11a and llb changes, and the output frequencies of VCOloa and 10b also change. Note that the output frequency is determined by the product of the reference frequency Fr and the N value.

To explain the operation of each part using numerical values, the input analog signal of the first and second input circuits 1a and 1b is +1.500.
When the frequency changes from V to -1,500V, the frequency division ratios of the variable frequency dividers 11a and 11b change from 1/200 to 1/800, and the output frequencies of vColoa and 10b change to 8.
It varies in the range of 6400MHz to 34.5600MHz. In addition, the center frequency of VCO10a and 10b is set to 2
If the frequency is 1°6000 MHz, the modulation depth is -60.0 ~
+60.0%.

This embodiment has the following effects.

(1) The output frequency is the reference frequency Fr and the division ratio 1/N.
Based on (determined by FrXN, the variable frequency divider 11a,
The correspondence (linearity) between the digital signal as a control signal of llb and the output frequency is extremely good. Further, the PLL circuits 7a and 7b have good temperature characteristics. The A/D converter 4 is essentially the only circuit that affects the linearity and temperature characteristics in voltage-frequency conversion. Therefore, a highly stable and high performance voltage-frequency conversion circuit can be easily obtained.

(2) Since the output frequency of VCOloa and 10b is known in advance as mentioned above, it is not necessary to measure it with a frequency counter, and the voltage-frequency conversion characteristics can be adjusted using only a voltmeter that measures the level of the input analog signal. That is, it becomes possible to adjust the analog signal level in the input circuits 1a, 1b or the A/D converter 4, and the adjustment work becomes easier.

Therefore, cost reduction is achieved.

(3) When recording the calibration signal (calibration signal) on the recording medium 2, the calibration voltage (for example +IV
, OV, -IV) is no longer required. Since the frequency division ratio for obtaining the frequency corresponding to the calibration voltage is known in advance, the frequency signal for calibration can be obtained by simply setting the frequency division ratio of the variable frequency dividers 11a and 11b to a value corresponding to the calibration voltage. Obtainable.

(4) Since multiple input analog signals are time-division multiplexed by the multiplexer 3 and A/D converted by the common A/D converter 4, it is possible to provide an A/D converter for each channel and adjust it. becomes unnecessary. Therefore, not only the circuit configuration is simplified, but also the number of adjustment steps is significantly reduced, thereby achieving cost reduction.

[Modifications] The present invention is not limited to the above-described embodiments, and, for example, the following modifications are possible.

(1) As shown in FIG. 2, it is possible to form one channel independently. In addition, in Figure 2, the first
Parts common to those in the figures are given the same reference numerals.

(2) The configuration can be such that the synchronization of the timing control signal supplied from the control circuit 6 is changed in accordance with the switching of the running speed of the recording medium 2.

[Effects of the Invention] As is clear from the above, according to the present invention, a high performance and highly stable voltage-frequency conversion circuit can be easily obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a multi-channel data recorder according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a modified voltage-frequency conversion circuit. la, lb...input circuit, 3...multiplexer,
4... A/D converter, 5a, 5b... latch circuit,
7a, 7b--PLL circuit, 8a, 8b--phase comparator, 9a, 9b--low pass filter, ICLa, 10
b...VCO, lla, llb...variable frequency divider.

Claims (1)

[Scope of Claims] [1] A reference frequency signal source, at least a phase comparator, a low-pass filter, a voltage controlled oscillator, and a variable frequency divider, wherein one input terminal of the phase comparator is connected to the reference frequency signal source. and the other input terminal is connected to the variable frequency divider, the low-pass filter is connected between the phase comparator and the voltage controlled oscillator, and the variable frequency divider is connected to the voltage controlled oscillator. A voltage comprising a connected PLL circuit, an input circuit for inputting an analog signal, and an analog-to-digital converter connected between the input circuit and the division ratio control terminal of the variable frequency divider. -Frequency conversion circuit. [2] includes a reference frequency signal source, at least a first phase comparator, a first low-pass filter, a first voltage-controlled oscillator, and a first variable frequency divider,
One input terminal of the first phase comparator is connected to the reference frequency signal source, the other input terminal is connected to the first variable frequency divider, and the first low-pass filter is connected to the first and the first voltage controlled oscillator, the first variable frequency divider is connected between a first PLL circuit connected to the first voltage controlled oscillator and at least a second PLL circuit. a phase comparator, a second low-pass filter, a second voltage controlled oscillator, and a second variable frequency divider, one input terminal of the second phase comparator is connected to the reference frequency signal source. , the other input terminal is connected to the second variable frequency divider, the second low-pass filter is connected between the second phase comparator and the second voltage controlled oscillator, and the second low-pass filter is connected between the second phase comparator and the second voltage controlled oscillator. The second variable frequency divider includes a second PLL circuit connected to the second voltage controlled oscillator, a first input circuit for inputting the first analog signal, and inputting the second analog signal. a multiplexer connected to the first and second input circuits to form a time-division multiplexed signal of the first and second analog signals; a multiplexer connected to the multiplexer; an analog-to-digital converter obtained from the analog-to-digital converter;
a first latch circuit that latches a first digital signal corresponding to the analog signal of and applies it to a frequency division control terminal of the first variable frequency divider of the first PLL circuit; and the analog-to-digital converter. said second obtained from
a second latch circuit that latches a second digital signal corresponding to the analog signal and supplies it to a frequency division control terminal of the second variable frequency divider of the second PLL circuit; .